diff --git a/fpga/constraints/soc.xdc b/fpga/constraints/soc.xdc index 65c8237..8b0cade 100644 --- a/fpga/constraints/soc.xdc +++ b/fpga/constraints/soc.xdc @@ -227,10 +227,19 @@ set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] -create_generated_clock -name cpu_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0] -create_generated_clock -name sys_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1] +# create_generated_clock -name cpu_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0] +# create_generated_clock -name sys_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1] -set_clock_groups -asynchronous -group [get_clocks cpu_clk] -group [get_clocks sys_clk] +# set_clock_groups -asynchronous -group [get_clocks cpu_clk] -group [get_clocks sys_clk] + +create_generated_clock -name cpu_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0] +create_generated_clock -name sys_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1] +create_generated_clock -name mlkem_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2] + +set_clock_groups -asynchronous \ + -group [get_clocks cpu_clk] \ + -group [get_clocks sys_clk] \ + -group [get_clocks mlkem_clk] set_input_delay -clock sys_clk -max 3 [get_ports {base_ram_data[*]}] set_input_delay -clock sys_clk -min 2 [get_ports {base_ram_data[*]}] diff --git a/fpga/vivado_reports_nodsp/cdc_mlkem_to_sys.rpt b/fpga/vivado_reports_nodsp/cdc_mlkem_to_sys.rpt new file mode 100644 index 0000000..bbd3e0b --- /dev/null +++ b/fpga/vivado_reports_nodsp/cdc_mlkem_to_sys.rpt @@ -0,0 +1,1924 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 +| Date : Sat Jul 11 09:20:56 2026 +| Host : fedora running 64-bit unknown +| Command : report_timing -from [get_clocks mlkem_clk] -to [get_clocks sys_clk] -delay_type max -max_paths 50 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/cdc_mlkem_to_sys.rpt +| Design : soc_top +| Device : 7a200t-fbg676 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Report + +Slack: inf + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 5.746ns (logic 0.642ns (11.174%) route 5.104ns (88.826%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.546ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.123ns + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 2.674 3.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1 + SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -5.674 -5.674 + propagated clock network latency + 3.551 -2.123 + +Slack: inf + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 5.746ns (logic 0.642ns (11.174%) route 5.104ns (88.826%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.546ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.123ns + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 2.674 3.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1 + SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -5.674 -5.674 + propagated clock network latency + 3.551 -2.123 + +Slack: inf + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Fast Process Corner) + Data Path Delay: 2.891ns (logic 0.260ns (8.995%) route 2.631ns (91.005%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.164ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.619ns + Source Clock Delay (SCD): -0.455ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.492 -0.455 + SLICE_X92Y102 FDCE 0.000 -0.455 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.204 -0.251 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 1.300 1.049 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.056 1.105 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 1.331 2.435 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1 + SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.229 -0.619 + +Slack: inf + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Fast Process Corner) + Data Path Delay: 2.891ns (logic 0.260ns (8.995%) route 2.631ns (91.005%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.164ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.619ns + Source Clock Delay (SCD): -0.455ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.492 -0.455 + SLICE_X92Y102 FDCE 0.000 -0.455 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.204 -0.251 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 1.300 1.049 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.056 1.105 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 1.331 2.435 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1 + SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.229 -0.619 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.364ns (logic 0.612ns (44.884%) route 0.752ns (55.116%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + SLICE_X64Y91 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O + net (fo=1, routed) 0.752 0.977 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.364ns (logic 0.612ns (44.884%) route 0.752ns (55.116%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + SLICE_X64Y91 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O + net (fo=1, routed) 0.752 0.977 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] + SLICE_X46Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.284ns (logic 0.612ns (47.657%) route 0.672ns (52.343%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 0.672 0.895 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.284ns (logic 0.612ns (47.657%) route 0.672ns (52.343%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 0.672 0.895 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0] + SLICE_X49Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.195ns (logic 0.595ns (49.811%) route 0.600ns (50.189%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 0.600 0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.195ns (logic 0.595ns (49.811%) route 0.600ns (50.189%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.207 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 0.600 0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] + SLICE_X50Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.183ns (logic 0.595ns (50.304%) route 0.588ns (49.696%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + SLICE_X64Y91 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 0.588 0.797 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.183ns (logic 0.595ns (50.304%) route 0.588ns (49.696%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + SLICE_X64Y91 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.209 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 0.588 0.797 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] + SLICE_X50Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.169ns (logic 0.612ns (52.356%) route 0.557ns (47.644%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.612ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O + net (fo=1, routed) 0.557 0.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.236 -0.612 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.169ns (logic 0.612ns (52.356%) route 0.557ns (47.644%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.612ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O + net (fo=1, routed) 0.557 0.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] + SLICE_X51Y85 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.236 -0.612 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.167ns (logic 0.612ns (52.454%) route 0.555ns (47.546%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 0.555 0.779 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.167ns (logic 0.612ns (52.454%) route 0.555ns (47.546%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 0.555 0.779 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] + SLICE_X50Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.166ns (logic 0.480ns (41.172%) route 0.686ns (58.828%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.092 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O + net (fo=1, routed) 0.686 0.778 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.166ns (logic 0.480ns (41.172%) route 0.686ns (58.828%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.092 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O + net (fo=1, routed) 0.686 0.778 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] + SLICE_X46Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.160ns (logic 0.612ns (52.737%) route 0.548ns (47.263%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X66Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.548 0.771 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.160ns (logic 0.612ns (52.737%) route 0.548ns (47.263%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X66Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.548 0.771 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] + SLICE_X50Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.139ns (logic 0.612ns (53.734%) route 0.527ns (46.266%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X66Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 0.527 0.750 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.139ns (logic 0.612ns (53.734%) route 0.527ns (46.266%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X66Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 0.527 0.750 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] + SLICE_X50Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.128ns (logic 0.595ns (52.742%) route 0.533ns (47.258%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X66Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 0.533 0.739 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.128ns (logic 0.595ns (52.742%) route 0.533ns (47.258%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X66Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 0.533 0.739 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] + SLICE_X49Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.122ns (logic 0.595ns (53.042%) route 0.527ns (46.958%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O + net (fo=1, routed) 0.527 0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.122ns (logic 0.595ns (53.042%) route 0.527ns (46.958%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O + net (fo=1, routed) 0.527 0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] + SLICE_X49Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.103ns (logic 0.482ns (43.685%) route 0.621ns (56.315%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O + net (fo=1, routed) 0.621 0.714 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.103ns (logic 0.482ns (43.685%) route 0.621ns (56.315%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.093 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O + net (fo=1, routed) 0.621 0.714 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] + SLICE_X49Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.093ns (logic 0.485ns (44.377%) route 0.608ns (55.623%)) + Logic Levels: 0 + Clock Path Skew: -0.222ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O + net (fo=1, routed) 0.608 0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10] + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.093ns (logic 0.485ns (44.377%) route 0.608ns (55.623%)) + Logic Levels: 0 + Clock Path Skew: -0.222ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.097 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O + net (fo=1, routed) 0.608 0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10] + SLICE_X48Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.073ns (logic 0.595ns (55.460%) route 0.478ns (44.540%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.478 0.684 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.073ns (logic 0.595ns (55.460%) route 0.478ns (44.540%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.478 0.684 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] + SLICE_X48Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.071ns (logic 0.595ns (55.545%) route 0.476ns (44.455%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X66Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 0.476 0.682 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.071ns (logic 0.595ns (55.545%) route 0.476ns (44.455%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X66Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 0.476 0.682 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] + SLICE_X48Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.064ns (logic 0.485ns (45.566%) route 0.579ns (54.434%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X66Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O + net (fo=1, routed) 0.579 0.675 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.064ns (logic 0.485ns (45.566%) route 0.579ns (54.434%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X66Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O + net (fo=1, routed) 0.579 0.675 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] + SLICE_X50Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.051ns (logic 0.485ns (46.153%) route 0.566ns (53.847%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O + net (fo=1, routed) 0.566 0.662 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.051ns (logic 0.485ns (46.153%) route 0.566ns (53.847%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O + net (fo=1, routed) 0.566 0.662 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4] + SLICE_X50Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.028ns (logic 0.485ns (47.163%) route 0.543ns (52.837%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O + net (fo=1, routed) 0.543 0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.028ns (logic 0.485ns (47.163%) route 0.543ns (52.837%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O + net (fo=1, routed) 0.543 0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] + SLICE_X48Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.026ns (logic 0.482ns (46.972%) route 0.544ns (53.028%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O + net (fo=1, routed) 0.544 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.026ns (logic 0.482ns (46.972%) route 0.544ns (53.028%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.093 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O + net (fo=1, routed) 0.544 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] + SLICE_X48Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.007ns (logic 0.491ns (48.781%) route 0.516ns (51.219%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.103 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O + net (fo=1, routed) 0.516 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.007ns (logic 0.491ns (48.781%) route 0.516ns (51.219%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.103 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O + net (fo=1, routed) 0.516 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] + SLICE_X46Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.001ns (logic 0.485ns (48.445%) route 0.516ns (51.555%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X66Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O + net (fo=1, routed) 0.516 0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.001ns (logic 0.485ns (48.445%) route 0.516ns (51.555%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X66Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O + net (fo=1, routed) 0.516 0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] + SLICE_X50Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.998ns (logic 0.480ns (48.113%) route 0.518ns (51.887%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O + net (fo=1, routed) 0.518 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.998ns (logic 0.480ns (48.113%) route 0.518ns (51.887%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.091 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O + net (fo=1, routed) 0.518 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] + SLICE_X50Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.239 -0.609 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.998ns (logic 0.491ns (49.223%) route 0.507ns (50.777%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O + net (fo=1, routed) 0.507 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.998ns (logic 0.491ns (49.223%) route 0.507ns (50.777%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.102 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O + net (fo=1, routed) 0.507 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2] + SLICE_X50Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + + + + diff --git a/fpga/vivado_reports_nodsp/cdc_sys_to_mlkem.rpt b/fpga/vivado_reports_nodsp/cdc_sys_to_mlkem.rpt new file mode 100644 index 0000000..45a15fe --- /dev/null +++ b/fpga/vivado_reports_nodsp/cdc_sys_to_mlkem.rpt @@ -0,0 +1,1932 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 +| Date : Sat Jul 11 09:20:56 2026 +| Host : fedora running 64-bit unknown +| Command : report_timing -from [get_clocks sys_clk] -to [get_clocks mlkem_clk] -delay_type max -max_paths 50 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/cdc_sys_to_mlkem.rpt +| Design : soc_top +| Device : 7a200t-fbg676 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Report + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 10.980ns (logic 0.668ns (6.084%) route 10.312ns (93.916%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.301ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.273ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.702 -2.574 + SLICE_X22Y139 FDCE 0.000 -2.574 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.199 8.406 pll_clk.u_rst_mlkem/p_0_in + SLICE_X96Y101 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -5.674 -5.674 + propagated clock network latency + 3.402 -2.273 + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 10.561ns (logic 0.668ns (6.325%) route 9.893ns (93.675%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.297ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.702 -2.574 + SLICE_X22Y139 FDCE 0.000 -2.574 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.780 7.987 pll_clk.u_rst_mlkem/p_0_in + SLICE_X92Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -5.674 -5.674 + propagated clock network latency + 3.398 -2.277 + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Fast Process Corner) + Data Path Delay: 5.593ns (logic 0.261ns (4.667%) route 5.332ns (95.333%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.267ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.679ns + Source Clock Delay (SCD): -0.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.535 -0.412 + SLICE_X22Y139 FDCE 0.000 -0.412 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.204 -0.208 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 1.683 1.475 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.057 1.532 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 3.649 5.181 pll_clk.u_rst_mlkem/p_0_in + SLICE_X96Y101 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.169 -0.679 + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Fast Process Corner) + Data Path Delay: 5.410ns (logic 0.261ns (4.824%) route 5.149ns (95.176%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.268ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.680ns + Source Clock Delay (SCD): -0.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.535 -0.412 + SLICE_X22Y139 FDCE 0.000 -0.412 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.204 -0.208 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 1.683 1.475 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.057 1.532 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 3.466 4.998 pll_clk.u_rst_mlkem/p_0_in + SLICE_X92Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.643ns (logic 0.668ns (10.055%) route 5.975ns (89.945%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.294ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.702 -2.574 + SLICE_X22Y139 FDCE 0.000 -2.574 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 2.863 4.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in + SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -5.674 -5.674 + propagated clock network latency + 3.395 -2.280 + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.643ns (logic 0.668ns (10.055%) route 5.975ns (89.945%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.294ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.702 -2.574 + SLICE_X22Y139 FDCE 0.000 -2.574 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 2.863 4.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in + SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -5.674 -5.674 + propagated clock network latency + 3.395 -2.280 + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Fast Process Corner) + Data Path Delay: 3.391ns (logic 0.261ns (7.696%) route 3.130ns (92.304%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.268ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.680ns + Source Clock Delay (SCD): -0.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.535 -0.412 + SLICE_X22Y139 FDCE 0.000 -0.412 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.204 -0.208 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 1.683 1.475 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.057 1.532 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 1.448 2.979 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in + SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Fast Process Corner) + Data Path Delay: 3.391ns (logic 0.261ns (7.696%) route 3.130ns (92.304%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.268ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.680ns + Source Clock Delay (SCD): -0.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.535 -0.412 + SLICE_X22Y139 FDCE 0.000 -0.412 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.204 -0.208 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 1.683 1.475 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.057 1.532 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 1.448 2.979 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in + SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.143ns (logic 0.612ns (53.534%) route 0.531ns (46.466%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + SLICE_X70Y97 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK + SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/O + net (fo=1, routed) 0.531 0.756 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[36] + SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.143ns (logic 0.612ns (53.534%) route 0.531ns (46.466%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + SLICE_X70Y97 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK + SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/O + net (fo=1, routed) 0.531 0.756 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[36] + SLICE_X67Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.059ns (logic 0.612ns (57.810%) route 0.447ns (42.190%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X44Y81 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK + SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.447 0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] + SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.059ns (logic 0.612ns (57.810%) route 0.447ns (42.190%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X44Y81 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK + SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.447 0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] + SLICE_X45Y83 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.002ns (logic 0.595ns (59.409%) route 0.407ns (40.591%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + SLICE_X52Y83 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.407 0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7] + SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.002ns (logic 0.595ns (59.409%) route 0.407ns (40.591%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + SLICE_X52Y83 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.208 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.407 0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7] + SLICE_X54Y85 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.994ns (logic 0.612ns (61.564%) route 0.382ns (38.436%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + SLICE_X68Y97 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK + SLICE_X68Y97 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O + net (fo=1, routed) 0.382 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48] + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.231 -0.617 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.994ns (logic 0.612ns (61.564%) route 0.382ns (38.436%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + SLICE_X68Y97 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK + SLICE_X68Y97 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O + net (fo=1, routed) 0.382 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48] + SLICE_X70Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.231 -0.617 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.982ns (logic 0.612ns (62.344%) route 0.370ns (37.656%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.384ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.563 -0.384 + SLICE_X62Y93 RAMD32 0.000 -0.384 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK + SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O + net (fo=1, routed) 0.370 0.597 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0] + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.234 -0.614 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.982ns (logic 0.612ns (62.344%) route 0.370ns (37.656%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.384ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.563 -0.384 + SLICE_X62Y93 RAMD32 0.000 -0.384 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK + SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.228 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O + net (fo=1, routed) 0.370 0.597 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0] + SLICE_X65Y96 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.234 -0.614 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.966ns (logic 0.612ns (63.335%) route 0.354ns (36.665%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.611ns + Source Clock Delay (SCD): -0.380ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.567 -0.380 + SLICE_X56Y93 RAMD32 0.000 -0.380 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK + SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.232 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O + net (fo=1, routed) 0.354 0.586 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36] + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.237 -0.611 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.966ns (logic 0.612ns (63.335%) route 0.354ns (36.665%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.611ns + Source Clock Delay (SCD): -0.380ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.567 -0.380 + SLICE_X56Y93 RAMD32 0.000 -0.380 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK + SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O + net (fo=1, routed) 0.354 0.586 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36] + SLICE_X56Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.237 -0.611 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.963ns (logic 0.491ns (50.975%) route 0.472ns (49.025%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.384ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.563 -0.384 + SLICE_X62Y93 RAMD32 0.000 -0.384 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK + SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.107 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O + net (fo=1, routed) 0.472 0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2] + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.234 -0.614 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.963ns (logic 0.491ns (50.975%) route 0.472ns (49.025%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.384ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.563 -0.384 + SLICE_X62Y93 RAMD32 0.000 -0.384 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK + SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.107 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O + net (fo=1, routed) 0.472 0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2] + SLICE_X65Y96 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.234 -0.614 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.957ns (logic 0.595ns (62.185%) route 0.362ns (37.815%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + SLICE_X64Y94 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.362 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13] + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.231 -0.617 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.957ns (logic 0.595ns (62.185%) route 0.362ns (37.815%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + SLICE_X64Y94 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.210 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.362 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13] + SLICE_X70Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.231 -0.617 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.957ns (logic 0.482ns (50.382%) route 0.475ns (49.618%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + SLICE_X64Y94 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O + net (fo=1, routed) 0.475 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15] + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.231 -0.617 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.957ns (logic 0.482ns (50.382%) route 0.475ns (49.618%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + SLICE_X64Y94 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.097 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O + net (fo=1, routed) 0.475 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15] + SLICE_X70Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.231 -0.617 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.954ns (logic 0.482ns (50.537%) route 0.472ns (49.463%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + SLICE_X52Y83 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.095 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/O + net (fo=1, routed) 0.472 0.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[9] + SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.954ns (logic 0.482ns (50.537%) route 0.472ns (49.463%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + SLICE_X52Y83 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.095 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/O + net (fo=1, routed) 0.472 0.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[9] + SLICE_X54Y86 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.940ns (logic 0.595ns (63.287%) route 0.345ns (36.713%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X44Y80 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.345 0.551 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1] + SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.940ns (logic 0.595ns (63.287%) route 0.345ns (36.713%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + SLICE_X44Y80 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.345 0.551 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1] + SLICE_X42Y80 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.935ns (logic 0.612ns (65.444%) route 0.323ns (34.556%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + SLICE_X64Y94 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O + net (fo=1, routed) 0.323 0.550 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12] + SLICE_X67Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.935ns (logic 0.612ns (65.444%) route 0.323ns (34.556%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + SLICE_X64Y94 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.227 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O + net (fo=1, routed) 0.323 0.550 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12] + SLICE_X67Y94 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.927ns (logic 0.595ns (64.162%) route 0.332ns (35.838%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X44Y81 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 0.332 0.539 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] + SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.927ns (logic 0.595ns (64.162%) route 0.332ns (35.838%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + SLICE_X44Y81 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.207 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 0.332 0.539 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] + SLICE_X45Y83 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.925ns (logic 0.595ns (64.303%) route 0.330ns (35.697%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.615ns + Source Clock Delay (SCD): -0.391ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.556 -0.391 + SLICE_X46Y79 RAMD32 0.000 -0.391 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.204 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 0.330 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[7] + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.925ns (logic 0.595ns (64.303%) route 0.330ns (35.697%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.615ns + Source Clock Delay (SCD): -0.391ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.556 -0.391 + SLICE_X46Y79 RAMD32 0.000 -0.391 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.204 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 0.330 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[7] + SLICE_X51Y81 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.919ns (logic 0.595ns (64.745%) route 0.324ns (35.255%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + SLICE_X64Y93 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.324 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[7] + SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.919ns (logic 0.595ns (64.745%) route 0.324ns (35.255%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + SLICE_X64Y93 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.210 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.324 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[7] + SLICE_X67Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.908ns (logic 0.612ns (67.424%) route 0.296ns (32.576%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + SLICE_X70Y98 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK + SLICE_X70Y98 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O + net (fo=1, routed) 0.296 0.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42] + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.908ns (logic 0.612ns (67.424%) route 0.296ns (32.576%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + SLICE_X70Y98 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK + SLICE_X70Y98 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O + net (fo=1, routed) 0.296 0.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42] + SLICE_X72Y97 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.911ns (logic 0.612ns (67.168%) route 0.299ns (32.832%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.615ns + Source Clock Delay (SCD): -0.391ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.556 -0.391 + SLICE_X46Y79 RAMD32 0.000 -0.391 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK + SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 0.299 0.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6] + SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.911ns (logic 0.612ns (67.168%) route 0.299ns (32.832%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.615ns + Source Clock Delay (SCD): -0.391ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.556 -0.391 + SLICE_X46Y79 RAMD32 0.000 -0.391 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK + SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 0.299 0.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6] + SLICE_X49Y81 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.889ns (logic 0.482ns (54.189%) route 0.407ns (45.811%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + SLICE_X52Y84 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/O + net (fo=1, routed) 0.407 0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[3] + SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.889ns (logic 0.482ns (54.189%) route 0.407ns (45.811%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + SLICE_X52Y84 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.096 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/O + net (fo=1, routed) 0.407 0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[3] + SLICE_X54Y85 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.866ns (logic 0.595ns (68.739%) route 0.271ns (31.261%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + SLICE_X52Y85 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + SLICE_X52Y85 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.271 0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[13] + SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.866ns (logic 0.595ns (68.739%) route 0.271ns (31.261%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + SLICE_X52Y85 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + SLICE_X52Y85 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.210 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.271 0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[13] + SLICE_X54Y86 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.858ns (logic 0.480ns (55.963%) route 0.378ns (44.037%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + SLICE_X52Y83 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/O + net (fo=1, routed) 0.378 0.471 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[11] + SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.858ns (logic 0.480ns (55.963%) route 0.378ns (44.037%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + SLICE_X52Y83 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.093 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/O + net (fo=1, routed) 0.378 0.471 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[11] + SLICE_X54Y85 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.849ns (logic 0.612ns (72.044%) route 0.237ns (27.956%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + SLICE_X64Y93 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK + SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/O + net (fo=1, routed) 0.237 0.464 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[6] + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.234 -0.614 + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.849ns (logic 0.612ns (72.044%) route 0.237ns (27.956%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + SLICE_X64Y93 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK + SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.227 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/O + net (fo=1, routed) 0.237 0.464 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[6] + SLICE_X65Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.234 -0.614 + + + + diff --git a/fpga/vivado_reports_nodsp/clock_interaction.rpt b/fpga/vivado_reports_nodsp/clock_interaction.rpt index a8a58a3..0a18da3 100644 --- a/fpga/vivado_reports_nodsp/clock_interaction.rpt +++ b/fpga/vivado_reports_nodsp/clock_interaction.rpt @@ -1,28 +1,39 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 +<<<<<<< Updated upstream +| Date : Fri Jul 10 04:14:55 2026 +======= +| Date : Sat Jul 11 09:20:56 2026 +>>>>>>> Stashed changes | Host : fedora running 64-bit unknown -| Command : report_clock_interaction -file /home/fallensigh/vivado_reports_nodsp/clock_interaction.rpt +| Command : report_clock_interaction -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clock_interaction.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------------------- Clock Interaction Report Clock Interaction Table ----------------------- - WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock -From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints ------------------ ----------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- ------------------- -cpu_clk cpu_clk rise - rise 2.72 0.00 0 17264 30.32 Clean Timed -cpu_clk sys_clk 0 162 Ignored Asynchronous Groups -mlkem_clk_clk_pll mlkem_clk_clk_pll rise - rise 10.81 0.00 0 74168 40.00 Clean Timed -mlkem_clk_clk_pll sys_clk rise - rise 11.25 0.00 0 61 20.00 Clean Timed -sys_clk cpu_clk 0 59 Ignored Asynchronous Groups -sys_clk mlkem_clk_clk_pll rise - rise 9.16 0.00 0 112 20.00 Clean Timed -sys_clk sys_clk rise - rise 0.17 0.00 0 23704 20.00 Clean Timed + WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock +From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints +---------------- ---------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- ------------------- +<<<<<<< Updated upstream +cpu_clk cpu_clk rise - rise 1.51 0.00 0 17264 30.32 Clean Timed +cpu_clk sys_clk 0 154 Ignored Asynchronous Groups +sys_clk cpu_clk 0 59 Ignored Asynchronous Groups +sys_clk sys_clk rise - rise 0.15 0.00 0 96069 20.00 Clean Timed +======= +cpu_clk cpu_clk rise - rise 0.74 0.00 0 17264 30.00 Clean Timed +cpu_clk sys_clk 0 162 Ignored Asynchronous Groups +mlkem_clk mlkem_clk rise - rise 0.07 0.00 0 48386 13.00 Clean Timed +mlkem_clk sys_clk 0 61 Ignored Asynchronous Groups +sys_clk cpu_clk 0 59 Ignored Asynchronous Groups +sys_clk mlkem_clk 0 112 Ignored Asynchronous Groups +sys_clk sys_clk rise - rise 0.12 0.00 0 23193 20.00 Clean Timed +>>>>>>> Stashed changes diff --git a/fpga/vivado_reports_nodsp/clocks.rpt b/fpga/vivado_reports_nodsp/clocks.rpt index 7ce6dda..dee476d 100644 --- a/fpga/vivado_reports_nodsp/clocks.rpt +++ b/fpga/vivado_reports_nodsp/clocks.rpt @@ -1,13 +1,17 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 +<<<<<<< Updated upstream +| Date : Fri Jul 10 04:14:54 2026 +======= +| Date : Sat Jul 11 09:20:56 2026 +>>>>>>> Stashed changes | Host : fedora running 64-bit unknown -| Command : report_clocks -file /home/fallensigh/vivado_reports_nodsp/clocks.rpt +| Command : report_clocks -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clocks.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 --------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------- Clock Report @@ -21,12 +25,16 @@ Attributes I: Inverted S: Pin phase-shifted with Latency mode -Clock Period(ns) Waveform(ns) Attributes Sources -clk 20.000 {0.000 10.000} P {clk} -clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT} -cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} -mlkem_clk_clk_pll 40.000 {0.000 20.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2} -sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1} +Clock Period(ns) Waveform(ns) Attributes Sources +clk 20.000 {0.000 10.000} P {clk} +clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT} +<<<<<<< Updated upstream +cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} +======= +cpu_clk 30.000 {0.000 15.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} +mlkem_clk 13.000 {0.000 6.500} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2} +>>>>>>> Stashed changes +sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1} ==================================================== @@ -43,16 +51,19 @@ Generated Clock : cpu_clk Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Master Clock : clk Edges : {1 2 3} -Edge Shifts(ns) : {0.000 5.161 10.323} +Edge Shifts(ns) : {0.000 5.000 10.000} Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} -Generated Clock : mlkem_clk_clk_pll +<<<<<<< Updated upstream +======= +Generated Clock : mlkem_clk Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Master Clock : clk Edges : {1 2 3} -Edge Shifts(ns) : {0.000 10.000 20.000} +Edge Shifts(ns) : {0.000 -3.500 -7.000} Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2} +>>>>>>> Stashed changes Generated Clock : sys_clk Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Master Clock : clk diff --git a/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt b/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt index 441963e..fe3a748 100644 --- a/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt +++ b/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt @@ -1,13 +1,17 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:35:00 2026 +<<<<<<< Updated upstream +| Date : Fri Jul 10 04:15:40 2026 +======= +| Date : Sat Jul 11 09:21:26 2026 +>>>>>>> Stashed changes | Host : fedora running 64-bit unknown -| Command : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_nodsp/design_analysis_complexity.rpt +| Command : report_design_analysis -complexity -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt | Design : soc_top | Device : xc7a200t | Design State : Routed -------------------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- Report Design Analysis @@ -18,18 +22,31 @@ Table of Contents 1. Complexity Characteristics (Cells) ------------------------------------- -+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+ -| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM | -+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+ -| (top) | soc_top | 0.34 | 3.77 | 118528 | 801(1.2%) | 6978(10.2%) | 9384(13.7%) | 7294(10.7%) | 8477(12.4%) | 35413(51.8%) | 1175 | 16 | 39 | 6020 | 0 | -| u_axi_axil_adapter | axi_axil_adapter | 0.50 | 5.92 | 1309 | 0(0.0%) | 8(0.7%) | 43(3.8%) | 100(8.9%) | 200(17.7%) | 776(68.9%) | 0 | 0 | 0 | 0 | 0 | -| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 | -| u_cdma_matmul_bridge | cdma_matmul_bridge | 0.46 | 2.22 | 1002 | 1(0.3%) | 65(17.1%) | 39(10.3%) | 174(45.8%) | 13(3.4%) | 88(23.2%) | 0 | 0 | 0 | 0 | 0 | -| u_cpu | core_top | 0.56 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 | -| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.56 | 3.75 | 74954 | 362(0.9%) | 3923(9.7%) | 6649(16.4%) | 4109(10.2%) | 4490(11.1%) | 20899(51.7%) | 1169 | 16 | 18 | 5286 | 0 | -| u_matmul_axi_slave | matmul_axi_slave | 0.63 | 3.76 | 15159 | 18(0.2%) | 1646(15.2%) | 357(3.3%) | 830(7.6%) | 974(9.0%) | 7026(64.7%) | 6 | 0 | 0 | 413 | 0 | -| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.36 | 3.45 | 3680 | 136(6.5%) | 181(8.6%) | 405(19.3%) | 255(12.2%) | 342(16.3%) | 776(37.0%) | 0 | 0 | 1 | 4 | 0 | -+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+ +<<<<<<< Updated upstream ++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+ +| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM | ++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+ +| (top) | soc_top | 0.31 | 3.78 | 131904 | 802(1.0%) | 9228(11.4%) | 10135(12.5%) | 10316(12.7%) | 12781(15.7%) | 37981(46.7%) | 1175 | 0 | 41 | 6069 | 0 | +| u_axi_axil_adapter | axi_axil_adapter | 0.37 | 4.65 | 1624 | 0(0.0%) | 25(1.8%) | 36(2.6%) | 860(61.8%) | 202(14.5%) | 269(19.3%) | 0 | 0 | 0 | 62 | 0 | +| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 | +| u_cpu | core_top | 0.59 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 | +| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.41 | 3.78 | 87846 | 374(0.7%) | 6103(11.5%) | 7425(14.0%) | 6353(12.0%) | 8174(15.5%) | 24445(46.2%) | 1169 | 0 | 20 | 5269 | 0 | +| u_matmul_axi_slave | matmul_axi_slave | 0.60 | 3.76 | 15711 | 18(0.2%) | 1632(14.3%) | 345(3.0%) | 805(7.1%) | 1733(15.2%) | 6875(60.3%) | 6 | 0 | 0 | 417 | 0 | +| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.46 | 3.31 | 3435 | 136(7.4%) | 239(12.9%) | 432(23.4%) | 301(16.3%) | 234(12.6%) | 508(27.5%) | 0 | 0 | 1 | 4 | 0 | ++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+ +======= ++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+-------------+-------------+--------------+------------+-----+------+------+------+ +| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM | ++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+-------------+-------------+--------------+------------+-----+------+------+------+ +| (top) | soc_top | 0.37 | 3.61 | 102050 | 871(1.4%) | 8543(13.4%) | 10370(16.3%) | 8684(13.7%) | 8274(13.0%) | 26800(42.2%) | 1216 | 0 | 49 | 2433 | 0 | +| u_axi_axil_adapter | axi_axil_adapter | 0.43 | 4.86 | 1534 | 0(0.0%) | 28(2.2%) | 37(2.8%) | 763(58.6%) | 216(16.6%) | 258(19.8%) | 0 | 0 | 0 | 62 | 0 | +| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 | +| u_cpu | core_top | 0.62 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 | +| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.35 | 3.49 | 58249 | 424(1.2%) | 5455(15.4%) | 7551(21.3%) | 4691(13.2%) | 4348(12.2%) | 13041(36.7%) | 1210 | 0 | 28 | 1632 | 0 | +| u_matmul_axi_slave | matmul_axi_slave | 0.58 | 3.76 | 15281 | 18(0.2%) | 1640(14.9%) | 369(3.4%) | 792(7.2%) | 1009(9.2%) | 7145(65.1%) | 6 | 0 | 0 | 418 | 0 | +| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.41 | 3.25 | 3423 | 136(7.4%) | 183(10.0%) | 430(23.4%) | 401(21.8%) | 243(13.2%) | 445(24.2%) | 0 | 0 | 1 | 4 | 0 | ++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+-------------+-------------+--------------+------------+-----+------+------+------+ +>>>>>>> Stashed changes * Complexity Ranges ** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal, 0.65 - 0.85 -> high, 0.85 - 1.0 -> very high *** -* -> Not computable as cell size is very small diff --git a/fpga/vivado_reports_nodsp/design_analysis_timing.rpt b/fpga/vivado_reports_nodsp/design_analysis_timing.rpt index 6e7bf34..6761b69 100644 --- a/fpga/vivado_reports_nodsp/design_analysis_timing.rpt +++ b/fpga/vivado_reports_nodsp/design_analysis_timing.rpt @@ -1,13 +1,17 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:29 2026 +<<<<<<< Updated upstream +| Date : Fri Jul 10 04:15:09 2026 +======= +| Date : Sat Jul 11 09:21:05 2026 +>>>>>>> Stashed changes | Host : fedora running 64-bit unknown -| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_nodsp/design_analysis_timing.rpt +| Command : report_design_analysis -timing -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_timing.rpt | Design : soc_top | Device : xc7a200t | Design State : Routed ------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------------------------- Report Design Analysis @@ -18,35 +22,67 @@ Table of Contents 1. Setup Path Characteristics 1-1 --------------------------------- -+---------------------------+------------------------------------------------------+ -| Characteristics | Path #1 | -+---------------------------+------------------------------------------------------+ -| Requirement | 20.000 | -| Path Delay | 15.605 | -| Logic Delay | 5.343(35%) | -| Net Delay | 10.263(65%) | -| Clock Skew | -3.858 | -| Slack | 0.167 | -| Clock Relationship | Safely Timed | -| Logic Levels | 9 | -| Routes | 9 | -| Logical Path | FDRE LUT4 LUT6 LUT5 LUT6 RAMD32 LUT6 LUT5 LUT3 OBUFT | -| Start Point Clock | sys_clk | -| End Point Clock | sys_clk | -| DSP Block | None | -| BRAM | None | -| IO Crossings | 3 | -| Config Crossings | 0 | -| SLR Crossings | 0 | -| PBlocks | 0 | -| High Fanout | 130 | -| Dont Touch | 0 | -| Mark Debug | 0 | -| Start Point Pin Primitive | FDRE/C | -| End Point Pin Primitive | ext_ram_data[18] | -| Start Point Pin | FSM_sequential_ext_wr_state_reg[1]/C | -| End Point Pin | ext_ram_data[18] | -+---------------------------+------------------------------------------------------+ +<<<<<<< Updated upstream ++---------------------------+----------------------------------------------------------------------------------------+ +| Characteristics | Path #1 | ++---------------------------+----------------------------------------------------------------------------------------+ +| Requirement | 20.000 | +| Path Delay | 15.529 | +| Logic Delay | 6.868(45%) | +| Net Delay | 8.661(55%) | +| Clock Skew | -3.955 | +| Slack | 0.146 | +| Clock Relationship | Safely Timed | +| Logic Levels | 14 | +| Routes | 12 | +| Logical Path | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 LUT4 CARRY4 CARRY4 LUT6 LUT6 LUT6 OBUF | +| Start Point Clock | sys_clk | +| End Point Clock | sys_clk | +| DSP Block | None | +| BRAM | None | +| IO Crossings | 3 | +| Config Crossings | 0 | +| SLR Crossings | 0 | +| PBlocks | 0 | +| High Fanout | 80 | +| Dont Touch | 0 | +| Mark Debug | 0 | +| Start Point Pin Primitive | FDCE/C | +| End Point Pin Primitive | base_ram_be_n[3] | +| Start Point Pin | ax_req_q_len_reg[3]/C | +| End Point Pin | base_ram_be_n[3] | ++---------------------------+----------------------------------------------------------------------------------------+ +======= ++---------------------------+-----------------------+ +| Characteristics | Path #1 | ++---------------------------+-----------------------+ +| Requirement | 13.000 | +| Path Delay | 13.035 | +| Logic Delay | 0.752(6%) | +| Net Delay | 12.283(94%) | +| Clock Skew | 0.135 | +| Slack | 0.070 | +| Clock Relationship | Safely Timed | +| Logic Levels | 1 | +| Routes | 1 | +| Logical Path | FDRE MUXF7 FDCE | +| Start Point Clock | mlkem_clk | +| End Point Clock | mlkem_clk | +| DSP Block | None | +| BRAM | None | +| IO Crossings | 0 | +| Config Crossings | 0 | +| SLR Crossings | 0 | +| PBlocks | 0 | +| High Fanout | 1088 | +| Dont Touch | 0 | +| Mark Debug | 0 | +| Start Point Pin Primitive | FDRE/C | +| End Point Pin Primitive | FDCE/D | +| Start Point Pin | dj_wb_inz_reg/C | +| End Point Pin | dj_block_r_reg[732]/D | ++---------------------------+-----------------------+ +>>>>>>> Stashed changes * Bounding box calculated as % of dimensions for the target device (436, 500) diff --git a/fpga/vivado_reports_nodsp/drc.rpt b/fpga/vivado_reports_nodsp/drc.rpt index 213e823..e5f8b3e 100644 --- a/fpga/vivado_reports_nodsp/drc.rpt +++ b/fpga/vivado_reports_nodsp/drc.rpt @@ -1,14 +1,18 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:33:58 2026 +<<<<<<< Updated upstream +| Date : Fri Jul 10 04:14:40 2026 +======= +| Date : Sat Jul 11 09:20:47 2026 +>>>>>>> Stashed changes | Host : fedora running 64-bit unknown -| Command : report_drc -file /home/fallensigh/vivado_reports_nodsp/drc.rpt +| Command : report_drc -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/drc.rpt | Design : soc_top | Device : xc7a200tfbg676-1 | Speed File : -1 | Design State : Fully Routed ------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------- Report DRC @@ -24,14 +28,11 @@ Table of Contents Design limits: Ruledeck: default Max violations: - Violations found: 90 + Violations found: 42 +-----------+----------+----------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+----------+----------------------------+------------+ | CHECK-3 | Warning | Report rule limit reached | 2 | -| DPIP-1 | Warning | Input pipelining | 16 | -| DPOP-1 | Warning | PREG Output pipelining | 16 | -| DPOP-2 | Warning | MREG Output pipelining | 16 | | REQP-1839 | Warning | RAMB36 async control check | 20 | | REQP-1840 | Warning | RAMB18 async control check | 20 | +-----------+----------+----------------------------+------------+ @@ -48,246 +49,6 @@ Report rule limit reached REQP-1840 rule limit reached: 20 violations have been found. Related violations: -DPIP-1#1 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#2 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#3 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#4 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#5 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#6 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#7 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#8 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#9 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#10 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#11 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#12 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#13 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#14 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#15 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#16 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPOP-1#1 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#2 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#3 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#4 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#5 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#6 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#7 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#8 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#9 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#10 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#11 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#12 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#13 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#14 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#15 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#16 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-2#1 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#2 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#3 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#4 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#5 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#6 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#7 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#8 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#9 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#10 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#11 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#12 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#13 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#14 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#15 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#16 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - REQP-1839#1 Warning RAMB36 async control check The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. diff --git a/fpga/vivado_reports_nodsp/high_fanout.rpt b/fpga/vivado_reports_nodsp/high_fanout.rpt index 5af6bfc..de4b247 100644 --- a/fpga/vivado_reports_nodsp/high_fanout.rpt +++ b/fpga/vivado_reports_nodsp/high_fanout.rpt @@ -1,12 +1,16 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 +<<<<<<< Updated upstream +| Date : Fri Jul 10 04:14:55 2026 +======= +| Date : Sat Jul 11 09:20:57 2026 +>>>>>>> Stashed changes | Host : fedora running 64-bit unknown -| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_nodsp/high_fanout.rpt +| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/high_fanout.rpt | Design : soc_top | Device : xc7a200t --------------------------------------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- High Fan-out Nets Information @@ -16,132 +20,133 @@ High Fan-out Nets Information +---------------------------------------------------------------------------------------+--------+-------------+ | Net Name | Fanout | Driver Type | +---------------------------------------------------------------------------------------+--------+-------------+ -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1] | 24598 | LUT5 | -| pll_clk.u_clk_pll/inst/sys_clk | 10004 | BUFG | -| pll_clk.u_rst_sys/p_0_in | 4130 | LUT1 | +<<<<<<< Updated upstream +| pll_clk.u_clk_pll/inst/sys_clk | 35652 | BUFG | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1] | 24670 | LUT5 | +| pll_clk.u_rst_sys/p_0_in | 5108 | LUT1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[0] | 3758 | FDCE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0 | 2151 | FDRE | +======= +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/delay_reg[1] | 15647 | LUT5 | +| pll_clk.u_clk_pll/inst/sys_clk | 9971 | BUFG | +| pll_clk.u_rst_sys/p_0_in | 4121 | LUT1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mb_en | 2121 | LUT6 | +>>>>>>> Stashed changes | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT2 | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[0]_0 | 2018 | FDSE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_n_0 | 1619 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1613 | LUT3 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0] | 1608 | LUT2 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 | 1608 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state[2]_i_3_n_0 | 1604 | LUT5 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sel_cbd | 1603 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1601 | LUT3 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 | 1601 | LUT6 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_6_n_0 | 1601 | LUT6 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_7_n_0 | 1601 | LUT6 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 | +<<<<<<< Updated upstream | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1] | 1543 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2] | 1542 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active | 1130 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1109 | LUT2 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE | -| pll_clk.u_rst_mlkem/delay_reg[1]_0 | 1069 | LUT1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0 | 936 | LUT5 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0 | 938 | LUT5 | +| u_matmul_axi_slave/w_addr[2] | 873 | FDRE | | u_cpu/reset | 799 | FDRE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0] | 769 | CARRY4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1] | 769 | CARRY4 | -| u_matmul_axi_slave/w_addr[2] | 724 | FDRE | | u_cpu/u_mul/E[0] | 716 | LUT1 | -| u_matmul_axi_slave/w_addr[3] | 628 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1 | 528 | LUT6 | -| u_matmul_axi_slave/current_r_offset[2] | 522 | LUT5 | -| u_matmul_axi_slave/current_r_offset[3] | 520 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0] | 516 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1] | 516 | FDCE | +| u_matmul_axi_slave/w_addr[4] | 655 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1 | 525 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1] | 518 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0] | 515 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_rep_2[0] | 512 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[2] | 390 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[3]_0[0] | 512 | LUT5 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2] | 385 | CARRY4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_vld_reg_n_0 | 370 | FDCE | +======= +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in | 1344 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1109 | LUT2 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE | +| pll_clk.u_rst_mlkem/delay_reg[1]_1 | 1066 | LUT1 | +| u_cpu/reset | 799 | FDRE | +| u_cpu/u_mul/E[0] | 716 | LUT1 | +| u_matmul_axi_slave/w_addr[2] | 644 | FDRE | +| u_matmul_axi_slave/current_r_offset[2] | 524 | LUT5 | +| u_matmul_axi_slave/current_r_offset[3] | 522 | LUT5 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[2]_rep__3[0] | 513 | LUT5 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 | +>>>>>>> Stashed changes | u_cpu/wb_stage/w_index[0] | 358 | LUT6 | | u_cpu/wb_stage/w_index[1] | 358 | LUT6 | | u_cpu/wb_stage/w_index[2] | 358 | LUT6 | | u_cpu/wb_stage/w_index[3] | 358 | LUT6 | | u_cpu/wb_stage/w_index[4] | 358 | LUT6 | +| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 357 | LUT3 | +| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0 | 356 | LUT3 | | u_matmul_axi_slave/acc_idx_d4[0] | 354 | FDRE | | u_matmul_axi_slave/acc_idx_d4[1] | 354 | FDRE | | u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE | | u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE | | u_cpu/wb_stage/we_0 | 324 | LUT4 | -| u_matmul_axi_slave/w_addr[4] | 317 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 290 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3] | 284 | FDCE | -| u_matmul_axi_slave/cur_bank_reg_n_0 | 277 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 263 | RAMB18E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 263 | RAMB18E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 262 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 261 | RAMB18E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 261 | RAMB36E1 | +<<<<<<< Updated upstream +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 293 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r2[4] | 288 | CARRY4 | +| u_matmul_axi_slave/cur_bank_reg_n_0 | 274 | FDRE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 261 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[4] | 260 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 259 | RAMB36E1 | -| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 259 | FDRE | -| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0 | 257 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_active_reg_rep__7[0] | 256 | LUT5 | +| u_matmul_axi_slave/sel0[1] | 259 | FDRE | +| u_matmul_axi_slave/b1_b_reg[0][31]_i_8_n_7 | 258 | CARRY4 | +| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 258 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_phase_reg[1]_0[0] | 256 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 | -| u_matmul_axi_slave/m_in_b[0][31]_i_1_n_0 | 256 | LUT6 | +| u_matmul_axi_slave/m_in_a[3][31]_i_1_n_0 | 256 | LUT6 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 | -| u_matmul_axi_slave/w_addr[5] | 246 | FDRE | +| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT2 | +| u_matmul_axi_slave/b0_a[6][25]_i_2_n_0 | 242 | LUT2 | +| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 239 | LUT3 | +| u_matmul_axi_slave/m_in_a[3][30]_i_6_n_0 | 238 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 237 | FDCE | +| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 | +| u_cpu/mem_stage/E[0] | 234 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3] | 231 | FDCE | +======= +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 289 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_4 | 288 | CARRY4 | +| u_matmul_axi_slave/w_addr[4] | 286 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 260 | LUT5 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/E[0] | 256 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 | +| u_matmul_axi_slave/m_in_a[3][31]_i_1_n_0 | 256 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_7 | 248 | FDCE | | u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT3 | | u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 | | u_cpu/mem_stage/E[0] | 234 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 234 | FDCE | -| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 229 | LUT3 | -| u_matmul_axi_slave/m_in_b[0][31]_i_7_n_0 | 228 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 227 | FDCE | +>>>>>>> Stashed changes | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 224 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 224 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 224 | LUT4 | @@ -150,72 +155,252 @@ High Fan-out Nets Information | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 224 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 224 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 224 | LUT4 | +<<<<<<< Updated upstream +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[5] | 219 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 216 | RAMB18E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 216 | RAMB18E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 215 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[2] | 215 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 214 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 214 | RAMB18E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 214 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 212 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 212 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 212 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 212 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 212 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 212 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 212 | RAMB36E1 | | u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 | | u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 | | u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE | -| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0] | 203 | FDRE | -| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1] | 203 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6] | 200 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 200 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[3] | 197 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7] | 207 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 206 | FDCE | +======= +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_2 | 222 | FDCE | +| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 | +| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 | +| u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE | +>>>>>>> Stashed changes | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2] | 196 | FDCE | -| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 196 | LUT6 | | u_cpu/wb_stage/Q[33] | 194 | FDRE | | u_cpu/wb_stage/Q[34] | 194 | FDRE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5] | 194 | FDCE | +<<<<<<< Updated upstream | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3] | 193 | CARRY4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r_reg[4]_rep_n_0 | 191 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[2] | 187 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3] | 187 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 187 | FDCE | -| u_matmul_axi_slave/current_r_offset[4] | 187 | LUT5 | -| u_matmul_axi_slave/s_axi_wready_reg_1 | 181 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[3] | 187 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[2] | 186 | FDCE | | u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3] | 180 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 177 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0] | 176 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 180 | FDCE | +| u_matmul_axi_slave/b0_b_reg[1][30]_i_4_n_7 | 178 | CARRY4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 176 | FDCE | +======= +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[2]_rep_n_0 | 191 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_6 | 186 | FDCE | +| u_matmul_axi_slave/w_addr[5] | 184 | FDRE | +| u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_1 | 179 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 178 | FDCE | +| u_matmul_axi_slave/b1_b[0][31]_i_7_n_0 | 177 | LUT3 | +>>>>>>> Stashed changes | u_matmul_axi_slave/p_0_in__0 | 176 | LUT4 | | u_matmul_axi_slave/p_0_in__0__0 | 176 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt114_out | 175 | LUT2 | | u_cpu/wb_stage/Q[37] | 173 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7] | 173 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_4_n_7 | 171 | CARRY4 | +<<<<<<< Updated upstream +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]_rep__0_n_0 | 172 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[131][11]_i_4_n_0 | 171 | LUT3 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[127]_i_2_n_0 | 169 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[383]_i_2_n_0 | 169 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[639]_i_2_n_0 | 169 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[895]_i_2_n_0 | 169 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 169 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5] | 166 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r2[3] | 169 | CARRY4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[74][11]_i_4_n_0 | 168 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[6]_0[0] | 168 | CARRY4 | +| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_0 | 167 | LUT2 | +| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_1 | 167 | LUT2 | +| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 167 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[129][11]_i_3_n_0 | 166 | LUT3 | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__0_n_0 | 165 | FDRE | +======= +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_2 | 172 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r_reg[255]_i_5_n_5 | 171 | CARRY4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/z_word_reg[1][31]_i_6_n_7 | 170 | CARRY4 | +| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 170 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_4 | 168 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/z_word_reg[1][31]_i_6_n_6 | 168 | CARRY4 | +>>>>>>> Stashed changes | u_cpu/wb_stage/Q[32] | 164 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 164 | FDCE | | u_cpu/wb_stage/Q[35] | 163 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg[0]_rep__0_n_0 | 163 | FDCE | | u_cpu/wb_stage/Q[36] | 162 | FDRE | -| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0 | 161 | LUT3 | +<<<<<<< Updated upstream | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1023]_i_2_n_0 | 160 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[255]_i_2_n_0 | 160 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[511]_i_2_n_0 | 160 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[767]_i_2_n_0 | 160 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__12_n_0 | 158 | FDCE | +| u_matmul_axi_slave/w_addr_reg[3]_rep__2_0 | 158 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[181][5]_i_3_n_0 | 157 | LUT2 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[6] | 156 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 155 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6] | 153 | FDCE | -| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 153 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[7] | 155 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3] | 154 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[4] | 154 | FDCE | +| u_matmul_axi_slave/w_addr[3] | 153 | FDRE | +======= +| u_matmul_axi_slave/pipe_cnt_reg_n_0_[3] | 162 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_34_n_0 | 161 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[3] | 158 | FDRE | +| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0 | 157 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 156 | FDCE | +| u_matmul_axi_slave/w_addr_reg[3]_rep_n_0 | 153 | FDRE | +>>>>>>> Stashed changes | u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0 | 151 | FDRE | | u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1 | 150 | CARRY4 | | u_cpu/dcache/awaddr[31]_i_3_n_0 | 148 | LUT2 | | u_cpu/dcache/awaddr[31]_i_4_n_0 | 148 | LUT2 | -| u_matmul_axi_slave/s_axi_wready_reg_0 | 148 | LUT5 | +<<<<<<< Updated upstream +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 148 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[202][11]_i_3_n_0 | 148 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 147 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__1_n_0 | 146 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep_n_0 | 146 | FDCE | +| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 146 | LUT3 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0] | 145 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_63_n_0 | 144 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 143 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 143 | FDCE | -| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0 | 143 | LUT3 | -| u_matmul_axi_slave/pipe_cnt[3]_i_4_n_0 | 143 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep_n_0 | 142 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 141 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__10_n_0 | 145 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[2] | 144 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/hek_r[247]_i_3_n_0 | 144 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/hek_r[255]_i_3_n_0 | 144 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__17_n_0 | 143 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[106][11]_i_3_n_0 | 143 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 142 | FDCE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[0] | 142 | FDSE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[5] | 141 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5] | 141 | FDCE | | u_cpu/dcache/write_buffer_state | 140 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_reg_rep__6_n_0 | 140 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 140 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5] | 140 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[7] | 140 | FDCE | +======= +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN | 148 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_10 | 146 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_9 | 143 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 142 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_43_n_0 | 141 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_57_n_0 | 141 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[4] | 141 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[5] | 141 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[6] | 141 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[7] | 141 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 141 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[7] | 141 | FDCE | +| u_cpu/dcache/write_buffer_state | 140 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 140 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__3_n_0 | 140 | FDCE | | u_cpu/u_csr/tlbw_r_tlbidx[0] | 139 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_37_n_0 | 139 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep__3_n_0 | 139 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5] | 139 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_3 | 138 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[3] | 138 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[6]_rep_n_0 | 138 | FDCE | +| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[7]_1 | 137 | LUT2 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[4]_rep_n_0 | 137 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[5]_rep_n_0 | 137 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[2] | 137 | FDRE | +| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0 | 137 | FDRE | +| u_cpu/u_csr/tlbw_r_tlbidx[1] | 136 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1080]_i_5_n_0 | 136 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1081]_i_5_n_0 | 136 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1082]_i_5_n_0 | 136 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1083]_i_5_n_0 | 136 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1084]_i_6_n_0 | 136 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_3_n_0 | 136 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1087]_i_9_n_0 | 136 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1087]_i_3_n_0 | 136 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx_reg[7]_rep_n_0 | 136 | FDCE | +| u_matmul_axi_slave/b1_b[0][31]_i_8_n_0 | 136 | LUT2 | +| u_snix_axil_cdma_mux_8ch/ep_rd_elem[0] | 136 | LUT6 | +| u_snix_axil_cdma_mux_8ch/ep_rd_elem[1] | 136 | LUT5 | +| u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] | 135 | LUT6 | +| u_snix_axil_cdma_mux_8ch/ep_rd_elem[3] | 135 | LUT5 | +| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_0 | 134 | LUT2 | +| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[7]_0 | 134 | LUT2 | +| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[7]_2 | 134 | LUT2 | +| u_matmul_axi_slave/w_addr[3] | 134 | FDRE | +| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[29]_i_7_n_0 | 133 | LUT2 | +| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[29]_i_9_n_0 | 133 | LUT2 | +| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[31]_i_12_n_0 | 133 | LUT2 | +| u_axi_axil_adapter/axi_axil_adapter_rd_inst/s_axil_rdata[31]_i_13_n_0 | 133 | LUT2 | +| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[3]_0 | 133 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/dbg_dk_idx[4] | 133 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/dbg_dk_idx[3] | 132 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_repN_4 | 132 | FDCE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[2] | 132 | FDRE | +| u_matmul_axi_slave/c1_elem[0] | 132 | LUT6 | +| u_matmul_axi_slave/c1_elem[1] | 132 | LUT5 | +| u_matmul_axi_slave/c1_elem[2] | 132 | LUT4 | +| u_matmul_axi_slave/c1_elem[3] | 132 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep_n_0 | 131 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_reject | 130 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_8 | 130 | FDCE | +| u_matmul_axi_slave/pipe_cnt_reg_n_0_[1] | 130 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[1] | 129 | FDRE | +| u_confreg/s_rdata[31]_i_8_n_0 | 128 | LUT3 | +| u_confreg/s_rdata[31]_i_9_n_0 | 128 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_reject_reg_rep_n_0 | 128 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0] | 128 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[1] | 128 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[2] | 128 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[4] | 128 | FDCE | +| u_matmul_axi_slave/current_r_offset[5] | 128 | LUT3 | +| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 128 | FDRE | +| u_matmul_axi_slave/pipe_cnt_reg_n_0_[0] | 128 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__0_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__10_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__1_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__2_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__3_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__4_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__5_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__6_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__7_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__8_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__9_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__10_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__11_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__12_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__13_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__2_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__3_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__4_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__5_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__6_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__7_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__8_n_0 | 127 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__9_n_0 | 127 | FDRE | +| u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] | 127 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__0_n_0 | 126 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__1_n_0 | 126 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[3]_rep__2_n_0 | 126 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0_repN_3 | 126 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/state[1] | 126 | FDCE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_rep__11_0 | 126 | FDRE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__1_n_0 | 126 | FDRE | +| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0] | 126 | FDRE | +>>>>>>> Stashed changes +---------------------------------------------------------------------------------------+--------+-------------+ diff --git a/fpga/vivado_reports_nodsp/methodology.rpt b/fpga/vivado_reports_nodsp/methodology.rpt index 82b3488..1de3683 100644 --- a/fpga/vivado_reports_nodsp/methodology.rpt +++ b/fpga/vivado_reports_nodsp/methodology.rpt @@ -1,14 +1,18 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:05 2026 +<<<<<<< Updated upstream +| Date : Fri Jul 10 04:14:46 2026 +======= +| Date : Sat Jul 11 09:20:51 2026 +>>>>>>> Stashed changes | Host : fedora running 64-bit unknown -| Command : report_methodology -file /home/fallensigh/vivado_reports_nodsp/methodology.rpt +| Command : report_methodology -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/methodology.rpt | Design : soc_top | Device : xc7a200tfbg676-1 | Speed File : -1 | Design State : Fully Routed ------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------- Report Methodology @@ -23,17 +27,27 @@ Table of Contents Floorplan: impl_1 Design limits: Max violations: - Violations found: 99 +<<<<<<< Updated upstream + Violations found: 107 +======= + Violations found: 115 +>>>>>>> Stashed changes +-----------+----------+-------------------------------------------------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+----------+-------------------------------------------------------------------+------------+ | LUTAR-1 | Warning | LUT drives async reset alert | 1 | | SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 | -| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 1 | +<<<<<<< Updated upstream +| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 9 | | SYNTH-16 | Warning | Address collision | 8 | +======= +| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 6 | +| SYNTH-16 | Warning | Address collision | 16 | +| TIMING-9 | Warning | Unknown CDC Logic | 1 | +>>>>>>> Stashed changes | TIMING-10 | Warning | Missing property on synchronizer | 1 | | TIMING-18 | Warning | Missing input or output delay | 76 | -| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 2 | +| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 4 | | XDCC-1 | Warning | Scoped Clock constraint overwritten with the same name | 1 | | XDCC-7 | Warning | Scoped Clock constraint overwritten on the same source | 1 | +-----------+----------+-------------------------------------------------------------------+------------+ @@ -42,7 +56,11 @@ Table of Contents ----------------- LUTAR-1#1 Warning LUT drives async reset alert -LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24584 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +<<<<<<< Updated upstream +LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24656 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +======= +LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 15633 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +>>>>>>> Stashed changes Related violations: SYNTH-5#1 Warning @@ -87,7 +105,71 @@ Related violations: SYNTH-6#1 Warning Timing of a block RAM might be sub-optimal -The timing for the instance u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +<<<<<<< Updated upstream +The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +======= +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +>>>>>>> Stashed changes +Related violations: + +SYNTH-6#2 Warning +Timing of a block RAM might be sub-optimal +<<<<<<< Updated upstream +The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +======= +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +>>>>>>> Stashed changes +Related violations: + +SYNTH-6#3 Warning +Timing of a block RAM might be sub-optimal +<<<<<<< Updated upstream +The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +======= +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +>>>>>>> Stashed changes +Related violations: + +SYNTH-6#4 Warning +Timing of a block RAM might be sub-optimal +<<<<<<< Updated upstream +The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +======= +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +>>>>>>> Stashed changes +Related violations: + +SYNTH-6#5 Warning +Timing of a block RAM might be sub-optimal +<<<<<<< Updated upstream +The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +======= +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +>>>>>>> Stashed changes +Related violations: + +SYNTH-6#6 Warning +Timing of a block RAM might be sub-optimal +<<<<<<< Updated upstream +The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#7 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#8 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#9 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +======= +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +>>>>>>> Stashed changes Related violations: SYNTH-16#1 Warning @@ -130,6 +212,51 @@ Address collision Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. Related violations: +SYNTH-16#9 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#10 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#11 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#12 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#13 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#14 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#15 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +SYNTH-16#16 Warning +Address collision +Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +TIMING-9#1 Warning +Unknown CDC Logic +One or more asynchronous Clock Domain Crossing has been detected between 2 clock domains through a set_false_path or a set_clock_groups or set_max_delay -datapath_only constraint but no double-registers logic synchronizer has been found on the side of the capture clock. It is recommended to run report_cdc for a complete and detailed CDC coverage. Please consider using XPM_CDC to avoid Critical severities +Related violations: + TIMING-10#1 Warning Missing property on synchronizer One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage @@ -517,12 +644,22 @@ Related violations: TIMING-47#1 Warning False path or asynchronous clock group between synchronous clocks -A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. +A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. Related violations: TIMING-47#2 Warning False path or asynchronous clock group between synchronous clocks -A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. +A Clock Group timing constraint is set between synchronous clocks mlkem_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. +Related violations: + +TIMING-47#3 Warning +False path or asynchronous clock group between synchronous clocks +A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. +Related violations: + +TIMING-47#4 Warning +False path or asynchronous clock group between synchronous clocks +A Clock Group timing constraint is set between synchronous clocks sys_clk and mlkem_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. Related violations: XDCC-1#1 Warning diff --git a/fpga/vivado_reports_nodsp/mlkem_clk_clk_pll_timing.rpt b/fpga/vivado_reports_nodsp/mlkem_clk_clk_pll_timing.rpt new file mode 100644 index 0000000..5c39a79 --- /dev/null +++ b/fpga/vivado_reports_nodsp/mlkem_clk_clk_pll_timing.rpt @@ -0,0 +1,8686 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 +| Date : Sat Jul 11 07:56:45 2026 +| Host : fedora running 64-bit unknown +| Command : report_timing -from [get_clocks mlkem_clk_clk_pll] -to [get_clocks mlkem_clk_clk_pll] -delay_type max -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/mlkem_clk_clk_pll_timing.rpt +| Design : soc_top +| Device : 7a200t-fbg676 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Report + +Slack (VIOLATED) : -1.393ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.076ns (logic 4.497ns (40.603%) route 6.579ns (59.397%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.999 8.163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/I5 + SLICE_X39Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/O + net (fo=1, routed) 0.387 8.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.674 + ------------------------------------------------------------------- + slack -1.393 + +Slack (VIOLATED) : -1.393ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.076ns (logic 4.497ns (40.603%) route 6.579ns (59.397%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.999 8.163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/I5 + SLICE_X39Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/O + net (fo=1, routed) 0.387 8.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.674 + ------------------------------------------------------------------- + slack -1.393 + +Slack (VIOLATED) : -1.393ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.076ns (logic 4.497ns (40.603%) route 6.579ns (59.397%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.999 8.163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/I5 + SLICE_X39Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/O + net (fo=1, routed) 0.387 8.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.674 + ------------------------------------------------------------------- + slack -1.393 + +Slack (VIOLATED) : -1.393ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.076ns (logic 4.497ns (40.603%) route 6.579ns (59.397%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.999 8.163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/I5 + SLICE_X39Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/O + net (fo=1, routed) 0.387 8.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.674 + ------------------------------------------------------------------- + slack -1.393 + +Slack (VIOLATED) : -1.393ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.076ns (logic 4.497ns (40.603%) route 6.579ns (59.397%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.999 8.163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/I5 + SLICE_X39Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/O + net (fo=1, routed) 0.387 8.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.674 + ------------------------------------------------------------------- + slack -1.393 + +Slack (VIOLATED) : -1.393ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.076ns (logic 4.497ns (40.603%) route 6.579ns (59.397%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.999 8.163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/I5 + SLICE_X39Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/O + net (fo=1, routed) 0.387 8.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.674 + ------------------------------------------------------------------- + slack -1.393 + +Slack (VIOLATED) : -1.393ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.076ns (logic 4.497ns (40.603%) route 6.579ns (59.397%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.999 8.163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/I5 + SLICE_X39Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/O + net (fo=1, routed) 0.387 8.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.674 + ------------------------------------------------------------------- + slack -1.393 + +Slack (VIOLATED) : -1.393ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.076ns (logic 4.497ns (40.603%) route 6.579ns (59.397%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.999 8.163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/I5 + SLICE_X39Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/O + net (fo=1, routed) 0.387 8.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.674 + ------------------------------------------------------------------- + slack -1.393 + +Slack (VIOLATED) : -1.393ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.076ns (logic 4.497ns (40.603%) route 6.579ns (59.397%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.999 8.163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/I5 + SLICE_X39Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/O + net (fo=1, routed) 0.387 8.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.674 + ------------------------------------------------------------------- + slack -1.393 + +Slack (VIOLATED) : -1.393ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.076ns (logic 4.497ns (40.603%) route 6.579ns (59.397%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.999 8.163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/I5 + SLICE_X39Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26__3/O + net (fo=1, routed) 0.387 8.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.674 + ------------------------------------------------------------------- + slack -1.393 + +Slack (VIOLATED) : -1.362ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.047ns (logic 2.724ns (24.659%) route 8.323ns (75.341%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CO[3] + net (fo=2, routed) 0.760 7.330 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[11] + SLICE_X45Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/I1 + SLICE_X45Y47 LUT6 (Prop_lut6_I1_O) 0.124 7.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/O + net (fo=1, routed) 0.651 8.105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_129_n_0_alias + SLICE_X42Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/I5 + SLICE_X42Y53 LUT6 (Prop_lut6_I5_O) 0.124 8.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/O + net (fo=1, routed) 0.310 8.539 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[11] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[11]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.539 + ------------------------------------------------------------------- + slack -1.362 + +Slack (VIOLATED) : -1.362ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.047ns (logic 2.724ns (24.659%) route 8.323ns (75.341%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CO[3] + net (fo=2, routed) 0.760 7.330 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[11] + SLICE_X45Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/I1 + SLICE_X45Y47 LUT6 (Prop_lut6_I1_O) 0.124 7.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/O + net (fo=1, routed) 0.651 8.105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_129_n_0_alias + SLICE_X42Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/I5 + SLICE_X42Y53 LUT6 (Prop_lut6_I5_O) 0.124 8.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/O + net (fo=1, routed) 0.310 8.539 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[11] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[11]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.539 + ------------------------------------------------------------------- + slack -1.362 + +Slack (VIOLATED) : -1.362ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.047ns (logic 2.724ns (24.659%) route 8.323ns (75.341%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CO[3] + net (fo=2, routed) 0.760 7.330 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[11] + SLICE_X45Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/I1 + SLICE_X45Y47 LUT6 (Prop_lut6_I1_O) 0.124 7.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/O + net (fo=1, routed) 0.651 8.105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_129_n_0_alias + SLICE_X42Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/I5 + SLICE_X42Y53 LUT6 (Prop_lut6_I5_O) 0.124 8.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/O + net (fo=1, routed) 0.310 8.539 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[11] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[11]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.539 + ------------------------------------------------------------------- + slack -1.362 + +Slack (VIOLATED) : -1.362ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.047ns (logic 2.724ns (24.659%) route 8.323ns (75.341%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CO[3] + net (fo=2, routed) 0.760 7.330 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[11] + SLICE_X45Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/I1 + SLICE_X45Y47 LUT6 (Prop_lut6_I1_O) 0.124 7.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/O + net (fo=1, routed) 0.651 8.105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_129_n_0_alias + SLICE_X42Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/I5 + SLICE_X42Y53 LUT6 (Prop_lut6_I5_O) 0.124 8.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/O + net (fo=1, routed) 0.310 8.539 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[11] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[11]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.539 + ------------------------------------------------------------------- + slack -1.362 + +Slack (VIOLATED) : -1.362ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.047ns (logic 2.724ns (24.659%) route 8.323ns (75.341%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CO[3] + net (fo=2, routed) 0.760 7.330 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[11] + SLICE_X45Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/I1 + SLICE_X45Y47 LUT6 (Prop_lut6_I1_O) 0.124 7.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/O + net (fo=1, routed) 0.651 8.105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_129_n_0_alias + SLICE_X42Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/I5 + SLICE_X42Y53 LUT6 (Prop_lut6_I5_O) 0.124 8.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/O + net (fo=1, routed) 0.310 8.539 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[11] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[11]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.539 + ------------------------------------------------------------------- + slack -1.362 + +Slack (VIOLATED) : -1.362ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.047ns (logic 2.724ns (24.659%) route 8.323ns (75.341%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CO[3] + net (fo=2, routed) 0.760 7.330 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[11] + SLICE_X45Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/I1 + SLICE_X45Y47 LUT6 (Prop_lut6_I1_O) 0.124 7.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/O + net (fo=1, routed) 0.651 8.105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_129_n_0_alias + SLICE_X42Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/I5 + SLICE_X42Y53 LUT6 (Prop_lut6_I5_O) 0.124 8.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/O + net (fo=1, routed) 0.310 8.539 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[11] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[11]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.539 + ------------------------------------------------------------------- + slack -1.362 + +Slack (VIOLATED) : -1.362ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.047ns (logic 2.724ns (24.659%) route 8.323ns (75.341%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CO[3] + net (fo=2, routed) 0.760 7.330 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[11] + SLICE_X45Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/I1 + SLICE_X45Y47 LUT6 (Prop_lut6_I1_O) 0.124 7.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/O + net (fo=1, routed) 0.651 8.105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_129_n_0_alias + SLICE_X42Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/I5 + SLICE_X42Y53 LUT6 (Prop_lut6_I5_O) 0.124 8.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/O + net (fo=1, routed) 0.310 8.539 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[11] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[11]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.539 + ------------------------------------------------------------------- + slack -1.362 + +Slack (VIOLATED) : -1.362ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.047ns (logic 2.724ns (24.659%) route 8.323ns (75.341%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CO[3] + net (fo=2, routed) 0.760 7.330 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[11] + SLICE_X45Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/I1 + SLICE_X45Y47 LUT6 (Prop_lut6_I1_O) 0.124 7.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/O + net (fo=1, routed) 0.651 8.105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_129_n_0_alias + SLICE_X42Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/I5 + SLICE_X42Y53 LUT6 (Prop_lut6_I5_O) 0.124 8.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/O + net (fo=1, routed) 0.310 8.539 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[11] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[11]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.539 + ------------------------------------------------------------------- + slack -1.362 + +Slack (VIOLATED) : -1.362ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.047ns (logic 2.724ns (24.659%) route 8.323ns (75.341%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CO[3] + net (fo=2, routed) 0.760 7.330 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[11] + SLICE_X45Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/I1 + SLICE_X45Y47 LUT6 (Prop_lut6_I1_O) 0.124 7.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/O + net (fo=1, routed) 0.651 8.105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_129_n_0_alias + SLICE_X42Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/I5 + SLICE_X42Y53 LUT6 (Prop_lut6_I5_O) 0.124 8.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/O + net (fo=1, routed) 0.310 8.539 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[11] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[11]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.539 + ------------------------------------------------------------------- + slack -1.362 + +Slack (VIOLATED) : -1.362ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.047ns (logic 2.724ns (24.659%) route 8.323ns (75.341%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CO[3] + net (fo=2, routed) 0.760 7.330 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[11] + SLICE_X45Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/I1 + SLICE_X45Y47 LUT6 (Prop_lut6_I1_O) 0.124 7.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_129/O + net (fo=1, routed) 0.651 8.105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_129_n_0_alias + SLICE_X42Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/I5 + SLICE_X42Y53 LUT6 (Prop_lut6_I5_O) 0.124 8.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_24__4_comp/O + net (fo=1, routed) 0.310 8.539 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[11] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[11]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.539 + ------------------------------------------------------------------- + slack -1.362 + +Slack (VIOLATED) : -1.359ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.042ns (logic 4.497ns (40.728%) route 6.545ns (59.272%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.678 7.842 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X41Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/I5 + SLICE_X41Y46 LUT6 (Prop_lut6_I5_O) 0.124 7.966 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/O + net (fo=1, routed) 0.674 8.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[1] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[1]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.640 + ------------------------------------------------------------------- + slack -1.359 + +Slack (VIOLATED) : -1.359ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.042ns (logic 4.497ns (40.728%) route 6.545ns (59.272%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.678 7.842 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X41Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/I5 + SLICE_X41Y46 LUT6 (Prop_lut6_I5_O) 0.124 7.966 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/O + net (fo=1, routed) 0.674 8.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[1] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[1]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.640 + ------------------------------------------------------------------- + slack -1.359 + +Slack (VIOLATED) : -1.359ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.042ns (logic 4.497ns (40.728%) route 6.545ns (59.272%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.678 7.842 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X41Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/I5 + SLICE_X41Y46 LUT6 (Prop_lut6_I5_O) 0.124 7.966 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/O + net (fo=1, routed) 0.674 8.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[1] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[1]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.640 + ------------------------------------------------------------------- + slack -1.359 + +Slack (VIOLATED) : -1.359ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.042ns (logic 4.497ns (40.728%) route 6.545ns (59.272%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.678 7.842 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X41Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/I5 + SLICE_X41Y46 LUT6 (Prop_lut6_I5_O) 0.124 7.966 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/O + net (fo=1, routed) 0.674 8.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[1] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[1]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.640 + ------------------------------------------------------------------- + slack -1.359 + +Slack (VIOLATED) : -1.359ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.042ns (logic 4.497ns (40.728%) route 6.545ns (59.272%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.678 7.842 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X41Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/I5 + SLICE_X41Y46 LUT6 (Prop_lut6_I5_O) 0.124 7.966 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/O + net (fo=1, routed) 0.674 8.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[1] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[1]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.640 + ------------------------------------------------------------------- + slack -1.359 + +Slack (VIOLATED) : -1.359ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.042ns (logic 4.497ns (40.728%) route 6.545ns (59.272%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.678 7.842 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X41Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/I5 + SLICE_X41Y46 LUT6 (Prop_lut6_I5_O) 0.124 7.966 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/O + net (fo=1, routed) 0.674 8.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[1] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[1]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.640 + ------------------------------------------------------------------- + slack -1.359 + +Slack (VIOLATED) : -1.359ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.042ns (logic 4.497ns (40.728%) route 6.545ns (59.272%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.678 7.842 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X41Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/I5 + SLICE_X41Y46 LUT6 (Prop_lut6_I5_O) 0.124 7.966 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/O + net (fo=1, routed) 0.674 8.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[1] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[1]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.640 + ------------------------------------------------------------------- + slack -1.359 + +Slack (VIOLATED) : -1.359ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.042ns (logic 4.497ns (40.728%) route 6.545ns (59.272%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.678 7.842 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X41Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/I5 + SLICE_X41Y46 LUT6 (Prop_lut6_I5_O) 0.124 7.966 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/O + net (fo=1, routed) 0.674 8.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[1] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[1]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.640 + ------------------------------------------------------------------- + slack -1.359 + +Slack (VIOLATED) : -1.359ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.042ns (logic 4.497ns (40.728%) route 6.545ns (59.272%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.678 7.842 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X41Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/I5 + SLICE_X41Y46 LUT6 (Prop_lut6_I5_O) 0.124 7.966 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/O + net (fo=1, routed) 0.674 8.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[1] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[1]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.640 + ------------------------------------------------------------------- + slack -1.359 + +Slack (VIOLATED) : -1.359ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.042ns (logic 4.497ns (40.728%) route 6.545ns (59.272%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.678 7.842 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X41Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/I5 + SLICE_X41Y46 LUT6 (Prop_lut6_I5_O) 0.124 7.966 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_32__4/O + net (fo=1, routed) 0.674 8.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[1] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[1] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[1]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.640 + ------------------------------------------------------------------- + slack -1.359 + +Slack (VIOLATED) : -1.319ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.002ns (logic 4.497ns (40.875%) route 6.505ns (59.125%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.774 7.938 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X38Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/I5 + SLICE_X38Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/O + net (fo=1, routed) 0.539 8.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[4] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.600 + ------------------------------------------------------------------- + slack -1.319 + +Slack (VIOLATED) : -1.319ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.002ns (logic 4.497ns (40.875%) route 6.505ns (59.125%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.774 7.938 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X38Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/I5 + SLICE_X38Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/O + net (fo=1, routed) 0.539 8.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[4] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.600 + ------------------------------------------------------------------- + slack -1.319 + +Slack (VIOLATED) : -1.319ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.002ns (logic 4.497ns (40.875%) route 6.505ns (59.125%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.774 7.938 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X38Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/I5 + SLICE_X38Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/O + net (fo=1, routed) 0.539 8.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[4] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.600 + ------------------------------------------------------------------- + slack -1.319 + +Slack (VIOLATED) : -1.319ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.002ns (logic 4.497ns (40.875%) route 6.505ns (59.125%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.774 7.938 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X38Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/I5 + SLICE_X38Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/O + net (fo=1, routed) 0.539 8.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[4] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.600 + ------------------------------------------------------------------- + slack -1.319 + +Slack (VIOLATED) : -1.319ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.002ns (logic 4.497ns (40.875%) route 6.505ns (59.125%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.774 7.938 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X38Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/I5 + SLICE_X38Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/O + net (fo=1, routed) 0.539 8.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[4] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.600 + ------------------------------------------------------------------- + slack -1.319 + +Slack (VIOLATED) : -1.319ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.002ns (logic 4.497ns (40.875%) route 6.505ns (59.125%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.774 7.938 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X38Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/I5 + SLICE_X38Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/O + net (fo=1, routed) 0.539 8.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[4] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.600 + ------------------------------------------------------------------- + slack -1.319 + +Slack (VIOLATED) : -1.319ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.002ns (logic 4.497ns (40.875%) route 6.505ns (59.125%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.774 7.938 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X38Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/I5 + SLICE_X38Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/O + net (fo=1, routed) 0.539 8.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[4] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.600 + ------------------------------------------------------------------- + slack -1.319 + +Slack (VIOLATED) : -1.319ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.002ns (logic 4.497ns (40.875%) route 6.505ns (59.125%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.774 7.938 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X38Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/I5 + SLICE_X38Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/O + net (fo=1, routed) 0.539 8.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[4] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.600 + ------------------------------------------------------------------- + slack -1.319 + +Slack (VIOLATED) : -1.319ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.002ns (logic 4.497ns (40.875%) route 6.505ns (59.125%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.774 7.938 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X38Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/I5 + SLICE_X38Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/O + net (fo=1, routed) 0.539 8.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[4] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.600 + ------------------------------------------------------------------- + slack -1.319 + +Slack (VIOLATED) : -1.319ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.002ns (logic 4.497ns (40.875%) route 6.505ns (59.125%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.774 7.938 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X38Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/I5 + SLICE_X38Y49 LUT6 (Prop_lut6_I5_O) 0.124 8.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29__3/O + net (fo=1, routed) 0.539 8.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[4] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.600 + ------------------------------------------------------------------- + slack -1.319 + +Slack (VIOLATED) : -1.293ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.975ns (logic 3.586ns (32.673%) route 7.389ns (67.327%)) + Logic Levels: 15 (CARRY4=3 LUT2=1 LUT5=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.718 6.018 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X36Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/I2 + SLICE_X36Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/O + net (fo=2, routed) 0.633 6.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_23 + SLICE_X40Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/I2 + SLICE_X40Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.899 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/O + net (fo=12, routed) 1.023 7.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0_n_0 + SLICE_X41Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/I0 + SLICE_X41Y47 LUT6 (Prop_lut6_I0_O) 0.124 8.046 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/O + net (fo=1, routed) 0.528 8.574 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[8] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[8]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.574 + ------------------------------------------------------------------- + slack -1.293 + +Slack (VIOLATED) : -1.293ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.975ns (logic 3.586ns (32.673%) route 7.389ns (67.327%)) + Logic Levels: 15 (CARRY4=3 LUT2=1 LUT5=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.718 6.018 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X36Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/I2 + SLICE_X36Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/O + net (fo=2, routed) 0.633 6.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_23 + SLICE_X40Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/I2 + SLICE_X40Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.899 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/O + net (fo=12, routed) 1.023 7.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0_n_0 + SLICE_X41Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/I0 + SLICE_X41Y47 LUT6 (Prop_lut6_I0_O) 0.124 8.046 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/O + net (fo=1, routed) 0.528 8.574 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[8] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[8]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.574 + ------------------------------------------------------------------- + slack -1.293 + +Slack (VIOLATED) : -1.293ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.975ns (logic 3.586ns (32.673%) route 7.389ns (67.327%)) + Logic Levels: 15 (CARRY4=3 LUT2=1 LUT5=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.718 6.018 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X36Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/I2 + SLICE_X36Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/O + net (fo=2, routed) 0.633 6.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_23 + SLICE_X40Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/I2 + SLICE_X40Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.899 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/O + net (fo=12, routed) 1.023 7.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0_n_0 + SLICE_X41Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/I0 + SLICE_X41Y47 LUT6 (Prop_lut6_I0_O) 0.124 8.046 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/O + net (fo=1, routed) 0.528 8.574 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[8] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[8]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.574 + ------------------------------------------------------------------- + slack -1.293 + +Slack (VIOLATED) : -1.293ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.975ns (logic 3.586ns (32.673%) route 7.389ns (67.327%)) + Logic Levels: 15 (CARRY4=3 LUT2=1 LUT5=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.718 6.018 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X36Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/I2 + SLICE_X36Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/O + net (fo=2, routed) 0.633 6.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_23 + SLICE_X40Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/I2 + SLICE_X40Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.899 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/O + net (fo=12, routed) 1.023 7.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0_n_0 + SLICE_X41Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/I0 + SLICE_X41Y47 LUT6 (Prop_lut6_I0_O) 0.124 8.046 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/O + net (fo=1, routed) 0.528 8.574 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[8] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[8]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.574 + ------------------------------------------------------------------- + slack -1.293 + +Slack (VIOLATED) : -1.293ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.975ns (logic 3.586ns (32.673%) route 7.389ns (67.327%)) + Logic Levels: 15 (CARRY4=3 LUT2=1 LUT5=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.718 6.018 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X36Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/I2 + SLICE_X36Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/O + net (fo=2, routed) 0.633 6.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_23 + SLICE_X40Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/I2 + SLICE_X40Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.899 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/O + net (fo=12, routed) 1.023 7.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0_n_0 + SLICE_X41Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/I0 + SLICE_X41Y47 LUT6 (Prop_lut6_I0_O) 0.124 8.046 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/O + net (fo=1, routed) 0.528 8.574 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[8] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[8]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.574 + ------------------------------------------------------------------- + slack -1.293 + +Slack (VIOLATED) : -1.293ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.975ns (logic 3.586ns (32.673%) route 7.389ns (67.327%)) + Logic Levels: 15 (CARRY4=3 LUT2=1 LUT5=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.718 6.018 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X36Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/I2 + SLICE_X36Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/O + net (fo=2, routed) 0.633 6.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_23 + SLICE_X40Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/I2 + SLICE_X40Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.899 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/O + net (fo=12, routed) 1.023 7.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0_n_0 + SLICE_X41Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/I0 + SLICE_X41Y47 LUT6 (Prop_lut6_I0_O) 0.124 8.046 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/O + net (fo=1, routed) 0.528 8.574 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[8] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[8]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.574 + ------------------------------------------------------------------- + slack -1.293 + +Slack (VIOLATED) : -1.293ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.975ns (logic 3.586ns (32.673%) route 7.389ns (67.327%)) + Logic Levels: 15 (CARRY4=3 LUT2=1 LUT5=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.718 6.018 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X36Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/I2 + SLICE_X36Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/O + net (fo=2, routed) 0.633 6.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_23 + SLICE_X40Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/I2 + SLICE_X40Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.899 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/O + net (fo=12, routed) 1.023 7.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0_n_0 + SLICE_X41Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/I0 + SLICE_X41Y47 LUT6 (Prop_lut6_I0_O) 0.124 8.046 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/O + net (fo=1, routed) 0.528 8.574 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[8] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[8]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.574 + ------------------------------------------------------------------- + slack -1.293 + +Slack (VIOLATED) : -1.293ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.975ns (logic 3.586ns (32.673%) route 7.389ns (67.327%)) + Logic Levels: 15 (CARRY4=3 LUT2=1 LUT5=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.718 6.018 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X36Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/I2 + SLICE_X36Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/O + net (fo=2, routed) 0.633 6.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_23 + SLICE_X40Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/I2 + SLICE_X40Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.899 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/O + net (fo=12, routed) 1.023 7.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0_n_0 + SLICE_X41Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/I0 + SLICE_X41Y47 LUT6 (Prop_lut6_I0_O) 0.124 8.046 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/O + net (fo=1, routed) 0.528 8.574 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[8] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[8]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.574 + ------------------------------------------------------------------- + slack -1.293 + +Slack (VIOLATED) : -1.293ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.975ns (logic 3.586ns (32.673%) route 7.389ns (67.327%)) + Logic Levels: 15 (CARRY4=3 LUT2=1 LUT5=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.718 6.018 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X36Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/I2 + SLICE_X36Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/O + net (fo=2, routed) 0.633 6.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_23 + SLICE_X40Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/I2 + SLICE_X40Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.899 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/O + net (fo=12, routed) 1.023 7.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0_n_0 + SLICE_X41Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/I0 + SLICE_X41Y47 LUT6 (Prop_lut6_I0_O) 0.124 8.046 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/O + net (fo=1, routed) 0.528 8.574 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[8] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[8]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.574 + ------------------------------------------------------------------- + slack -1.293 + +Slack (VIOLATED) : -1.293ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.975ns (logic 3.586ns (32.673%) route 7.389ns (67.327%)) + Logic Levels: 15 (CARRY4=3 LUT2=1 LUT5=1 LUT6=6 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.718 6.018 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X36Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/I2 + SLICE_X36Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_140__0/O + net (fo=2, routed) 0.633 6.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_23 + SLICE_X40Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/I2 + SLICE_X40Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.899 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0/O + net (fo=12, routed) 1.023 7.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76__0_n_0 + SLICE_X41Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/I0 + SLICE_X41Y47 LUT6 (Prop_lut6_I0_O) 0.124 8.046 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25__3/O + net (fo=1, routed) 0.528 8.574 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[8] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[8]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.574 + ------------------------------------------------------------------- + slack -1.293 + +Slack (VIOLATED) : -1.213ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1339]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.958ns (logic 0.718ns (6.552%) route 10.240ns (93.448%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.197ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.105ns = ( 7.895 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.240 8.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X127Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1339]_i_1/I0 + SLICE_X127Y72 LUT3 (Prop_lut3_I0_O) 0.299 8.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1339]_i_1/O + net (fo=1, routed) 0.000 8.552 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1339] + SLICE_X127Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1339]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.569 7.895 + clock pessimism -0.498 7.396 + clock uncertainty -0.088 7.308 + SLICE_X127Y72 FDCE (Setup_fdce_C_D) 0.031 7.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1339] + ------------------------------------------------------------------- + required time 7.339 + arrival time -8.552 + ------------------------------------------------------------------- + slack -1.213 + +Slack (VIOLATED) : -1.213ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1339]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.958ns (logic 0.718ns (6.552%) route 10.240ns (93.448%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.197ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.105ns = ( 7.895 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.240 8.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X127Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1339]_i_1/I0 + SLICE_X127Y72 LUT3 (Prop_lut3_I0_O) 0.299 8.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1339]_i_1/O + net (fo=1, routed) 0.000 8.552 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1339] + SLICE_X127Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1339]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.569 7.895 + clock pessimism -0.498 7.396 + clock uncertainty -0.088 7.308 + SLICE_X127Y72 FDCE (Setup_fdce_C_D) 0.031 7.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1339] + ------------------------------------------------------------------- + required time 7.339 + arrival time -8.552 + ------------------------------------------------------------------- + slack -1.213 + +Slack (VIOLATED) : -1.203ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1243]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.996ns (logic 0.718ns (6.530%) route 10.278ns (93.470%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.196ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.104ns = ( 7.896 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.278 8.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X128Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1243]_i_1/I0 + SLICE_X128Y72 LUT3 (Prop_lut3_I0_O) 0.299 8.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1243]_i_1/O + net (fo=1, routed) 0.000 8.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1243] + SLICE_X128Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1243]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.570 7.896 + clock pessimism -0.498 7.397 + clock uncertainty -0.088 7.309 + SLICE_X128Y72 FDCE (Setup_fdce_C_D) 0.077 7.386 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1243] + ------------------------------------------------------------------- + required time 7.386 + arrival time -8.589 + ------------------------------------------------------------------- + slack -1.203 + +Slack (VIOLATED) : -1.203ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1243]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.996ns (logic 0.718ns (6.530%) route 10.278ns (93.470%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.196ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.104ns = ( 7.896 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.278 8.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X128Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1243]_i_1/I0 + SLICE_X128Y72 LUT3 (Prop_lut3_I0_O) 0.299 8.589 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1243]_i_1/O + net (fo=1, routed) 0.000 8.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1243] + SLICE_X128Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1243]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.570 7.896 + clock pessimism -0.498 7.397 + clock uncertainty -0.088 7.309 + SLICE_X128Y72 FDCE (Setup_fdce_C_D) 0.077 7.386 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1243] + ------------------------------------------------------------------- + required time 7.386 + arrival time -8.589 + ------------------------------------------------------------------- + slack -1.203 + +Slack (VIOLATED) : -1.195ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1296]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.936ns (logic 0.718ns (6.565%) route 10.218ns (93.435%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.199ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.107ns = ( 7.893 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.218 8.231 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X122Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1296]_i_1/I0 + SLICE_X122Y73 LUT3 (Prop_lut3_I0_O) 0.299 8.530 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1296]_i_1/O + net (fo=1, routed) 0.000 8.530 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1296] + SLICE_X122Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1296]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.567 7.893 + clock pessimism -0.498 7.394 + clock uncertainty -0.088 7.306 + SLICE_X122Y73 FDCE (Setup_fdce_C_D) 0.029 7.335 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1296] + ------------------------------------------------------------------- + required time 7.335 + arrival time -8.530 + ------------------------------------------------------------------- + slack -1.195 + +Slack (VIOLATED) : -1.195ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1296]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.936ns (logic 0.718ns (6.565%) route 10.218ns (93.435%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.199ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.107ns = ( 7.893 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.218 8.231 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X122Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1296]_i_1/I0 + SLICE_X122Y73 LUT3 (Prop_lut3_I0_O) 0.299 8.530 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1296]_i_1/O + net (fo=1, routed) 0.000 8.530 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1296] + SLICE_X122Y73 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1296]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.567 7.893 + clock pessimism -0.498 7.394 + clock uncertainty -0.088 7.306 + SLICE_X122Y73 FDCE (Setup_fdce_C_D) 0.029 7.335 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1296] + ------------------------------------------------------------------- + required time 7.335 + arrival time -8.530 + ------------------------------------------------------------------- + slack -1.195 + +Slack (VIOLATED) : -1.193ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1377]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.949ns (logic 0.718ns (6.557%) route 10.231ns (93.443%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.186ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.094ns = ( 7.906 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.231 8.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X125Y88 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1377]_i_1/I0 + SLICE_X125Y88 LUT3 (Prop_lut3_I0_O) 0.299 8.543 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1377]_i_1/O + net (fo=1, routed) 0.000 8.543 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1377] + SLICE_X125Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1377]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.580 7.906 + clock pessimism -0.498 7.407 + clock uncertainty -0.088 7.319 + SLICE_X125Y88 FDCE (Setup_fdce_C_D) 0.031 7.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1377] + ------------------------------------------------------------------- + required time 7.350 + arrival time -8.543 + ------------------------------------------------------------------- + slack -1.193 + +Slack (VIOLATED) : -1.193ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1377]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.949ns (logic 0.718ns (6.557%) route 10.231ns (93.443%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.186ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.094ns = ( 7.906 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.231 8.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X125Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1377]_i_1/I0 + SLICE_X125Y88 LUT3 (Prop_lut3_I0_O) 0.299 8.543 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1377]_i_1/O + net (fo=1, routed) 0.000 8.543 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1377] + SLICE_X125Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1377]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.580 7.906 + clock pessimism -0.498 7.407 + clock uncertainty -0.088 7.319 + SLICE_X125Y88 FDCE (Setup_fdce_C_D) 0.031 7.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1377] + ------------------------------------------------------------------- + required time 7.350 + arrival time -8.543 + ------------------------------------------------------------------- + slack -1.193 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1319]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.022ns (logic 0.744ns (6.750%) route 10.278ns (93.250%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.196ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.104ns = ( 7.896 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.278 8.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X128Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1319]_i_1/I0 + SLICE_X128Y72 LUT3 (Prop_lut3_I0_O) 0.325 8.615 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1319]_i_1/O + net (fo=1, routed) 0.000 8.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1319] + SLICE_X128Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1319]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.570 7.896 + clock pessimism -0.498 7.397 + clock uncertainty -0.088 7.309 + SLICE_X128Y72 FDCE (Setup_fdce_C_D) 0.118 7.427 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1319] + ------------------------------------------------------------------- + required time 7.427 + arrival time -8.615 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1319]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 11.022ns (logic 0.744ns (6.750%) route 10.278ns (93.250%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.196ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.104ns = ( 7.896 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.278 8.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X128Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1319]_i_1/I0 + SLICE_X128Y72 LUT3 (Prop_lut3_I0_O) 0.325 8.615 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1319]_i_1/O + net (fo=1, routed) 0.000 8.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1319] + SLICE_X128Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1319]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.570 7.896 + clock pessimism -0.498 7.397 + clock uncertainty -0.088 7.309 + SLICE_X128Y72 FDCE (Setup_fdce_C_D) 0.118 7.427 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1319] + ------------------------------------------------------------------- + required time 7.427 + arrival time -8.615 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.871ns (logic 4.497ns (41.369%) route 6.374ns (58.631%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT5=1 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.611 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/I4 + SLICE_X39Y47 LUT5 (Prop_lut5_I4_O) 0.124 7.899 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/O + net (fo=1, routed) 0.570 8.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[0] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[0]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.469 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.871ns (logic 4.497ns (41.369%) route 6.374ns (58.631%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT5=1 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.611 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/I4 + SLICE_X39Y47 LUT5 (Prop_lut5_I4_O) 0.124 7.899 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/O + net (fo=1, routed) 0.570 8.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[0] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[0]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.469 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.871ns (logic 4.497ns (41.369%) route 6.374ns (58.631%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT5=1 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.611 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/I4 + SLICE_X39Y47 LUT5 (Prop_lut5_I4_O) 0.124 7.899 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/O + net (fo=1, routed) 0.570 8.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[0] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[0]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.469 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.871ns (logic 4.497ns (41.369%) route 6.374ns (58.631%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT5=1 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 r mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 r mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.611 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/I4 + SLICE_X39Y47 LUT5 (Prop_lut5_I4_O) 0.124 7.899 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/O + net (fo=1, routed) 0.570 8.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[0] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[0]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.469 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.871ns (logic 4.497ns (41.369%) route 6.374ns (58.631%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT5=1 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.611 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/I4 + SLICE_X39Y47 LUT5 (Prop_lut5_I4_O) 0.124 7.899 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/O + net (fo=1, routed) 0.570 8.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[0] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[0]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.469 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.871ns (logic 4.497ns (41.369%) route 6.374ns (58.631%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT5=1 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 f mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 r mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 r mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.611 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/I4 + SLICE_X39Y47 LUT5 (Prop_lut5_I4_O) 0.124 7.899 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/O + net (fo=1, routed) 0.570 8.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[0] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[0]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.469 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.871ns (logic 4.497ns (41.369%) route 6.374ns (58.631%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT5=1 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.611 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/I4 + SLICE_X39Y47 LUT5 (Prop_lut5_I4_O) 0.124 7.899 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/O + net (fo=1, routed) 0.570 8.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[0] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[0]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.469 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.871ns (logic 4.497ns (41.369%) route 6.374ns (58.631%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT5=1 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.611 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/I4 + SLICE_X39Y47 LUT5 (Prop_lut5_I4_O) 0.124 7.899 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/O + net (fo=1, routed) 0.570 8.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[0] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[0]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.469 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.871ns (logic 4.497ns (41.369%) route 6.374ns (58.631%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT5=1 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.611 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/I4 + SLICE_X39Y47 LUT5 (Prop_lut5_I4_O) 0.124 7.899 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/O + net (fo=1, routed) 0.570 8.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[0] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[0]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.469 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.871ns (logic 4.497ns (41.369%) route 6.374ns (58.631%)) + Logic Levels: 16 (CARRY4=4 LUT1=1 LUT2=1 LUT5=1 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 3.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/O[1] + net (fo=7, routed) 0.618 3.774 u_mlkem_axi_slave/u_mlkem/u_vsum[5] + SLICE_X37Y46 r mem_reg_i_247/I0 + SLICE_X37Y46 LUT1 (Prop_lut1_I0_O) 0.303 4.077 f mem_reg_i_247/O + net (fo=1, routed) 0.000 4.077 mem_reg_i_247_n_0 + SLICE_X37Y46 f mem_reg_i_165/S[0] + SLICE_X37Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 4.609 f mem_reg_i_165/CO[3] + net (fo=1, routed) 0.000 4.609 mem_reg_i_165_n_0 + SLICE_X37Y47 f mem_reg_i_149/CI + SLICE_X37Y47 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 4.831 r mem_reg_i_149/O[0] + net (fo=2, routed) 0.459 5.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub10[8] + SLICE_X41Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/I5 + SLICE_X41Y45 LUT6 (Prop_lut6_I5_O) 0.299 5.589 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_85__0/O + net (fo=3, routed) 0.651 6.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_149[6] + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/I2 + SLICE_X39Y46 LUT6 (Prop_lut6_I2_O) 0.124 6.363 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_141__0/O + net (fo=2, routed) 0.677 7.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_24 + SLICE_X39Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/I3 + SLICE_X39Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1/O + net (fo=12, routed) 0.611 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_81__1_n_0 + SLICE_X39Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/I4 + SLICE_X39Y47 LUT5 (Prop_lut5_I4_O) 0.124 7.899 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__4/O + net (fo=1, routed) 0.570 8.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[0] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[0]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.469 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1510]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.985ns (logic 0.718ns (6.536%) route 10.267ns (93.464%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.191ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.099ns = ( 7.901 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.267 8.280 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X120Y83 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1510]_i_1/I0 + SLICE_X120Y83 LUT3 (Prop_lut3_I0_O) 0.299 8.579 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1510]_i_1/O + net (fo=1, routed) 0.000 8.579 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1510] + SLICE_X120Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1510]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.575 7.901 + clock pessimism -0.498 7.402 + clock uncertainty -0.088 7.314 + SLICE_X120Y83 FDCE (Setup_fdce_C_D) 0.077 7.391 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1510] + ------------------------------------------------------------------- + required time 7.391 + arrival time -8.579 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1510]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.985ns (logic 0.718ns (6.536%) route 10.267ns (93.464%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.191ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.099ns = ( 7.901 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.267 8.280 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X120Y83 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1510]_i_1/I0 + SLICE_X120Y83 LUT3 (Prop_lut3_I0_O) 0.299 8.579 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1510]_i_1/O + net (fo=1, routed) 0.000 8.579 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1510] + SLICE_X120Y83 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1510]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.575 7.901 + clock pessimism -0.498 7.402 + clock uncertainty -0.088 7.314 + SLICE_X120Y83 FDCE (Setup_fdce_C_D) 0.077 7.391 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1510] + ------------------------------------------------------------------- + required time 7.391 + arrival time -8.579 + ------------------------------------------------------------------- + slack -1.188 + +Slack (VIOLATED) : -1.187ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1502]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.930ns (logic 0.718ns (6.569%) route 10.212ns (93.431%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.198ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.106ns = ( 7.894 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.212 8.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X122Y77 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1502]_i_1/I0 + SLICE_X122Y77 LUT3 (Prop_lut3_I0_O) 0.299 8.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1502]_i_1/O + net (fo=1, routed) 0.000 8.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1502] + SLICE_X122Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1502]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.568 7.894 + clock pessimism -0.498 7.395 + clock uncertainty -0.088 7.307 + SLICE_X122Y77 FDCE (Setup_fdce_C_D) 0.029 7.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1502] + ------------------------------------------------------------------- + required time 7.336 + arrival time -8.523 + ------------------------------------------------------------------- + slack -1.187 + +Slack (VIOLATED) : -1.187ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1502]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.930ns (logic 0.718ns (6.569%) route 10.212ns (93.431%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.198ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.106ns = ( 7.894 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.212 8.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X122Y77 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1502]_i_1/I0 + SLICE_X122Y77 LUT3 (Prop_lut3_I0_O) 0.299 8.523 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1502]_i_1/O + net (fo=1, routed) 0.000 8.523 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1502] + SLICE_X122Y77 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1502]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.568 7.894 + clock pessimism -0.498 7.395 + clock uncertainty -0.088 7.307 + SLICE_X122Y77 FDCE (Setup_fdce_C_D) 0.029 7.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1502] + ------------------------------------------------------------------- + required time 7.336 + arrival time -8.523 + ------------------------------------------------------------------- + slack -1.187 + +Slack (VIOLATED) : -1.183ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1490]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.927ns (logic 0.718ns (6.571%) route 10.209ns (93.429%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.197ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.105ns = ( 7.895 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.209 8.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X119Y71 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1490]_i_1/I0 + SLICE_X119Y71 LUT3 (Prop_lut3_I0_O) 0.299 8.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1490]_i_1/O + net (fo=1, routed) 0.000 8.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1490] + SLICE_X119Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1490]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.569 7.895 + clock pessimism -0.498 7.396 + clock uncertainty -0.088 7.308 + SLICE_X119Y71 FDCE (Setup_fdce_C_D) 0.029 7.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1490] + ------------------------------------------------------------------- + required time 7.337 + arrival time -8.520 + ------------------------------------------------------------------- + slack -1.183 + +Slack (VIOLATED) : -1.183ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1490]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.927ns (logic 0.718ns (6.571%) route 10.209ns (93.429%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.197ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.105ns = ( 7.895 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.209 8.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X119Y71 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1490]_i_1/I0 + SLICE_X119Y71 LUT3 (Prop_lut3_I0_O) 0.299 8.520 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1490]_i_1/O + net (fo=1, routed) 0.000 8.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1490] + SLICE_X119Y71 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1490]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.569 7.895 + clock pessimism -0.498 7.396 + clock uncertainty -0.088 7.308 + SLICE_X119Y71 FDCE (Setup_fdce_C_D) 0.029 7.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1490] + ------------------------------------------------------------------- + required time 7.337 + arrival time -8.520 + ------------------------------------------------------------------- + slack -1.183 + +Slack (VIOLATED) : -1.183ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1383]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.940ns (logic 0.718ns (6.563%) route 10.222ns (93.437%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.186ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.094ns = ( 7.906 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.222 8.234 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X115Y94 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1383]_i_1/I0 + SLICE_X115Y94 LUT3 (Prop_lut3_I0_O) 0.299 8.533 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1383]_i_1/O + net (fo=1, routed) 0.000 8.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1383] + SLICE_X115Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1383]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.580 7.906 + clock pessimism -0.498 7.407 + clock uncertainty -0.088 7.319 + SLICE_X115Y94 FDCE (Setup_fdce_C_D) 0.031 7.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1383] + ------------------------------------------------------------------- + required time 7.350 + arrival time -8.533 + ------------------------------------------------------------------- + slack -1.183 + +Slack (VIOLATED) : -1.183ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1383]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.940ns (logic 0.718ns (6.563%) route 10.222ns (93.437%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.186ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.094ns = ( 7.906 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.222 8.234 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X115Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1383]_i_1/I0 + SLICE_X115Y94 LUT3 (Prop_lut3_I0_O) 0.299 8.533 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1383]_i_1/O + net (fo=1, routed) 0.000 8.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1383] + SLICE_X115Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1383]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.580 7.906 + clock pessimism -0.498 7.407 + clock uncertainty -0.088 7.319 + SLICE_X115Y94 FDCE (Setup_fdce_C_D) 0.031 7.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1383] + ------------------------------------------------------------------- + required time 7.350 + arrival time -8.533 + ------------------------------------------------------------------- + slack -1.183 + +Slack (VIOLATED) : -1.177ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1360]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.964ns (logic 0.746ns (6.804%) route 10.218ns (93.196%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.199ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.107ns = ( 7.893 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.218 8.231 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X122Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1360]_i_1/I0 + SLICE_X122Y73 LUT3 (Prop_lut3_I0_O) 0.327 8.558 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1360]_i_1/O + net (fo=1, routed) 0.000 8.558 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1360] + SLICE_X122Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1360]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.567 7.893 + clock pessimism -0.498 7.394 + clock uncertainty -0.088 7.306 + SLICE_X122Y73 FDCE (Setup_fdce_C_D) 0.075 7.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1360] + ------------------------------------------------------------------- + required time 7.381 + arrival time -8.558 + ------------------------------------------------------------------- + slack -1.177 + +Slack (VIOLATED) : -1.177ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1360]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.964ns (logic 0.746ns (6.804%) route 10.218ns (93.196%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.199ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.107ns = ( 7.893 - 10.000 ) + Source Clock Delay (SCD): -2.407ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.869 -2.407 + SLICE_X32Y60 FDCE 0.000 -2.407 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/C + SLICE_X32Y60 FDCE (Prop_fdce_C_Q) 0.419 -1.988 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state_reg[1]/Q + net (fo=1344, routed) 10.218 8.231 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_0_in0_in + SLICE_X122Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1360]_i_1/I0 + SLICE_X122Y73 LUT3 (Prop_lut3_I0_O) 0.327 8.558 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1360]_i_1/O + net (fo=1, routed) 0.000 8.558 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/p_1_in[1360] + SLICE_X122Y73 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1360]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.567 7.893 + clock pessimism -0.498 7.394 + clock uncertainty -0.088 7.306 + SLICE_X122Y73 FDCE (Setup_fdce_C_D) 0.075 7.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1360] + ------------------------------------------------------------------- + required time 7.381 + arrival time -8.558 + ------------------------------------------------------------------- + slack -1.177 + +Slack (VIOLATED) : -1.176ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 4.411ns (40.621%) route 6.448ns (59.379%)) + Logic Levels: 16 (CARRY4=5 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.661 5.961 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/I1 + SLICE_X38Y47 LUT3 (Prop_lut3_I1_O) 0.124 6.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/O + net (fo=1, routed) 0.000 6.085 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174_n_0 + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/S[0] + SLICE_X38Y47 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/CO[3] + net (fo=1, routed) 0.000 6.617 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91_n_0 + SLICE_X38Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/CI + SLICE_X38Y48 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 6.856 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/O[2] + net (fo=1, routed) 0.778 7.635 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[10] + SLICE_X41Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/I4 + SLICE_X41Y48 LUT6 (Prop_lut6_I4_O) 0.302 7.937 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/O + net (fo=1, routed) 0.521 8.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[11] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[11]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.457 + ------------------------------------------------------------------- + slack -1.176 + +Slack (VIOLATED) : -1.176ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 4.411ns (40.621%) route 6.448ns (59.379%)) + Logic Levels: 16 (CARRY4=5 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.661 5.961 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/I1 + SLICE_X38Y47 LUT3 (Prop_lut3_I1_O) 0.124 6.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/O + net (fo=1, routed) 0.000 6.085 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174_n_0 + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/S[0] + SLICE_X38Y47 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/CO[3] + net (fo=1, routed) 0.000 6.617 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91_n_0 + SLICE_X38Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/CI + SLICE_X38Y48 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 6.856 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/O[2] + net (fo=1, routed) 0.778 7.635 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[10] + SLICE_X41Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/I4 + SLICE_X41Y48 LUT6 (Prop_lut6_I4_O) 0.302 7.937 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/O + net (fo=1, routed) 0.521 8.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[11] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[11]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.457 + ------------------------------------------------------------------- + slack -1.176 + +Slack (VIOLATED) : -1.176ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 4.411ns (40.621%) route 6.448ns (59.379%)) + Logic Levels: 16 (CARRY4=5 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.661 5.961 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/I1 + SLICE_X38Y47 LUT3 (Prop_lut3_I1_O) 0.124 6.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/O + net (fo=1, routed) 0.000 6.085 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174_n_0 + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/S[0] + SLICE_X38Y47 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/CO[3] + net (fo=1, routed) 0.000 6.617 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91_n_0 + SLICE_X38Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/CI + SLICE_X38Y48 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 6.856 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/O[2] + net (fo=1, routed) 0.778 7.635 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[10] + SLICE_X41Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/I4 + SLICE_X41Y48 LUT6 (Prop_lut6_I4_O) 0.302 7.937 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/O + net (fo=1, routed) 0.521 8.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[11] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[11]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.457 + ------------------------------------------------------------------- + slack -1.176 + +Slack (VIOLATED) : -1.176ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 4.411ns (40.621%) route 6.448ns (59.379%)) + Logic Levels: 16 (CARRY4=5 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.661 5.961 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/I1 + SLICE_X38Y47 LUT3 (Prop_lut3_I1_O) 0.124 6.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/O + net (fo=1, routed) 0.000 6.085 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174_n_0 + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/S[0] + SLICE_X38Y47 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/CO[3] + net (fo=1, routed) 0.000 6.617 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91_n_0 + SLICE_X38Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/CI + SLICE_X38Y48 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 6.856 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/O[2] + net (fo=1, routed) 0.778 7.635 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[10] + SLICE_X41Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/I4 + SLICE_X41Y48 LUT6 (Prop_lut6_I4_O) 0.302 7.937 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/O + net (fo=1, routed) 0.521 8.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[11] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[11]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.457 + ------------------------------------------------------------------- + slack -1.176 + +Slack (VIOLATED) : -1.176ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 4.411ns (40.621%) route 6.448ns (59.379%)) + Logic Levels: 16 (CARRY4=5 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.661 5.961 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X38Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/I1 + SLICE_X38Y47 LUT3 (Prop_lut3_I1_O) 0.124 6.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/O + net (fo=1, routed) 0.000 6.085 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174_n_0 + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/S[0] + SLICE_X38Y47 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/CO[3] + net (fo=1, routed) 0.000 6.617 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91_n_0 + SLICE_X38Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/CI + SLICE_X38Y48 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 6.856 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/O[2] + net (fo=1, routed) 0.778 7.635 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[10] + SLICE_X41Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/I4 + SLICE_X41Y48 LUT6 (Prop_lut6_I4_O) 0.302 7.937 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/O + net (fo=1, routed) 0.521 8.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[11] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[11]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.457 + ------------------------------------------------------------------- + slack -1.176 + +Slack (VIOLATED) : -1.176ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 4.411ns (40.621%) route 6.448ns (59.379%)) + Logic Levels: 16 (CARRY4=5 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.661 5.961 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X38Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/I1 + SLICE_X38Y47 LUT3 (Prop_lut3_I1_O) 0.124 6.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/O + net (fo=1, routed) 0.000 6.085 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174_n_0 + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/S[0] + SLICE_X38Y47 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/CO[3] + net (fo=1, routed) 0.000 6.617 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91_n_0 + SLICE_X38Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/CI + SLICE_X38Y48 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 6.856 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/O[2] + net (fo=1, routed) 0.778 7.635 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[10] + SLICE_X41Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/I4 + SLICE_X41Y48 LUT6 (Prop_lut6_I4_O) 0.302 7.937 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/O + net (fo=1, routed) 0.521 8.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[11] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[11]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.457 + ------------------------------------------------------------------- + slack -1.176 + +Slack (VIOLATED) : -1.176ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 4.411ns (40.621%) route 6.448ns (59.379%)) + Logic Levels: 16 (CARRY4=5 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.661 5.961 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X38Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/I1 + SLICE_X38Y47 LUT3 (Prop_lut3_I1_O) 0.124 6.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/O + net (fo=1, routed) 0.000 6.085 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174_n_0 + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/S[0] + SLICE_X38Y47 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/CO[3] + net (fo=1, routed) 0.000 6.617 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91_n_0 + SLICE_X38Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/CI + SLICE_X38Y48 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 6.856 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/O[2] + net (fo=1, routed) 0.778 7.635 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[10] + SLICE_X41Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/I4 + SLICE_X41Y48 LUT6 (Prop_lut6_I4_O) 0.302 7.937 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/O + net (fo=1, routed) 0.521 8.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[11] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[11]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.457 + ------------------------------------------------------------------- + slack -1.176 + +Slack (VIOLATED) : -1.176ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 4.411ns (40.621%) route 6.448ns (59.379%)) + Logic Levels: 16 (CARRY4=5 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.661 5.961 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X38Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/I1 + SLICE_X38Y47 LUT3 (Prop_lut3_I1_O) 0.124 6.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/O + net (fo=1, routed) 0.000 6.085 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174_n_0 + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/S[0] + SLICE_X38Y47 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/CO[3] + net (fo=1, routed) 0.000 6.617 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91_n_0 + SLICE_X38Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/CI + SLICE_X38Y48 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 6.856 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/O[2] + net (fo=1, routed) 0.778 7.635 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[10] + SLICE_X41Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/I4 + SLICE_X41Y48 LUT6 (Prop_lut6_I4_O) 0.302 7.937 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/O + net (fo=1, routed) 0.521 8.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[11] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[11]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.457 + ------------------------------------------------------------------- + slack -1.176 + +Slack (VIOLATED) : -1.176ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 4.411ns (40.621%) route 6.448ns (59.379%)) + Logic Levels: 16 (CARRY4=5 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.661 5.961 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X38Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/I1 + SLICE_X38Y47 LUT3 (Prop_lut3_I1_O) 0.124 6.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/O + net (fo=1, routed) 0.000 6.085 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174_n_0 + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/S[0] + SLICE_X38Y47 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/CO[3] + net (fo=1, routed) 0.000 6.617 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91_n_0 + SLICE_X38Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/CI + SLICE_X38Y48 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 6.856 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/O[2] + net (fo=1, routed) 0.778 7.635 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[10] + SLICE_X41Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/I4 + SLICE_X41Y48 LUT6 (Prop_lut6_I4_O) 0.302 7.937 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/O + net (fo=1, routed) 0.521 8.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[11] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[11]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.457 + ------------------------------------------------------------------- + slack -1.176 + +Slack (VIOLATED) : -1.176ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 4.411ns (40.621%) route 6.448ns (59.379%)) + Logic Levels: 16 (CARRY4=5 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.012ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.891ns = ( 8.109 - 10.000 ) + Source Clock Delay (SCD): -2.402ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.874 -2.402 + SLICE_X31Y52 FDCE 0.000 -2.402 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/C + SLICE_X31Y52 FDCE (Prop_fdce_C_Q) 0.456 -1.946 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[1]_replica_2/Q + net (fo=48, routed) 1.314 -0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg_n_0_[1]_repN_2_alias + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/I2 + SLICE_X29Y50 LUT6 (Prop_lut6_I2_O) 0.124 -0.507 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411/O + net (fo=1, routed) 0.000 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_411_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/I1 + SLICE_X29Y50 MUXF7 (Prop_muxf7_I1_O) 0.245 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372/O + net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_372_n_0 + SLICE_X29Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/I0 + SLICE_X29Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 -0.158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353/O + net (fo=1, routed) 0.795 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_353_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/I5 + SLICE_X31Y50 LUT6 (Prop_lut6_I5_O) 0.316 0.953 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346/O + net (fo=1, routed) 0.000 0.953 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_346_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/I0 + SLICE_X31Y50 MUXF7 (Prop_muxf7_I0_O) 0.238 1.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331/O + net (fo=1, routed) 0.000 1.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_331_n_0 + SLICE_X31Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/I0 + SLICE_X31Y50 MUXF8 (Prop_muxf8_I0_O) 0.104 1.295 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_310/O + net (fo=11, routed) 0.679 1.974 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_awidx_reg[7] + SLICE_X34Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/I1 + SLICE_X34Y45 LUT2 (Prop_lut2_I1_O) 0.316 2.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203/O + net (fo=1, routed) 0.000 2.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_203_n_0 + SLICE_X34Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/S[0] + SLICE_X34Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 2.822 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0/CO[3] + net (fo=1, routed) 0.000 2.822 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_116__0_n_0 + SLICE_X34Y46 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CI + SLICE_X34Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.936 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_175/CO[3] + net (fo=1, routed) 0.000 2.936 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/CO[0] + SLICE_X34Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/CI + SLICE_X34Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 3.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_144__0/O[2] + net (fo=10, routed) 0.920 4.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_8[2] + SLICE_X35Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/I0 + SLICE_X35Y46 LUT5 (Prop_lut5_I0_O) 0.302 4.396 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148/O + net (fo=11, routed) 0.780 5.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_148_n_0 + SLICE_X38Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/I5 + SLICE_X38Y45 LUT6 (Prop_lut6_I5_O) 0.124 5.300 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_replica/O + net (fo=22, routed) 0.661 5.961 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_176_n_0_repN + SLICE_X38Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/I1 + SLICE_X38Y47 LUT3 (Prop_lut3_I1_O) 0.124 6.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174/O + net (fo=1, routed) 0.000 6.085 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_174_n_0 + SLICE_X38Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/S[0] + SLICE_X38Y47 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/CO[3] + net (fo=1, routed) 0.000 6.617 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91_n_0 + SLICE_X38Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/CI + SLICE_X38Y48 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 6.856 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_80__0/O[2] + net (fo=1, routed) 0.778 7.635 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[10] + SLICE_X41Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/I4 + SLICE_X41Y48 LUT6 (Prop_lut6_I4_O) 0.302 7.937 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22__3/O + net (fo=1, routed) 0.521 8.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[11] + RAMB18_X2Y19 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.783 8.109 + clock pessimism -0.498 7.610 + clock uncertainty -0.088 7.522 + RAMB18_X2Y19 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[11]) + -0.241 7.281 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 7.281 + arrival time -8.457 + ------------------------------------------------------------------- + slack -1.176 + +Slack (VIOLATED) : -1.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 3.044ns (28.031%) route 7.815ns (71.969%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 6.712 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.446 7.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[10] + SLICE_X45Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/I1 + SLICE_X45Y48 LUT6 (Prop_lut6_I1_O) 0.302 7.460 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/O + net (fo=1, routed) 0.307 7.767 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132_n_0 + SLICE_X44Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 7.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/O + net (fo=1, routed) 0.461 8.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.352 + ------------------------------------------------------------------- + slack -1.175 + +Slack (VIOLATED) : -1.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 3.044ns (28.031%) route 7.815ns (71.969%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 6.712 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.446 7.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[10] + SLICE_X45Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/I1 + SLICE_X45Y48 LUT6 (Prop_lut6_I1_O) 0.302 7.460 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/O + net (fo=1, routed) 0.307 7.767 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132_n_0 + SLICE_X44Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 7.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/O + net (fo=1, routed) 0.461 8.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.352 + ------------------------------------------------------------------- + slack -1.175 + +Slack (VIOLATED) : -1.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 3.044ns (28.031%) route 7.815ns (71.969%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 6.712 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.446 7.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[10] + SLICE_X45Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/I1 + SLICE_X45Y48 LUT6 (Prop_lut6_I1_O) 0.302 7.460 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/O + net (fo=1, routed) 0.307 7.767 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132_n_0 + SLICE_X44Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 7.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/O + net (fo=1, routed) 0.461 8.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.352 + ------------------------------------------------------------------- + slack -1.175 + +Slack (VIOLATED) : -1.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 3.044ns (28.031%) route 7.815ns (71.969%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 6.712 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.446 7.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[10] + SLICE_X45Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/I1 + SLICE_X45Y48 LUT6 (Prop_lut6_I1_O) 0.302 7.460 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/O + net (fo=1, routed) 0.307 7.767 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132_n_0 + SLICE_X44Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 7.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/O + net (fo=1, routed) 0.461 8.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.352 + ------------------------------------------------------------------- + slack -1.175 + +Slack (VIOLATED) : -1.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 3.044ns (28.031%) route 7.815ns (71.969%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 6.712 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.446 7.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[10] + SLICE_X45Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/I1 + SLICE_X45Y48 LUT6 (Prop_lut6_I1_O) 0.302 7.460 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/O + net (fo=1, routed) 0.307 7.767 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132_n_0 + SLICE_X44Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 7.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/O + net (fo=1, routed) 0.461 8.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.352 + ------------------------------------------------------------------- + slack -1.175 + +Slack (VIOLATED) : -1.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 3.044ns (28.031%) route 7.815ns (71.969%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 6.712 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.446 7.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[10] + SLICE_X45Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/I1 + SLICE_X45Y48 LUT6 (Prop_lut6_I1_O) 0.302 7.460 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/O + net (fo=1, routed) 0.307 7.767 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132_n_0 + SLICE_X44Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 7.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/O + net (fo=1, routed) 0.461 8.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.352 + ------------------------------------------------------------------- + slack -1.175 + +Slack (VIOLATED) : -1.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 3.044ns (28.031%) route 7.815ns (71.969%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 6.712 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.446 7.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[10] + SLICE_X45Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/I1 + SLICE_X45Y48 LUT6 (Prop_lut6_I1_O) 0.302 7.460 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/O + net (fo=1, routed) 0.307 7.767 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132_n_0 + SLICE_X44Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 7.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/O + net (fo=1, routed) 0.461 8.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.352 + ------------------------------------------------------------------- + slack -1.175 + +Slack (VIOLATED) : -1.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 3.044ns (28.031%) route 7.815ns (71.969%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 6.712 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.446 7.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[10] + SLICE_X45Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/I1 + SLICE_X45Y48 LUT6 (Prop_lut6_I1_O) 0.302 7.460 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/O + net (fo=1, routed) 0.307 7.767 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132_n_0 + SLICE_X44Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 7.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/O + net (fo=1, routed) 0.461 8.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.352 + ------------------------------------------------------------------- + slack -1.175 + +Slack (VIOLATED) : -1.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 3.044ns (28.031%) route 7.815ns (71.969%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 6.712 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.446 7.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[10] + SLICE_X45Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/I1 + SLICE_X45Y48 LUT6 (Prop_lut6_I1_O) 0.302 7.460 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/O + net (fo=1, routed) 0.307 7.767 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132_n_0 + SLICE_X44Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 7.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/O + net (fo=1, routed) 0.461 8.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.352 + ------------------------------------------------------------------- + slack -1.175 + +Slack (VIOLATED) : -1.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: mlkem_clk_clk_pll + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (mlkem_clk_clk_pll rise@10.000ns - mlkem_clk_clk_pll rise@0.000ns) + Data Path Delay: 10.859ns (logic 3.044ns (28.031%) route 7.815ns (71.969%)) + Logic Levels: 13 (CARRY4=3 LUT4=1 LUT5=1 LUT6=7 MUXF7=1) + Clock Path Skew: 0.013ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.068ns = ( 7.932 - 10.000 ) + Source Clock Delay (SCD): -2.508ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.088ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.162ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk_clk_pll rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.768 -2.508 + SLICE_X67Y61 FDCE 0.000 -2.508 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/C + SLICE_X67Y61 FDCE (Prop_fdce_C_Q) 0.456 -2.052 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1/Q + net (fo=103, routed) 0.984 -1.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[7]_rep__1_n_0 + SLICE_X71Y63 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/I4 + SLICE_X71Y63 LUT6 (Prop_lut6_I4_O) 0.124 -0.943 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377/O + net (fo=2, routed) 1.056 0.113 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_377_n_0 + SLICE_X66Y60 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/I3 + SLICE_X66Y60 LUT6 (Prop_lut6_I3_O) 0.124 0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171/O + net (fo=1, routed) 1.067 1.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_171_n_0 + SLICE_X59Y55 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/I0 + SLICE_X59Y55 LUT6 (Prop_lut6_I0_O) 0.124 1.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81/O + net (fo=4, routed) 1.002 2.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_81_n_0 + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/I5 + SLICE_X49Y53 LUT6 (Prop_lut6_I5_O) 0.124 2.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_48/O + net (fo=1, routed) 0.000 2.553 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/data3[5] + SLICE_X49Y53 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/I1 + SLICE_X49Y53 MUXF7 (Prop_muxf7_I1_O) 0.217 2.770 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22/O + net (fo=1, routed) 0.770 3.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_22_n_0 + SLICE_X47Y49 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/I2 + SLICE_X47Y49 LUT5 (Prop_lut5_I2_O) 0.299 3.839 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_11/O + net (fo=2, routed) 0.884 4.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/p_0_in0_in + SLICE_X44Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I5 + SLICE_X44Y45 LUT6 (Prop_lut6_I5_O) 0.124 4.847 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.840 5.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X43Y45 LUT4 (Prop_lut4_I2_O) 0.124 5.810 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 5.810 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X43Y45 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X43Y45 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.342 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X43Y46 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X43Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.456 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 6.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X43Y47 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 6.712 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.446 7.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/D[10] + SLICE_X45Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/I1 + SLICE_X45Y48 LUT6 (Prop_lut6_I1_O) 0.302 7.460 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132/O + net (fo=1, routed) 0.307 7.767 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_132_n_0 + SLICE_X44Y50 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 7.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__4_comp/O + net (fo=1, routed) 0.461 8.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X2Y10 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk_clk_pll rise edge) + 10.000 10.000 r + clock source latency -5.674 4.326 + propagated clock network latency + 3.607 7.932 + clock pessimism -0.426 7.506 + clock uncertainty -0.088 7.417 + RAMB36_X2Y10 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 7.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 7.176 + arrival time -8.352 + ------------------------------------------------------------------- + slack -1.175 + + + + diff --git a/fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt b/fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt index 2fdd8cd..370c7fd 100644 --- a/fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt +++ b/fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt @@ -1,5215 +1,16499 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +<<<<<<< Updated upstream +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 +| Date : Fri Jul 10 04:14:54 2026 | Host : fedora running 64-bit unknown -| Command : report_timing -from [get_clocks mlkem_clk_clk_pll] -to [get_clocks mlkem_clk_clk_pll] -delay_type max -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/mlkem_clk_timing.rpt +| Command : report_timing -from [get_clocks sys_clk] -to [get_clocks sys_clk] -delay_type max -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Report -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 +| Date : Sat Jul 11 09:20:56 2026 +| Host : fedora running 64-bit unknown +| Command : report_timing -from [get_clocks mlkem_clk] -to [get_clocks mlkem_clk] -delay_type max -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt +| Design : soc_top +| Device : 7a200t-fbg676 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Report + +Slack (MET) : 0.070ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 + required time 13.354 + arrival time -13.208 ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O + net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732] + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732] ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 + required time 10.626 + arrival time -10.555 ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.070 + +Slack (MET) : 0.070ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 + required time 13.354 + arrival time -13.208 ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O + net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732] + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732] ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 + required time 10.626 + arrival time -10.555 ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.070 + +Slack (MET) : 0.070ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 + required time 13.354 + arrival time -13.208 ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O + net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732] + SLICE_X145Y37 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732] ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 + required time 10.626 + arrival time -10.555 ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.070 + +Slack (MET) : 0.070ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 + required time 13.354 + arrival time -13.208 ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O + net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732] + SLICE_X145Y37 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732] ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 + required time 10.626 + arrival time -10.555 ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.070 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 + required time 13.354 + arrival time -13.208 ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 + required time 10.168 + arrival time -10.080 ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 + required time 13.354 + arrival time -13.208 ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 + required time 10.168 + arrival time -10.080 ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 + required time 13.354 + arrival time -13.208 ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 + required time 10.168 + arrival time -10.080 ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 + required time 13.354 + arrival time -13.208 ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 + required time 10.168 + arrival time -10.080 ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 + required time 13.354 + arrival time -13.208 ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 + required time 10.168 + arrival time -10.080 ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 + required time 13.354 + arrival time -13.208 ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.146 + +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 + required time 10.168 + arrival time -10.080 ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 + required time 17.194 + arrival time -16.951 ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.243 + +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 + required time 10.168 + arrival time -10.080 ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 + required time 17.194 + arrival time -16.951 ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.243 + +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 + required time 10.168 + arrival time -10.080 ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 + required time 17.194 + arrival time -16.951 ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.243 + +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 + required time 10.168 + arrival time -10.080 ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 + required time 17.194 + arrival time -16.951 ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.243 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 + required time 10.168 + arrival time -10.080 ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.088 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 + required time 17.194 + arrival time -16.922 ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.272 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 + required time 10.168 + arrival time -10.077 ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 + required time 17.194 + arrival time -16.922 ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.272 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 + required time 10.168 + arrival time -10.077 ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 + required time 17.194 + arrival time -16.922 ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.272 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 + required time 10.168 + arrival time -10.077 ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 + required time 17.194 + arrival time -16.922 ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.272 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 + required time 10.168 + arrival time -10.077 ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 + required time 13.354 + arrival time -13.079 ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 + required time 10.168 + arrival time -10.077 ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 + required time 13.354 + arrival time -13.079 ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 + required time 10.168 + arrival time -10.077 ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 + required time 13.354 + arrival time -13.079 ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 + required time 10.168 + arrival time -10.077 ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 + required time 13.354 + arrival time -13.079 ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 + required time 10.168 + arrival time -10.077 ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 + required time 13.354 + arrival time -13.079 ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 + required time 10.168 + arrival time -10.077 ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 + required time 13.354 + arrival time -13.079 ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 + required time 10.168 + arrival time -10.077 ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.091 + +Slack (MET) : 0.128ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 + required time 13.354 + arrival time -13.079 ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948] + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 + required time 10.701 + arrival time -10.573 ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.128 + +Slack (MET) : 0.128ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 + required time 13.354 + arrival time -13.079 ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948] + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 + required time 10.701 + arrival time -10.573 ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.128 + +Slack (MET) : 0.128ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 + required time 13.354 + arrival time -13.079 ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948] + SLICE_X163Y34 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 + required time 10.701 + arrival time -10.573 ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.128 + +Slack (MET) : 0.128ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948] + SLICE_X163Y34 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948] + ------------------------------------------------------------------- + required time 10.701 + arrival time -10.573 + ------------------------------------------------------------------- + slack 0.128 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.135ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O + net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731] + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.491 + ------------------------------------------------------------------- + slack 0.135 + +Slack (MET) : 0.135ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O + net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731] + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.491 + ------------------------------------------------------------------- + slack 0.135 + +Slack (MET) : 0.135ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O + net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731] + SLICE_X145Y37 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.491 + ------------------------------------------------------------------- + slack 0.135 + +Slack (MET) : 0.135ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O + net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731] + SLICE_X145Y37 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.491 + ------------------------------------------------------------------- + slack 0.135 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.159ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S + SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O + net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943] + SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943] ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 + required time 10.750 + arrival time -10.591 ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.159 + +Slack (MET) : 0.159ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 + required time 13.354 + arrival time -13.030 ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S + SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O + net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943] + SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943] ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 + required time 10.750 + arrival time -10.591 ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.159 + +Slack (MET) : 0.159ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 + required time 13.354 + arrival time -13.030 ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S + SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O + net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943] + SLICE_X162Y34 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943] ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 + required time 10.750 + arrival time -10.591 ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.159 + +Slack (MET) : 0.159ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 + required time 13.354 + arrival time -13.030 ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S + SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O + net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943] + SLICE_X162Y34 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943] ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 + required time 10.750 + arrival time -10.591 ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.159 + +Slack (MET) : 0.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 + required time 13.354 + arrival time -13.030 ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2 + SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O + net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0 + SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0 + SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O + net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975] + SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 3.833 11.158 + clock pessimism -0.498 10.660 + clock uncertainty -0.093 10.567 + SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975] ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 + required time 10.631 + arrival time -10.455 ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.175 + +Slack (MET) : 0.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 + required time 13.354 + arrival time -13.030 ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.324 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X155Y43 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2 + SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O + net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0 + SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0 + SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O + net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975] + SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 3.833 11.158 + clock pessimism -0.498 10.660 + clock uncertainty -0.093 10.567 + SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 + required time 10.631 + arrival time -10.455 ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.175 + +Slack (MET) : 0.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 + required time 13.354 + arrival time -13.026 ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2 + SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O + net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0 + SLICE_X155Y43 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0 + SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O + net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975] + SLICE_X155Y43 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 3.833 11.158 + clock pessimism -0.498 10.660 + clock uncertainty -0.093 10.567 + SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 + required time 10.631 + arrival time -10.455 ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.175 + +Slack (MET) : 0.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 + required time 13.354 + arrival time -13.026 ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X155Y43 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2 + SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O + net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0 + SLICE_X155Y43 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0 + SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O + net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975] + SLICE_X155Y43 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 3.833 11.158 + clock pessimism -0.498 10.660 + clock uncertainty -0.093 10.567 + SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 + required time 10.631 + arrival time -10.455 ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.175 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.214ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 + required time 13.354 + arrival time -13.026 ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2 + SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O + net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0 + SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0 + SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888] + SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.907 11.232 + clock pessimism -0.498 10.734 + clock uncertainty -0.093 10.641 + SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888] ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 + required time 10.754 + arrival time -10.573 ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.214ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 + required time 13.354 + arrival time -13.026 ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X162Y40 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2 + SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O + net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0 + SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0 + SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888] + SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.907 11.232 + clock pessimism -0.498 10.734 + clock uncertainty -0.093 10.641 + SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888] ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 + required time 10.754 + arrival time -10.573 ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.214ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 + required time 13.354 + arrival time -13.026 ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2 + SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O + net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0 + SLICE_X162Y40 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0 + SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888] + SLICE_X162Y40 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.907 11.232 + clock pessimism -0.498 10.734 + clock uncertainty -0.093 10.641 + SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888] ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 + required time 10.754 + arrival time -10.573 ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.214ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 + required time 13.354 + arrival time -13.026 ------------------------------------------------------------------- - slack 11.403 + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X162Y40 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2 + SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O + net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0 + SLICE_X162Y40 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0 + SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888] + SLICE_X162Y40 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + ------------------------------------------------------------------- ------------------- -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.907 11.232 + clock pessimism -0.498 10.734 + clock uncertainty -0.093 10.641 + SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888] + ------------------------------------------------------------------- + required time 10.754 + arrival time -10.573 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 + required time 13.354 + arrival time -13.026 ------------------------------------------------------------------- - slack 11.414 + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 + required time 13.354 + arrival time -13.026 ------------------------------------------------------------------- - slack 11.414 + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 + required time 13.354 + arrival time -13.026 ------------------------------------------------------------------- - slack 11.414 + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 + required time 13.354 + arrival time -13.026 ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.328 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 + required time 10.252 + arrival time -10.071 ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] + 3.381 17.706 + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 + required time 17.242 + arrival time -16.913 ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.329 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 + required time 10.252 + arrival time -10.071 ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] + 3.381 17.706 + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 + required time 17.242 + arrival time -16.913 ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.329 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 + required time 10.252 + arrival time -10.071 ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.381 17.706 + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 + required time 17.242 + arrival time -16.913 ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.329 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 + required time 10.252 + arrival time -10.071 ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.381 17.706 + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 + required time 17.242 + arrival time -16.913 ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.329 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 + required time 10.252 + arrival time -10.071 ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.373 17.699 + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 + required time 17.186 + arrival time -16.854 ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.332 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 + required time 10.252 + arrival time -10.071 ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] + 3.373 17.699 + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 + required time 17.186 + arrival time -16.854 ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.332 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 + required time 10.252 + arrival time -10.071 ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.181 + +Slack (MET) : 0.185ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] + 3.373 17.699 + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 + required time 17.186 + arrival time -16.854 ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.332 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y33 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S + SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O + net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812] + SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] + 3.902 11.227 + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 + required time 10.700 + arrival time -10.515 ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + slack 0.185 + +Slack (MET) : 0.185ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] + 3.373 17.699 + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 + required time 17.186 + arrival time -16.854 ------------------------------------------------------------------- - slack 11.505 + slack 0.332 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y33 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S + SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O + net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812] + SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + ------------------------------------------------------------------- ------------------- -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.902 11.227 + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] + ------------------------------------------------------------------- + required time 10.700 + arrival time -10.515 + ------------------------------------------------------------------- + slack 0.185 + +Slack (MET) : 0.185ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 + required time 13.354 + arrival time -13.010 ------------------------------------------------------------------- - slack 11.505 + slack 0.344 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y33 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S + SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O + net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812] + SLICE_X160Y33 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + ------------------------------------------------------------------- ------------------- -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.902 11.227 + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] + ------------------------------------------------------------------- + required time 10.700 + arrival time -10.515 + ------------------------------------------------------------------- + slack 0.185 + +Slack (MET) : 0.185ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 + required time 13.354 + arrival time -13.010 ------------------------------------------------------------------- - slack 11.505 + slack 0.344 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y33 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S + SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O + net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812] + SLICE_X160Y33 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + ------------------------------------------------------------------- ------------------- -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.902 11.227 + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] + ------------------------------------------------------------------- + required time 10.700 + arrival time -10.515 + ------------------------------------------------------------------- + slack 0.185 + +Slack (MET) : 0.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.992ns (logic 0.732ns (5.634%) route 12.260ns (94.366%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 + required time 13.354 + arrival time -13.010 ------------------------------------------------------------------- - slack 11.519 + slack 0.344 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.513 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/O + net (fo=1, routed) 0.000 10.513 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[946] + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D + ------------------------------------------------------------------- ------------------- -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946] + ------------------------------------------------------------------- + required time 10.701 + arrival time -10.513 + ------------------------------------------------------------------- + slack 0.188 + +Slack (MET) : 0.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.992ns (logic 0.732ns (5.634%) route 12.260ns (94.366%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns +>>>>>>> Stashed changes Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.010 + ------------------------------------------------------------------- + slack 0.344 +======= + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.513 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/O + net (fo=1, routed) 0.000 10.513 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[946] + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946] ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 + required time 10.701 + arrival time -10.513 ------------------------------------------------------------------- - slack 11.519 + slack 0.188 +>>>>>>> Stashed changes diff --git a/fpga/vivado_reports_nodsp/power.rpt b/fpga/vivado_reports_nodsp/power.rpt index 851e855..19c6dcd 100644 --- a/fpga/vivado_reports_nodsp/power.rpt +++ b/fpga/vivado_reports_nodsp/power.rpt @@ -1,16 +1,20 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:25 2026 +<<<<<<< Updated upstream +| Date : Fri Jul 10 04:15:05 2026 +======= +| Date : Sat Jul 11 09:21:02 2026 +>>>>>>> Stashed changes | Host : fedora running 64-bit unknown -| Command : report_power -file /home/fallensigh/vivado_reports_nodsp/power.rpt +| Command : report_power -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/power.rpt | Design : soc_top | Device : xc7a200tfbg676-1 | Design State : routed | Grade : commercial | Process : typical | Characterization : Production ------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------- Power Report @@ -30,14 +34,25 @@ Table of Contents ---------- +--------------------------+--------------+ -| Total On-Chip Power (W) | 0.549 | +<<<<<<< Updated upstream +| Total On-Chip Power (W) | 0.686 | | Design Power Budget (W) | Unspecified* | | Power Budget Margin (W) | NA | -| Dynamic (W) | 0.409 | +| Dynamic (W) | 0.545 | | Device Static (W) | 0.141 | | Effective TJA (C/W) | 1.9 | -| Max Ambient (C) | 84.0 | -| Junction Temperature (C) | 26.0 | +| Max Ambient (C) | 83.7 | +| Junction Temperature (C) | 26.3 | +======= +| Total On-Chip Power (W) | 0.779 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.637 | +| Device Static (W) | 0.142 | +| Effective TJA (C/W) | 1.9 | +| Max Ambient (C) | 83.5 | +| Junction Temperature (C) | 26.5 | +>>>>>>> Stashed changes | Confidence Level | Low | | Setting File | --- | | Simulation Activity File | --- | @@ -52,22 +67,39 @@ Table of Contents +--------------------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +--------------------------+-----------+----------+-----------+-----------------+ -| Clocks | 0.042 | 7 | --- | --- | -| Slice Logic | 0.069 | 120086 | --- | --- | -| LUT as Logic | 0.064 | 63754 | 133800 | 47.65 | -| CARRY4 | 0.002 | 2859 | 33450 | 8.55 | -| LUT as Distributed RAM | <0.001 | 740 | 46200 | 1.60 | -| Register | <0.001 | 39931 | 267600 | 14.92 | +<<<<<<< Updated upstream +| Clocks | 0.056 | 6 | --- | --- | +| Slice Logic | 0.109 | 133224 | --- | --- | +| LUT as Logic | 0.102 | 75460 | 133800 | 56.40 | +| CARRY4 | 0.003 | 3546 | 33450 | 10.60 | +| LUT as Distributed RAM | 0.002 | 628 | 46200 | 1.36 | +| Register | 0.001 | 39690 | 267600 | 14.83 | | LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 | -| F7/F8 Muxes | <0.001 | 6036 | 133800 | 4.51 | -| Others | 0.000 | 318 | --- | --- | -| Signals | 0.115 | 85084 | --- | --- | -| Block RAM | 0.019 | 23.5 | 365 | 6.44 | -| PLL | 0.132 | 1 | 10 | 10.00 | -| DSPs | 0.009 | 16 | 740 | 2.16 | -| I/O | 0.023 | 202 | 400 | 50.50 | +| F7/F8 Muxes | <0.001 | 6085 | 133800 | 4.55 | +| Others | 0.000 | 289 | --- | --- | +| Signals | 0.194 | 93202 | --- | --- | +| Block RAM | 0.019 | 25.5 | 365 | 6.99 | +| PLL | 0.137 | 1 | 10 | 10.00 | +| I/O | 0.029 | 202 | 400 | 50.50 | | Static Power | 0.141 | | | | -| Total | 0.549 | | | | +| Total | 0.686 | | | | +======= +| Clocks | 0.060 | 7 | --- | --- | +| Slice Logic | 0.137 | 103629 | --- | --- | +| LUT as Logic | 0.128 | 53158 | 133800 | 39.73 | +| CARRY4 | 0.005 | 3669 | 33450 | 10.97 | +| Register | 0.002 | 31000 | 267600 | 11.58 | +| LUT as Distributed RAM | 0.001 | 740 | 46200 | 1.60 | +| LUT as Shift Register | <0.001 | 1168 | 46200 | 2.53 | +| F7/F8 Muxes | <0.001 | 2449 | 133800 | 1.83 | +| Others | 0.000 | 333 | --- | --- | +| Signals | 0.284 | 78815 | --- | --- | +| Block RAM | 0.027 | 29.5 | 365 | 8.08 | +| PLL | 0.102 | 1 | 10 | 10.00 | +| I/O | 0.027 | 202 | 400 | 50.50 | +| Static Power | 0.142 | | | | +| Total | 0.779 | | | | +>>>>>>> Stashed changes +--------------------------+-----------+----------+-----------+-----------------+ @@ -77,16 +109,21 @@ Table of Contents +-----------+-------------+-----------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | +-----------+-------------+-----------+-------------+------------+ -| Vccint | 1.000 | 0.294 | 0.262 | 0.032 | -| Vccaux | 1.800 | 0.099 | 0.069 | 0.031 | -| Vcco33 | 3.300 | 0.011 | 0.006 | 0.005 | +<<<<<<< Updated upstream +| Vccint | 1.000 | 0.423 | 0.391 | 0.032 | +| Vccaux | 1.800 | 0.101 | 0.070 | 0.031 | +======= +| Vccint | 1.000 | 0.545 | 0.512 | 0.033 | +| Vccaux | 1.800 | 0.085 | 0.054 | 0.031 | +>>>>>>> Stashed changes +| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | | Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | | Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | | Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | | Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccbram | 1.000 | 0.003 | 0.001 | 0.001 | +| Vccbram | 1.000 | 0.003 | 0.002 | 0.001 | | MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | | MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | | Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | @@ -130,15 +167,26 @@ Table of Contents 2.2 Clock Constraints --------------------- -+-------------------+------------------------------------------+-----------------+ -| Clock | Domain | Constraint (ns) | -+-------------------+------------------------------------------+-----------------+ -| clk | clk | 20.0 | -| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 | -| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 | -| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 40.0 | -| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 | -+-------------------+------------------------------------------+-----------------+ +<<<<<<< Updated upstream ++------------------+-----------------------------------------+-----------------+ +| Clock | Domain | Constraint (ns) | ++------------------+-----------------------------------------+-----------------+ +| clk | clk | 20.0 | +| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 | +| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 | +| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 | ++------------------+-----------------------------------------+-----------------+ +======= ++------------------+------------------------------------------+-----------------+ +| Clock | Domain | Constraint (ns) | ++------------------+------------------------------------------+-----------------+ +| clk | clk | 20.0 | +| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 | +| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.0 | +| mlkem_clk | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 13.0 | +| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 | ++------------------+------------------------------------------+-----------------+ +>>>>>>> Stashed changes 3. Detailed Reports @@ -150,31 +198,64 @@ Table of Contents +----------------------------+-----------+ | Name | Power (W) | +----------------------------+-----------+ -| soc_top | 0.409 | -| pll_clk.u_clk_pll | 0.133 | -| inst | 0.133 | +<<<<<<< Updated upstream +| soc_top | 0.545 | +| pll_clk.u_clk_pll | 0.138 | +| inst | 0.138 | +| u_Axi_CDC | 0.003 | +| u_axi_uart_controller | 0.002 | +| u_cpu | 0.025 | +| addr_trans | 0.002 | +| tlb_entry | 0.002 | +| btb | 0.003 | +| dcache | 0.006 | +| icache | 0.005 | +| u_csr | 0.001 | +| u_mul | 0.004 | +| u_fft_mlkem_axi_slave | 0.251 | +| u_fft_controller | 0.030 | +| u_FFT | 0.027 | +| u_out0 | 0.001 | +| u_out1 | 0.001 | +| u_mlkem_axi_slave | 0.221 | +| u_mlkem | 0.218 | +| u_matmul_axi_slave | 0.081 | +======= +| soc_top | 0.637 | +| pll_clk.u_clk_pll | 0.103 | +| inst | 0.103 | | u_Axi_CDC | 0.002 | -| u_axi_uart_controller | 0.001 | +| u_axi_uart_controller | 0.002 | | uart0 | 0.001 | | regs | 0.001 | | u_cdma_matmul_bridge | 0.001 | -| u_cpu | 0.018 | +| u_confreg | 0.001 | +| u_cpu | 0.027 | | addr_trans | 0.002 | | tlb_entry | 0.002 | -| btb | 0.002 | +| btb | 0.003 | | dcache | 0.004 | | icache | 0.005 | -| u_csr | 0.002 | -| u_fft_mlkem_axi_slave | 0.148 | -| u_fft_controller | 0.032 | -| u_FFT | 0.029 | -| u_mlkem_axi_cdc | 0.002 | -| u_mlkem_axi_slave | 0.115 | -| u_mlkem | 0.113 | -| u_matmul_axi_slave | 0.065 | -| u_snix_axil_cdma_mux_8ch | 0.009 | +| u_csr | 0.001 | +| u_mul | 0.008 | +| u_fft_mlkem_axi_slave | 0.373 | +| u_fft_controller | 0.031 | +| u_FFT | 0.028 | +| u_out0 | 0.001 | +| u_out1 | 0.001 | +| u_mlkem_axi_cdc | 0.003 | +| wFifo | 0.001 | +| u_mlkem_axi_slave | 0.339 | +| u_mlkem | 0.332 | +| u_matmul_axi_slave | 0.077 | +>>>>>>> Stashed changes +| mult_inst[0].u_mult | 0.003 | +| mult_inst[1].u_mult | 0.002 | +| mult_inst[2].u_mult | 0.002 | +| mult_inst[3].u_mult | 0.002 | +| u_snix_axil_cdma_mux_8ch | 0.008 | | u_core_engine | 0.004 | -| axis_fifo_u0 | 0.003 | +| axis_fifo_u0 | 0.002 | +----------------------------+-----------+ diff --git a/fpga/vivado_reports_nodsp/route_status.rpt b/fpga/vivado_reports_nodsp/route_status.rpt index a98697c..44dd1ca 100644 --- a/fpga/vivado_reports_nodsp/route_status.rpt +++ b/fpga/vivado_reports_nodsp/route_status.rpt @@ -1,12 +1,21 @@ Design Route Status : # nets : ------------------------------------------- : ----------- : - # of logical nets.......................... : 128919 : - # of nets not needing routing.......... : 43824 : - # of internally routed nets........ : 43359 : +<<<<<<< Updated upstream + # of logical nets.......................... : 144034 : + # of nets not needing routing.......... : 50823 : + # of internally routed nets........ : 50442 : + # of nets with no loads............ : 381 : + # of routable nets..................... : 93211 : + # of fully routed nets............. : 93211 : +======= + # of logical nets.......................... : 114880 : + # of nets not needing routing.......... : 36054 : + # of internally routed nets........ : 35589 : # of nets with no loads............ : 465 : - # of routable nets..................... : 85095 : - # of fully routed nets............. : 85095 : + # of routable nets..................... : 78826 : + # of fully routed nets............. : 78826 : +>>>>>>> Stashed changes # of nets with routing errors.......... : 0 : ------------------------------------------- : ----------- : diff --git a/fpga/vivado_reports_nodsp/timing_hold_paths.rpt b/fpga/vivado_reports_nodsp/timing_hold_paths.rpt index fefd31f..9acc394 100644 --- a/fpga/vivado_reports_nodsp/timing_hold_paths.rpt +++ b/fpga/vivado_reports_nodsp/timing_hold_paths.rpt @@ -1,197 +1,239 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 +<<<<<<< Updated upstream +| Date : Fri Jul 10 04:14:54 2026 +======= +| Date : Sat Jul 11 09:20:56 2026 +>>>>>>> Stashed changes | Host : fedora running 64-bit unknown -| Command : report_timing -delay_type min -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/timing_hold_paths.rpt +| Command : report_timing -delay_type min -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_hold_paths.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Report -Slack (MET) : 0.032ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D +<<<<<<< Updated upstream +Slack (MET) : 0.040ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_b_reg[1][23]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.141ns (31.835%) route 0.302ns (68.165%)) Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.040ns +======= +Slack (MET) : 0.024ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns +>>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D +<<<<<<< Updated upstream + 1.174 -0.674 + SLICE_X47Y102 FDRE 0.000 -0.674 r u_matmul_axi_slave/m_in_b_reg[1][23]/C + SLICE_X47Y102 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_matmul_axi_slave/m_in_b_reg[1][23]/Q + net (fo=1, routed) 0.302 -0.231 u_matmul_axi_slave/mult_inst[1].u_mult/Q[23] + SLICE_X59Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D +======= + 1.238 -0.610 + SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.595 -0.352 - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] + 1.566 -0.381 +<<<<<<< Updated upstream + clock pessimism 0.040 -0.341 + SLICE_X59Y98 FDRE (Hold_fdre_C_D) 0.070 -0.271 u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23] ------------------------------------------------------------------- - required time 0.053 - arrival time -0.021 + required time 0.271 + arrival time -0.231 ------------------------------------------------------------------- - slack 0.032 + slack 0.040 -Slack (MET) : 0.032ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D +Slack (MET) : 0.040ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_b_reg[1][23]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.141ns (31.835%) route 0.302ns (68.165%)) Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.040ns +======= + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.287 + arrival time -0.263 + ------------------------------------------------------------------- + slack 0.024 + +Slack (MET) : 0.024ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns +>>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.191 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D +<<<<<<< Updated upstream + 1.174 -0.674 + SLICE_X47Y102 FDRE 0.000 -0.674 r u_matmul_axi_slave/m_in_b_reg[1][23]/C + SLICE_X47Y102 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_matmul_axi_slave/m_in_b_reg[1][23]/Q + net (fo=1, routed) 0.302 -0.231 u_matmul_axi_slave/mult_inst[1].u_mult/Q[23] + SLICE_X59Y98 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D +======= + 1.238 -0.610 + SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X56Y90 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.595 -0.352 - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] + 1.566 -0.381 +<<<<<<< Updated upstream + clock pessimism 0.040 -0.341 + SLICE_X59Y98 FDRE (Hold_fdre_C_D) 0.070 -0.271 u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23] ------------------------------------------------------------------- - required time 0.053 - arrival time -0.021 + required time 0.271 + arrival time -0.231 ------------------------------------------------------------------- - slack 0.032 + slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.412ns (logic 0.187ns (45.442%) route 0.225ns (54.558%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.413ns + Source Clock Delay (SCD): -0.639ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D + 1.209 -0.639 + SLICE_X82Y77 FDCE 0.000 -0.639 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C + SLICE_X82Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.498 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/Q + net (fo=3, routed) 0.225 -0.274 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg_n_0_[11] + SLICE_X85Y77 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/I2 + SLICE_X85Y77 LUT3 (Prop_lut3_I2_O) 0.046 -0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/O + net (fo=1, routed) 0.000 -0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1_n_0 + SLICE_X85Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] + 1.534 -0.413 + clock pessimism 0.037 -0.376 + SLICE_X85Y77 FDCE (Hold_fdce_C_D) 0.107 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] ------------------------------------------------------------------- - required time 0.061 - arrival time -0.019 + required time 0.269 + arrival time -0.228 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.042ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.412ns (logic 0.187ns (45.442%) route 0.225ns (54.558%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.413ns + Source Clock Delay (SCD): -0.639ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D + 1.209 -0.639 + SLICE_X82Y77 FDCE 0.000 -0.639 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C + SLICE_X82Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.498 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/Q + net (fo=3, routed) 0.225 -0.274 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg_n_0_[11] + SLICE_X85Y77 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/I2 + SLICE_X85Y77 LUT3 (Prop_lut3_I2_O) 0.046 -0.228 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/O + net (fo=1, routed) 0.000 -0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1_n_0 + SLICE_X85Y77 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] + 1.534 -0.413 + clock pessimism 0.037 -0.376 + SLICE_X85Y77 FDCE (Hold_fdce_C_D) 0.107 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] ------------------------------------------------------------------- - required time 0.061 - arrival time -0.019 + required time 0.269 + arrival time -0.228 ------------------------------------------------------------------- slack 0.042 @@ -200,38 +242,219 @@ Slack (MET) : 0.049ns (arrival time - required time) (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +======= + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.287 + arrival time -0.263 + ------------------------------------------------------------------- + slack 0.024 + +Slack (MET) : 0.024ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.287 + arrival time -0.263 + ------------------------------------------------------------------- + slack 0.024 + +Slack (MET) : 0.024ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X56Y90 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.287 + arrival time -0.263 + ------------------------------------------------------------------- + slack 0.024 + +Slack (MET) : 0.040ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_csr/csr_badv_reg[0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.218ns + Data Path Delay: 0.405ns (logic 0.186ns (45.911%) route 0.219ns (54.089%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.274ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.308 -0.541 - SLICE_X47Y34 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C - SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q - net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I + 1.175 -0.674 + SLICE_X113Y150 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C + SLICE_X113Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/Q + net (fo=3, routed) 0.219 -0.314 u_cpu/wb_stage/ms_to_ws_bus_r_reg_n_0_[0] + SLICE_X107Y149 r u_cpu/wb_stage/csr_badv[0]_i_1/I2 + SLICE_X107Y149 LUT6 (Prop_lut6_I2_O) 0.045 -0.269 r u_cpu/wb_stage/csr_badv[0]_i_1/O + net (fo=1, routed) 0.000 -0.269 u_cpu/u_csr/csr_badv_reg[31]_4[0] + SLICE_X107Y149 FDRE r u_cpu/u_csr/csr_badv_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.637 -0.310 - clock pessimism -0.218 -0.528 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA + 1.502 -0.445 + clock pessimism 0.045 -0.400 + SLICE_X107Y149 FDRE (Hold_fdre_C_D) 0.091 -0.309 u_cpu/u_csr/csr_badv_reg[0] ------------------------------------------------------------------- - required time 0.381 - arrival time -0.332 + required time 0.309 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.040 + +Slack (MET) : 0.040ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_csr/csr_badv_reg[0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.405ns (logic 0.186ns (45.911%) route 0.219ns (54.089%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.274ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.175 -0.674 + SLICE_X113Y150 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C + SLICE_X113Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/Q + net (fo=3, routed) 0.219 -0.314 u_cpu/wb_stage/ms_to_ws_bus_r_reg_n_0_[0] + SLICE_X107Y149 f u_cpu/wb_stage/csr_badv[0]_i_1/I2 + SLICE_X107Y149 LUT6 (Prop_lut6_I2_O) 0.045 -0.269 f u_cpu/wb_stage/csr_badv[0]_i_1/O + net (fo=1, routed) 0.000 -0.269 u_cpu/u_csr/csr_badv_reg[31]_4[0] + SLICE_X107Y149 FDRE f u_cpu/u_csr/csr_badv_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.502 -0.445 + clock pessimism 0.045 -0.400 + SLICE_X107Y149 FDRE (Hold_fdre_C_D) 0.091 -0.309 u_cpu/u_csr/csr_badv_reg[0] + ------------------------------------------------------------------- + required time 0.309 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.040 + +Slack (MET) : 0.049ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) +>>>>>>> Stashed changes + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) +<<<<<<< Updated upstream + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.236 -0.612 + SLICE_X97Y50 FDRE 0.000 -0.612 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C + SLICE_X97Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.471 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q + net (fo=4, routed) 0.068 -0.403 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 + SLICE_X96Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.216 -0.599 + SLICE_X96Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.452 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA + ------------------------------------------------------------------- + required time 0.452 + arrival time -0.403 ------------------------------------------------------------------- slack 0.049 @@ -243,459 +466,117 @@ Slack (MET) : 0.049ns (arrival time - required time) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%)) + Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.218ns + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.308 -0.541 - SLICE_X47Y34 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C - SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo0_reg[14]/Q - net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 - SLICE_X46Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I + 1.236 -0.612 + SLICE_X97Y50 FDRE 0.000 -0.612 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C + SLICE_X97Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.471 f u_cpu/u_csr/csr_tlbelo0_reg[14]/Q + net (fo=4, routed) 0.068 -0.403 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 + SLICE_X96Y50 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.637 -0.310 - clock pessimism -0.218 -0.528 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA + 1.564 -0.383 + clock pessimism -0.216 -0.599 + SLICE_X96Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.452 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- - required time 0.381 - arrival time -0.332 + required time 0.452 + arrival time -0.403 ------------------------------------------------------------------- slack 0.049 -Slack (MET) : 0.052ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk +Slack (MET) : 0.049ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.382ns (logic 0.141ns (36.898%) route 0.241ns (63.102%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.052 - -Slack (MET) : 0.052ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.052 - -Slack (MET) : 0.054ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.487ns + Source Clock Delay (SCD): -0.710ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.269 -0.579 - SLICE_X20Y72 RAMD32 0.000 -0.579 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D + 1.139 -0.710 + SLICE_X85Y170 FDCE 0.000 -0.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C + SLICE_X85Y170 FDCE (Prop_fdce_C_Q) 0.141 -0.569 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/Q + net (fo=14, routed) 0.241 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[9] + SLICE_X81Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.592 -0.355 - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14] + 1.460 -0.487 + clock pessimism 0.040 -0.447 + SLICE_X81Y171 FDCE (Hold_fdce_C_D) 0.070 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9] ------------------------------------------------------------------- - required time 0.067 - arrival time -0.013 + required time 0.377 + arrival time -0.328 ------------------------------------------------------------------- - slack 0.054 + slack 0.049 -Slack (MET) : 0.054ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.049ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.382ns (logic 0.141ns (36.898%) route 0.241ns (63.102%)) Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.487ns + Source Clock Delay (SCD): -0.710ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.269 -0.579 - SLICE_X20Y72 RAMD32 0.000 -0.579 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.185 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] - SLICE_X23Y73 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D + 1.139 -0.710 + SLICE_X85Y170 FDCE 0.000 -0.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C + SLICE_X85Y170 FDCE (Prop_fdce_C_Q) 0.141 -0.569 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/Q + net (fo=14, routed) 0.241 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[9] + SLICE_X81Y171 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.592 -0.355 - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14] + 1.460 -0.487 + clock pessimism 0.040 -0.447 + SLICE_X81Y171 FDCE (Hold_fdce_C_D) 0.070 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9] ------------------------------------------------------------------- - required time 0.067 - arrival time -0.013 + required time 0.377 + arrival time -0.328 ------------------------------------------------------------------- - slack 0.054 + slack 0.049 -Slack (MET) : 0.057ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.496ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.353 -0.496 - SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C - SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q - net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.037 -0.301 - SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC - ------------------------------------------------------------------- - required time 0.157 - arrival time -0.100 - ------------------------------------------------------------------- - slack 0.057 - -Slack (MET) : 0.057ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.496ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.353 -0.496 - SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C - SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 f u_cpu/axi_bridge/awaddr_reg[10]/Q - net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 - SLICE_X16Y57 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.037 -0.301 - SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC - ------------------------------------------------------------------- - required time 0.157 - arrival time -0.100 - ------------------------------------------------------------------- - slack 0.057 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.695ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.153 -0.695 - SLICE_X84Y144 FDRE 0.000 -0.695 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q - net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0 - SLICE_X84Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/I0 - SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O - net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0 - SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.472 -0.475 - clock pessimism 0.045 -0.430 - SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6] - ------------------------------------------------------------------- - required time 0.309 - arrival time -0.251 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.695ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.153 -0.695 - SLICE_X84Y144 FDRE 0.000 -0.695 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q - net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0 - SLICE_X84Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/I0 - SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O - net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0 - SLICE_X84Y151 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.472 -0.475 - clock pessimism 0.045 -0.430 - SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6] - ------------------------------------------------------------------- - required time 0.309 - arrival time -0.251 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[0]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[0]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.155 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[0]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[0]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.155 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.061ns (arrival time - required time) +Slack (MET) : 0.051ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I @@ -703,39 +584,39 @@ Slack (MET) : 0.061ns (arrival time - required time) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) + Data Path Delay: 0.211ns (logic 0.141ns (66.741%) route 0.070ns (33.259%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.273ns - Source Clock Delay (SCD): -0.507ns - Clock Pessimism Removal (CPR): 0.221ns + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.342 -0.507 - SLICE_X37Y38 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C - SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q - net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 - SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + 1.233 -0.615 + SLICE_X67Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C + SLICE_X67Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q + net (fo=4, routed) 0.070 -0.404 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 + SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.674 -0.273 - clock pessimism -0.221 -0.494 - SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA + 1.561 -0.386 + clock pessimism -0.216 -0.602 + SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.455 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA ------------------------------------------------------------------- - required time 0.347 - arrival time -0.285 + required time 0.455 + arrival time -0.404 ------------------------------------------------------------------- - slack 0.061 + slack 0.051 -Slack (MET) : 0.061ns (arrival time - required time) +Slack (MET) : 0.051ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I @@ -743,1617 +624,177 @@ Slack (MET) : 0.061ns (arrival time - required time) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) + Data Path Delay: 0.211ns (logic 0.141ns (66.741%) route 0.070ns (33.259%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.273ns - Source Clock Delay (SCD): -0.507ns - Clock Pessimism Removal (CPR): 0.221ns + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.342 -0.507 - SLICE_X37Y38 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C - SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 f u_cpu/u_csr/csr_tlbelo1_reg[20]/Q - net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 - SLICE_X36Y38 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + 1.233 -0.615 + SLICE_X67Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C + SLICE_X67Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_cpu/u_csr/csr_tlbelo1_reg[20]/Q + net (fo=4, routed) 0.070 -0.404 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 + SLICE_X66Y50 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.674 -0.273 - clock pessimism -0.221 -0.494 - SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA + 1.561 -0.386 + clock pessimism -0.216 -0.602 + SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.455 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA ------------------------------------------------------------------- - required time 0.347 - arrival time -0.285 + required time 0.455 + arrival time -0.404 + ------------------------------------------------------------------- + slack 0.051 + +Slack (MET) : 0.056ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.508ns (logic 0.213ns (41.922%) route 0.295ns (58.078%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X112Y55 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C + SLICE_X112Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/Q + net (fo=5, routed) 0.295 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[8] + SLICE_X114Y49 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/I2 + SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.049 -0.094 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/O + net (fo=1, routed) 0.000 -0.094 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[8] + SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.653 -0.294 + clock pessimism 0.037 -0.257 + SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8] + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.056 + +Slack (MET) : 0.056ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.508ns (logic 0.213ns (41.922%) route 0.295ns (58.078%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X112Y55 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C + SLICE_X112Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.438 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/Q + net (fo=5, routed) 0.295 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[8] + SLICE_X114Y49 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/I2 + SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.049 -0.094 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/O + net (fo=1, routed) 0.000 -0.094 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[8] + SLICE_X114Y49 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.653 -0.294 + clock pessimism 0.037 -0.257 + SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8] + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.056 + +Slack (MET) : 0.061ns (arrival time - required time) + Source: u_confreg/confreg_int_set_reg[11]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[11]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.376ns (logic 0.246ns (65.365%) route 0.130ns (34.635%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.335ns + Source Clock Delay (SCD): -0.494ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.355 -0.494 + SLICE_X8Y49 FDRE 0.000 -0.494 r u_confreg/confreg_int_set_reg[11]/C + SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.148 -0.346 r u_confreg/confreg_int_set_reg[11]/Q + net (fo=2, routed) 0.130 -0.215 u_confreg/u_int_ctrl/edge_int_state_reg[31]_0[11] + SLICE_X8Y51 r u_confreg/u_int_ctrl/edge_int_state[11]_i_1/I2 + SLICE_X8Y51 LUT4 (Prop_lut4_I2_O) 0.098 -0.117 r u_confreg/u_int_ctrl/edge_int_state[11]_i_1/O + net (fo=1, routed) 0.000 -0.117 u_confreg/u_int_ctrl/edge_int_state[11]_i_1_n_0 + SLICE_X8Y51 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.612 -0.335 + clock pessimism 0.037 -0.298 + SLICE_X8Y51 FDCE (Hold_fdce_C_D) 0.120 -0.178 u_confreg/u_int_ctrl/edge_int_state_reg[11] + ------------------------------------------------------------------- + required time 0.178 + arrival time -0.117 ------------------------------------------------------------------- slack 0.061 -Slack (MET) : 0.066ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D +Slack (MET) : 0.061ns (arrival time - required time) + Source: u_confreg/confreg_int_set_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.554 -0.393 - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.020 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.066ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.554 -0.393 - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.020 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.077ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.277ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X86Y154 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q - net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] - SLICE_X86Y148 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/I0 - SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O - net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0 - SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.478 -0.469 - clock pessimism 0.045 -0.424 - SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.255 - ------------------------------------------------------------------- - slack 0.077 - -Slack (MET) : 0.077ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.277ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X86Y154 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q - net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] - SLICE_X86Y148 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/I0 - SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O - net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0 - SLICE_X86Y148 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.478 -0.469 - clock pessimism 0.045 -0.424 - SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.255 - ------------------------------------------------------------------- - slack 0.077 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.260ns - Source Clock Delay (SCD): -0.566ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.282 -0.566 - SLICE_X18Y50 SRLC32E 0.000 -0.566 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.188 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31 - net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56 - SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.687 -0.260 - clock pessimism 0.037 -0.223 - SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32 - ------------------------------------------------------------------- - required time 0.101 - arrival time -0.023 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.260ns - Source Clock Delay (SCD): -0.566ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.282 -0.566 - SLICE_X18Y50 SRLC32E 0.000 -0.566 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.188 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31 - net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56 - SLICE_X14Y49 SRLC32E f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.687 -0.260 - clock pessimism 0.037 -0.223 - SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32 - ------------------------------------------------------------------- - required time 0.101 - arrival time -0.023 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q - net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.378 - arrival time -0.299 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q - net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0 - SLICE_X6Y56 RAMD32 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.378 - arrival time -0.299 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.410 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.410 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.080ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q - net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.377 - arrival time -0.298 - ------------------------------------------------------------------- - slack 0.080 - -Slack (MET) : 0.080ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q - net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0 - SLICE_X6Y56 RAMD32 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.377 - arrival time -0.298 - ------------------------------------------------------------------- - slack 0.080 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q - net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49] - ------------------------------------------------------------------- - required time 0.228 - arrival time -0.145 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q - net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49] - SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49] - ------------------------------------------------------------------- - required time 0.228 - arrival time -0.145 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[11]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%)) - Logic Levels: 0 - Clock Path Skew: 0.056ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X62Y75 FDCE 0.000 -0.626 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q - net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5] - RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.357 - clock pessimism -0.213 -0.570 - RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10]) - 0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.302 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%)) - Logic Levels: 0 - Clock Path Skew: 0.056ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X62Y75 FDCE 0.000 -0.626 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q - net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5] - RAMB18_X3Y30 RAMB18E1 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.357 - clock pessimism -0.213 -0.570 - RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10]) - 0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.302 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] - SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.002 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.195 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] - SLICE_X14Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.002 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[1]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[1]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.182 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[1]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[1]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 - SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.182 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.087ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.089 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] - SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.029 - ------------------------------------------------------------------- - slack 0.087 - -Slack (MET) : 0.087ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.089 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] - SLICE_X23Y77 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.029 - ------------------------------------------------------------------- - slack 0.087 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.095ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.464ns - Source Clock Delay (SCD): -0.683ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.165 -0.683 - SLICE_X73Y148 FDCE 0.000 -0.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q - net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16] - SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.483 -0.464 - clock pessimism 0.045 -0.419 - SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16] - ------------------------------------------------------------------- - required time 0.362 - arrival time -0.267 - ------------------------------------------------------------------- - slack 0.095 - -Slack (MET) : 0.095ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.464ns - Source Clock Delay (SCD): -0.683ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.165 -0.683 - SLICE_X73Y148 FDCE 0.000 -0.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q - net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16] - SLICE_X73Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.483 -0.464 - clock pessimism 0.045 -0.419 - SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16] - ------------------------------------------------------------------- - required time 0.362 - arrival time -0.267 - ------------------------------------------------------------------- - slack 0.095 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.568ns + Data Path Delay: 0.376ns (logic 0.246ns (65.365%) route 0.130ns (34.635%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.335ns + Source Clock Delay (SCD): -0.494ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -2361,5505 +802,113 @@ Slack (MET) : 0.096ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.280 -0.568 - SLICE_X20Y50 SRLC32E 0.000 -0.568 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.190 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31 - net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55 - SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D + 1.355 -0.494 + SLICE_X8Y49 FDRE 0.000 -0.494 r u_confreg/confreg_int_set_reg[11]/C + SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.148 -0.346 f u_confreg/confreg_int_set_reg[11]/Q + net (fo=2, routed) 0.130 -0.215 u_confreg/u_int_ctrl/edge_int_state_reg[31]_0[11] + SLICE_X8Y51 f u_confreg/u_int_ctrl/edge_int_state[11]_i_1/I2 + SLICE_X8Y51 LUT4 (Prop_lut4_I2_O) 0.098 -0.117 f u_confreg/u_int_ctrl/edge_int_state[11]_i_1/O + net (fo=1, routed) 0.000 -0.117 u_confreg/u_int_ctrl/edge_int_state[11]_i_1_n_0 + SLICE_X8Y51 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.685 -0.262 - clock pessimism 0.037 -0.225 - SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32 - ------------------------------------------------------------------- - required time 0.103 - arrival time -0.008 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X20Y50 SRLC32E 0.000 -0.568 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.190 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31 - net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55 - SLICE_X20Y49 SRLC32E f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.685 -0.262 - clock pessimism 0.037 -0.225 - SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32 - ------------------------------------------------------------------- - required time 0.103 - arrival time -0.008 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[14]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[14]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB - ------------------------------------------------------------------- - required time 0.306 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[14]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[14]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0 - SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB - ------------------------------------------------------------------- - required time 0.306 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q - net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.280 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo1_reg[26]/Q - net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0 - SLICE_X46Y36 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.280 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q - net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51] - ------------------------------------------------------------------- - required time 0.229 - arrival time -0.128 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q - net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51] - SLICE_X15Y89 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51] - ------------------------------------------------------------------- - required time 0.229 - arrival time -0.128 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%)) - Logic Levels: 0 - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q - net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59] - ------------------------------------------------------------------- - required time 0.226 - arrival time -0.125 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%)) - Logic Levels: 0 - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q - net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59] - SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59] - ------------------------------------------------------------------- - required time 0.226 - arrival time -0.125 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X21Y48 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[3]/C - SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[3]/Q - net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1 + 1.612 -0.335 + clock pessimism 0.037 -0.298 + SLICE_X8Y51 FDCE (Hold_fdce_C_D) 0.120 -0.178 u_confreg/u_int_ctrl/edge_int_state_reg[11] ------------------------------------------------------------------- required time 0.178 - arrival time -0.075 + arrival time -0.117 ------------------------------------------------------------------- - slack 0.103 + slack 0.061 -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.526ns (logic 0.210ns (39.912%) route 0.316ns (60.088%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.352 -0.497 - SLICE_X21Y48 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[3]/C - SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[3]/Q - net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1 - SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.178 - arrival time -0.075 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D + 1.246 -0.602 + SLICE_X112Y53 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C + SLICE_X112Y53 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/Q + net (fo=5, routed) 0.316 -0.122 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[10] + SLICE_X114Y49 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/I2 + SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.046 -0.076 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/O + net (fo=1, routed) 0.000 -0.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[10] + SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] + 1.653 -0.294 + clock pessimism 0.037 -0.257 + SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10] ------------------------------------------------------------------- - required time -0.016 - arrival time 0.119 + required time 0.150 + arrival time -0.076 ------------------------------------------------------------------- - slack 0.103 + slack 0.074 -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.119 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.105ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.526ns (logic 0.210ns (39.912%) route 0.316ns (60.088%)) Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X83Y155 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q - net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5] - SLICE_X84Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/I0 - SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0 - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.471 -0.476 - clock pessimism 0.040 -0.436 - SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5] - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.200 - ------------------------------------------------------------------- - slack 0.105 - -Slack (MET) : 0.105ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X83Y155 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q - net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5] - SLICE_X84Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/I0 - SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0 - SLICE_X84Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.471 -0.476 - clock pessimism 0.040 -0.436 - SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5] - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.200 - ------------------------------------------------------------------- - slack 0.105 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[1]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[1]/Q - net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[1]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[1]/Q - net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1 - SLICE_X6Y45 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q - net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D + 1.246 -0.602 + SLICE_X112Y53 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C + SLICE_X112Y53 FDRE (Prop_fdre_C_Q) 0.164 -0.438 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/Q + net (fo=5, routed) 0.316 -0.122 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[10] + SLICE_X114Y49 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/I2 + SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.046 -0.076 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/O + net (fo=1, routed) 0.000 -0.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[10] + SLICE_X114Y49 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57] + 1.653 -0.294 + clock pessimism 0.037 -0.257 + SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10] ------------------------------------------------------------------- - required time 0.233 - arrival time -0.127 + required time 0.150 + arrival time -0.076 ------------------------------------------------------------------- - slack 0.106 + slack 0.074 -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q - net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57] - SLICE_X15Y89 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57] - ------------------------------------------------------------------- - required time 0.233 - arrival time -0.127 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.280ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.458ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.156 -0.693 - SLICE_X89Y154 FDCE 0.000 -0.693 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q - net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] - SLICE_X90Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/I3 - SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O - net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0 - SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.489 -0.458 - clock pessimism 0.045 -0.413 - SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8] - ------------------------------------------------------------------- - required time 0.292 - arrival time -0.185 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.280ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.458ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.156 -0.693 - SLICE_X89Y154 FDCE 0.000 -0.693 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q - net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] - SLICE_X90Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/I3 - SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O - net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0 - SLICE_X90Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.489 -0.458 - clock pessimism 0.045 -0.413 - SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8] - ------------------------------------------------------------------- - required time 0.292 - arrival time -0.185 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X64Y76 RAMD32 0.000 -0.626 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.081 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X64Y76 RAMD32 0.000 -0.626 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.081 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.268 -0.580 - SLICE_X22Y71 RAMD32 0.000 -0.580 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.056 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.268 -0.580 - SLICE_X22Y71 RAMD32 0.000 -0.580 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] - SLICE_X25Y70 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.056 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q - net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48] - ------------------------------------------------------------------- - required time 0.232 - arrival time -0.124 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q - net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48] - SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48] - ------------------------------------------------------------------- - required time 0.232 - arrival time -0.124 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) +Slack (MET) : 0.076ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 @@ -7867,11 +916,11 @@ Slack (MET) : 0.117ns (arrival time - required time) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) + Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.313ns + Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7879,27 +928,27 @@ Slack (MET) : 0.117ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + 1.302 -0.546 + SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + 1.634 -0.313 + clock pessimism -0.192 -0.505 + SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 + required time 0.196 + arrival time -0.120 ------------------------------------------------------------------- - slack 0.117 + slack 0.076 -Slack (MET) : 0.117ns (arrival time - required time) +Slack (MET) : 0.076ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 @@ -7907,11 +956,11 @@ Slack (MET) : 0.117ns (arrival time - required time) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) + Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.313ns + Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7919,27 +968,27 @@ Slack (MET) : 0.117ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + 1.302 -0.546 + SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X2Y66 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + 1.634 -0.313 + clock pessimism -0.192 -0.505 + SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 + required time 0.196 + arrival time -0.120 ------------------------------------------------------------------- - slack 0.117 + slack 0.076 -Slack (MET) : 0.117ns (arrival time - required time) +Slack (MET) : 0.076ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 @@ -7947,11 +996,11 @@ Slack (MET) : 0.117ns (arrival time - required time) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) + Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.313ns + Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7959,27 +1008,27 @@ Slack (MET) : 0.117ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + 1.302 -0.546 + SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + 1.634 -0.313 + clock pessimism -0.192 -0.505 + SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 + required time 0.196 + arrival time -0.120 ------------------------------------------------------------------- - slack 0.117 + slack 0.076 -Slack (MET) : 0.117ns (arrival time - required time) +Slack (MET) : 0.076ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 @@ -7987,11 +1036,11 @@ Slack (MET) : 0.117ns (arrival time - required time) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) + Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.313ns + Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7999,3681 +1048,117 @@ Slack (MET) : 0.117ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + 1.302 -0.546 + SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X2Y66 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + 1.634 -0.313 + clock pessimism -0.192 -0.505 + SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 + required time 0.196 + arrival time -0.120 ------------------------------------------------------------------- - slack 0.117 + slack 0.076 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.118ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[15]/C +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[15]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[15]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1 - ------------------------------------------------------------------- - required time 0.328 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.118 - -Slack (MET) : 0.118ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[15]/C + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) + Data Path Delay: 0.349ns (logic 0.164ns (46.999%) route 0.185ns (53.001%)) Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[15]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[15]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1 - SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1 - ------------------------------------------------------------------- - required time 0.328 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.118 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.369 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.369 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 0.025 - arrival time 0.096 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 0.025 - arrival time 0.096 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.496 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.496 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.272 -0.576 - SLICE_X15Y70 FDCE 0.000 -0.576 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.272 -0.576 - SLICE_X15Y70 FDCE 0.000 -0.576 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y70 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X17Y59 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns + Source Clock Delay (SCD): -0.506ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + 1.343 -0.506 + SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C + SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q + net (fo=33, routed) 0.185 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] + SLICE_X39Y52 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] + clock pessimism 0.037 -0.310 + SLICE_X39Y52 FDRE (Hold_fdre_C_D) 0.070 -0.240 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2] ------------------------------------------------------------------- - required time 0.499 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.499 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.476 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.476 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[10]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[10]/Q - net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[10]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[10]/Q - net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0 - SLICE_X44Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0 - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.232 -0.541 - SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.466 - arrival time -0.344 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0 - SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.232 -0.541 - SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.466 - arrival time -0.344 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X17Y59 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.539ns - Clock Pessimism Removal (CPR): 0.231ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.539 - SLICE_X1Y61 FDSE 0.000 -0.539 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0 - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.231 -0.539 - SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0] - ------------------------------------------------------------------- - required time 0.464 - arrival time -0.342 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.539ns - Clock Pessimism Removal (CPR): 0.231ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.539 - SLICE_X1Y61 FDSE 0.000 -0.539 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 f u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0 - SLICE_X1Y61 FDSE f u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.231 -0.539 - SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0] - ------------------------------------------------------------------- - required time 0.464 - arrival time -0.342 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.603ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.245 -0.603 - SLICE_X117Y61 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q - net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0] - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.573 -0.374 - clock pessimism -0.229 -0.603 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] - ------------------------------------------------------------------- - required time 0.528 - arrival time -0.406 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.603ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.245 -0.603 - SLICE_X117Y61 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q - net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0] - SLICE_X117Y61 FDCE f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.573 -0.374 - clock pessimism -0.229 -0.603 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] - ------------------------------------------------------------------- - required time 0.528 - arrival time -0.406 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.261 -0.587 - SLICE_X29Y74 FDCE 0.000 -0.587 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.227 -0.587 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.512 - arrival time -0.390 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.261 -0.587 - SLICE_X29Y74 FDCE 0.000 -0.587 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X29Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.227 -0.587 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.512 - arrival time -0.390 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0 - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.229 -0.570 - SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.229 -0.570 - SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.477 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.477 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.553ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.295 -0.553 - SLICE_X5Y75 FDCE 0.000 -0.553 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.623 -0.324 - clock pessimism -0.229 -0.553 - SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.478 - arrival time -0.356 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.553ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.295 -0.553 - SLICE_X5Y75 FDCE 0.000 -0.553 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.623 -0.324 - clock pessimism -0.229 -0.553 - SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.478 - arrival time -0.356 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.123ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y34 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[12]/C - SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[12]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.218 -0.527 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.123 - -Slack (MET) : 0.123ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y34 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[12]/C - SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[12]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0 - SLICE_X44Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.218 -0.527 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.123 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y36 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[16]/C - SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[16]/Q - net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y36 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[16]/C - SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo0_reg[16]/Q - net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0 - SLICE_X46Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[22]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%)) - Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X5Y47 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[22]/C - SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[22]/Q - net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0 - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.196 -0.425 - SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC - ------------------------------------------------------------------- - required time 0.281 + required time 0.240 arrival time -0.157 ------------------------------------------------------------------- - slack 0.124 + slack 0.084 -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[22]/C +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%)) + Data Path Delay: 0.349ns (logic 0.164ns (46.999%) route 0.185ns (53.001%)) Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.196ns + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.506ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.382 -0.467 - SLICE_X5Y47 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[22]/C - SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[22]/Q - net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0 - SLICE_X2Y48 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I + 1.343 -0.506 + SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C + SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 f u_cpu/u_csr/csr_tlbidx_reg[26]/Q + net (fo=33, routed) 0.185 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] + SLICE_X39Y52 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.718 -0.229 - clock pessimism -0.196 -0.425 - SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC + 1.600 -0.347 + clock pessimism 0.037 -0.310 + SLICE_X39Y52 FDRE (Hold_fdre_C_D) 0.070 -0.240 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2] ------------------------------------------------------------------- - required time 0.281 + required time 0.240 arrival time -0.157 ------------------------------------------------------------------- - slack 0.124 + slack 0.084 -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) + Data Path Delay: 0.339ns (logic 0.128ns (37.707%) route 0.211ns (62.293%)) Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.504 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.504 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.481 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.481 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.394 - arrival time -0.266 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.394 - arrival time -0.266 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.510ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.339 -0.510 - SLICE_X41Y37 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[15]/C - SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[15]/Q - net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1 - SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1 - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.510ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.339 -0.510 - SLICE_X41Y37 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[15]/C - SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 f u_cpu/u_csr/csr_tlbelo1_reg[15]/Q - net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1 - SLICE_X40Y38 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1 - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q - net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 - ------------------------------------------------------------------- - required time 0.406 - arrival time -0.278 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo1_reg[27]/Q - net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 - SLICE_X46Y36 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 - ------------------------------------------------------------------- - required time 0.406 - arrival time -0.278 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0 - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.602 -0.345 - clock pessimism -0.230 -0.575 - SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.369 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0 - SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.602 -0.345 - clock pessimism -0.230 -0.575 - SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.369 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.390 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.390 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.542ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.542 - SLICE_X43Y32 FDRE 0.000 -0.542 r u_cpu/u_csr/csr_tlbelo0_reg[20]/C - SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 r u_cpu/u_csr/csr_tlbelo0_reg[20]/Q - net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0 - SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.542ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.542 - SLICE_X43Y32 FDRE 0.000 -0.542 r u_cpu/u_csr/csr_tlbelo0_reg[20]/C - SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 f u_cpu/u_csr/csr_tlbelo0_reg[20]/Q - net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0 - SLICE_X42Y33 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[0]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[0]/Q - net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.172 - ------------------------------------------------------------------- - slack 0.133 - -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[0]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[0]/Q - net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0 - SLICE_X6Y45 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.172 - ------------------------------------------------------------------- - slack 0.133 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q - net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[2]/Q - net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D - SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -11681,39 +1166,39 @@ Slack (MET) : 0.135ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.349 -0.500 - SLICE_X28Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[2]/C - SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[2]/Q - net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I + 1.313 -0.536 + SLICE_X47Y47 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[5]/C + SLICE_X47Y47 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[5]/Q + net (fo=1, routed) 0.211 -0.196 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIC1 + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y51 RAMD32 (Hold_ramd32_CLK_I) + 0.061 -0.280 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1 ------------------------------------------------------------------- - required time 0.165 - arrival time -0.031 + required time 0.280 + arrival time -0.196 ------------------------------------------------------------------- - slack 0.135 + slack 0.084 -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[2]/C +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%)) + Data Path Delay: 0.339ns (logic 0.128ns (37.707%) route 0.211ns (62.293%)) Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -11721,597 +1206,39 @@ Slack (MET) : 0.135ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.349 -0.500 - SLICE_X28Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[2]/C - SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 f u_cpu/axi_bridge/araddr_reg[2]/Q - net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0 - SLICE_X36Y59 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I + 1.313 -0.536 + SLICE_X47Y47 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[5]/C + SLICE_X47Y47 FDRE (Prop_fdre_C_Q) 0.128 -0.408 f u_cpu/axi_bridge/araddr_reg[5]/Q + net (fo=1, routed) 0.211 -0.196 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIC1 + SLICE_X44Y51 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y51 RAMD32 (Hold_ramd32_CLK_I) + 0.061 -0.280 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1 ------------------------------------------------------------------- - required time 0.165 - arrival time -0.031 + required time 0.280 + arrival time -0.196 ------------------------------------------------------------------- - slack 0.135 + slack 0.084 -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/axi_bridge/wstrb_reg[2]/C + (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[12]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[12]/Q - net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.170 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[12]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[12]/Q - net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0 - SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.170 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[12]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[12]/Q - net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.385 - arrival time -0.249 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[12]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_cpu/u_csr/csr_tlbelo1_reg[12]/Q - net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 - SLICE_X46Y32 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.385 - arrival time -0.249 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.349 -0.500 - SLICE_X29Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[0]/C - SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[0]/Q - net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.164 - arrival time -0.028 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.349 -0.500 - SLICE_X29Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[0]/C - SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 f u_cpu/axi_bridge/araddr_reg[0]/Q - net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X36Y59 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.164 - arrival time -0.028 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[11]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[11]/Q - net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.405 - arrival time -0.268 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[11]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_cpu/u_csr/csr_tlbelo1_reg[11]/Q - net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1 - SLICE_X46Y32 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.405 - arrival time -0.268 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[28]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y48 FDRE 0.000 -0.465 r u_cpu/axi_bridge/wdata_reg[28]/C - SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 r u_cpu/axi_bridge/wdata_reg[28]/Q - net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I) - 0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC - ------------------------------------------------------------------- - required time 0.359 - arrival time -0.221 - ------------------------------------------------------------------- - slack 0.138 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[28]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y48 FDRE 0.000 -0.465 r u_cpu/axi_bridge/wdata_reg[28]/C - SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 f u_cpu/axi_bridge/wdata_reg[28]/Q - net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I) - 0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC - ------------------------------------------------------------------- - required time 0.359 - arrival time -0.221 - ------------------------------------------------------------------- - slack 0.138 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y43 FDRE 0.000 -0.468 r u_cpu/icache/lfsr/r_lfsr_reg[6]/C - SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/icache/lfsr/r_lfsr_reg[6]/Q - net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0] - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.236 -0.468 - SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7] - ------------------------------------------------------------------- - required time 0.397 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y43 FDRE 0.000 -0.468 r u_cpu/icache/lfsr/r_lfsr_reg[6]/C - SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/icache/lfsr/r_lfsr_reg[6]/Q - net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0] - SLICE_X5Y43 FDRE f u_cpu/icache/lfsr/r_lfsr_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.236 -0.468 - SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7] - ------------------------------------------------------------------- - required time 0.397 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[11]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[11]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1 - SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism -0.217 -0.524 - SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.400 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[11]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[11]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1 - SLICE_X44Y37 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism -0.217 -0.524 - SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.400 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%)) + Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.268ns - Source Clock Delay (SCD): -0.502ns + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.496ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -12319,38 +1246,39 @@ Slack (MET) : 0.140ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.347 -0.502 - SLICE_X31Y41 FDRE 0.000 -0.502 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q - net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16] - SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/D + 1.353 -0.496 + SLICE_X15Y41 FDSE 0.000 -0.496 r u_cpu/axi_bridge/wstrb_reg[2]/C + SLICE_X15Y41 FDSE (Prop_fdse_C_Q) 0.128 -0.368 r u_cpu/axi_bridge/wstrb_reg[2]/Q + net (fo=1, routed) 0.059 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0 + SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.679 -0.268 - clock pessimism -0.221 -0.489 - SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16] + 1.685 -0.262 + clock pessimism -0.221 -0.483 + SLICE_X14Y41 RAMD32 (Hold_ramd32_CLK_I) + 0.090 -0.393 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- - required time 0.442 - arrival time -0.301 + required time 0.393 + arrival time -0.309 ------------------------------------------------------------------- - slack 0.140 + slack 0.084 -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/axi_bridge/wstrb_reg[2]/C + (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%)) + Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.268ns - Source Clock Delay (SCD): -0.502ns + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.496ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -12358,39 +1286,40 @@ Slack (MET) : 0.140ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.347 -0.502 - SLICE_X31Y41 FDRE 0.000 -0.502 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q - net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16] - SLICE_X30Y41 FDRE f u_cpu/u_csr/lladdr_reg[16]/D + 1.353 -0.496 + SLICE_X15Y41 FDSE 0.000 -0.496 r u_cpu/axi_bridge/wstrb_reg[2]/C + SLICE_X15Y41 FDSE (Prop_fdse_C_Q) 0.128 -0.368 f u_cpu/axi_bridge/wstrb_reg[2]/Q + net (fo=1, routed) 0.059 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0 + SLICE_X14Y41 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.679 -0.268 - clock pessimism -0.221 -0.489 - SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16] + 1.685 -0.262 + clock pessimism -0.221 -0.483 + SLICE_X14Y41 RAMD32 (Hold_ramd32_CLK_I) + 0.090 -0.393 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- - required time 0.442 - arrival time -0.301 + required time 0.393 + arrival time -0.309 ------------------------------------------------------------------- - slack 0.140 + slack 0.084 -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[9]/D + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%)) + Data Path Delay: 0.347ns (logic 0.141ns (40.688%) route 0.206ns (59.312%)) Logic Levels: 0 - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.269ns + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.504ns - Clock Pessimism Removal (CPR): 0.196ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -12398,38 +1327,38 @@ Slack (MET) : 0.143ns (arrival time - required time) clock source latency -1.848 -1.848 propagated clock network latency 1.345 -0.504 - SLICE_X32Y40 FDRE 0.000 -0.504 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q - net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9] - SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/D + SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[27]/C + SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[27]/Q + net (fo=33, routed) 0.206 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[8] + SLICE_X37Y50 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.678 -0.269 - clock pessimism -0.196 -0.465 - SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9] + 1.601 -0.346 + clock pessimism 0.037 -0.309 + SLICE_X37Y50 FDRE (Hold_fdre_C_D) 0.066 -0.243 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3] ------------------------------------------------------------------- - required time 0.387 - arrival time -0.244 + required time 0.243 + arrival time -0.157 ------------------------------------------------------------------- - slack 0.143 + slack 0.086 -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[9]/D + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%)) + Data Path Delay: 0.347ns (logic 0.141ns (40.688%) route 0.206ns (59.312%)) Logic Levels: 0 - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.269ns + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.504ns - Clock Pessimism Removal (CPR): 0.196ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -12437,649 +1366,37 @@ Slack (MET) : 0.143ns (arrival time - required time) clock source latency -1.848 -1.848 propagated clock network latency 1.345 -0.504 - SLICE_X32Y40 FDRE 0.000 -0.504 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q - net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9] - SLICE_X31Y39 FDRE f u_cpu/u_csr/lladdr_reg[9]/D + SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[27]/C + SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/u_csr/csr_tlbidx_reg[27]/Q + net (fo=33, routed) 0.206 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[8] + SLICE_X37Y50 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.678 -0.269 - clock pessimism -0.196 -0.465 - SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9] + 1.601 -0.346 + clock pessimism 0.037 -0.309 + SLICE_X37Y50 FDRE (Hold_fdre_C_D) 0.066 -0.243 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3] ------------------------------------------------------------------- - required time 0.387 - arrival time -0.244 + required time 0.243 + arrival time -0.157 ------------------------------------------------------------------- - slack 0.143 + slack 0.086 -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%)) - Logic Levels: 0 - Clock Path Skew: 0.035ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.282ns - Source Clock Delay (SCD): -0.513ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.336 -0.513 - SLICE_X27Y26 FDRE 0.000 -0.513 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q - net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46] - SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.665 -0.282 - clock pessimism -0.196 -0.478 - SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82] - ------------------------------------------------------------------- - required time 0.407 - arrival time -0.259 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%)) - Logic Levels: 0 - Clock Path Skew: 0.035ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.282ns - Source Clock Delay (SCD): -0.513ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.336 -0.513 - SLICE_X27Y26 FDRE 0.000 -0.513 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 f u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q - net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46] - SLICE_X28Y26 FDRE f u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.665 -0.282 - clock pessimism -0.196 -0.478 - SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82] - ------------------------------------------------------------------- - required time 0.407 - arrival time -0.259 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1 - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1 - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.524ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.468ns (logic 0.227ns (48.556%) route 0.241ns (51.444%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns + Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.339ns + Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -13087,704 +1404,11 @@ Slack (MET) : 0.524ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.187 -0.103 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X17Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.605 -0.342 - clock pessimism -0.192 -0.534 - SLICE_X17Y86 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3] - ------------------------------------------------------------------- - required time 0.626 - arrival time -0.103 - ------------------------------------------------------------------- - slack 0.524 - -Slack (MET) : 0.548ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.227ns (48.316%) route 0.243ns (51.684%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.189 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X15Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.605 -0.342 - clock pessimism -0.214 -0.556 - SLICE_X15Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.648 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.648 - arrival time -0.101 - ------------------------------------------------------------------- - slack 0.548 - -Slack (MET) : 0.558ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X14Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.620 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.620 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.558 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.650ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.622ns (logic 0.227ns (36.501%) route 0.395ns (63.499%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.341 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X16Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR + 1.279 -0.569 + SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -13792,3044 +1416,22317 @@ Slack (MET) : 0.650ns (arrival time - required time) propagated clock network latency 1.608 -0.339 clock pessimism -0.192 -0.531 - SLICE_X16Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3] + SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- - required time 0.598 - arrival time 0.052 + required time 0.221 + arrival time -0.135 ------------------------------------------------------------------- - slack 0.650 + slack 0.087 -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.339ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + 1.279 -0.569 + SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X16Y61 RAMD32 f axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] + 1.608 -0.339 + clock pessimism -0.192 -0.531 + SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 + required time 0.221 + arrival time -0.135 ------------------------------------------------------------------- - slack 0.651 + slack 0.087 -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.339ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + 1.279 -0.569 + SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] + 1.608 -0.339 + clock pessimism -0.192 -0.531 + SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 + required time 0.221 + arrival time -0.135 ------------------------------------------------------------------- - slack 0.651 + slack 0.087 -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.339ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + 1.279 -0.569 + SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X16Y61 RAMD32 f axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] + 1.608 -0.339 + clock pessimism -0.192 -0.531 + SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 + required time 0.221 + arrival time -0.135 ------------------------------------------------------------------- - slack 0.651 + slack 0.087 -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMS32 f u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMS32 f u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.703 + slack 0.087 -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.703 + slack 0.087 -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1 ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.703 + slack 0.087 -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1 ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.800 + slack 0.087 -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.800 + slack 0.087 -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1 ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.800 + slack 0.087 -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1 ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.800 + slack 0.087 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.805 + slack 0.087 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.805 + slack 0.087 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1 ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.805 + slack 0.087 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1 ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.805 + slack 0.087 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.805 + slack 0.087 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.805 + slack 0.087 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1 ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.805 + slack 0.087 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1 ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.805 + slack 0.087 -Slack (MET) : 0.824ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X121Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.824 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0] - ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg - ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.881ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X120Y70 FDCE (Remov_fdce_C_CLR) -0.067 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1] - ------------------------------------------------------------------- - required time 0.642 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.881 - -Slack (MET) : 0.881ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X120Y70 FDCE (Remov_fdce_C_CLR) -0.067 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2] - ------------------------------------------------------------------- - required time 0.642 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.881 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_confreg/int_out_or_q1_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/int_out_or_q2_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.480ns (logic 0.141ns (29.360%) route 0.339ns (70.640%)) + Logic Levels: 0 + Clock Path Skew: 0.316ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.260ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.309 -0.539 + SLICE_X4Y50 FDRE 0.000 -0.539 r u_confreg/int_out_or_q1_reg/C + SLICE_X4Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/int_out_or_q1_reg/Q + net (fo=1, routed) 0.339 -0.059 u_confreg/int_out_or_q1 + SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.687 -0.260 + clock pessimism 0.037 -0.223 + SLICE_X9Y47 FDRE (Hold_fdre_C_D) 0.075 -0.148 u_confreg/int_out_or_q2_reg + ------------------------------------------------------------------- + required time 0.148 + arrival time -0.059 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_confreg/int_out_or_q1_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/int_out_or_q2_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.480ns (logic 0.141ns (29.360%) route 0.339ns (70.640%)) + Logic Levels: 0 + Clock Path Skew: 0.316ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.260ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.309 -0.539 + SLICE_X4Y50 FDRE 0.000 -0.539 r u_confreg/int_out_or_q1_reg/C + SLICE_X4Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_confreg/int_out_or_q1_reg/Q + net (fo=1, routed) 0.339 -0.059 u_confreg/int_out_or_q1 + SLICE_X9Y47 FDRE f u_confreg/int_out_or_q2_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.687 -0.260 + clock pessimism 0.037 -0.223 + SLICE_X9Y47 FDRE (Hold_fdre_C_D) 0.075 -0.148 u_confreg/int_out_or_q2_reg + ------------------------------------------------------------------- + required time 0.148 + arrival time -0.059 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.090ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.252ns (logic 0.141ns (55.979%) route 0.111ns (44.021%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.615ns +======= + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.233 -0.615 + SLICE_X69Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[22]/C + SLICE_X69Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[22]/Q + net (fo=4, routed) 0.111 -0.363 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIB0 + SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I +======= + 1.181 -0.667 + SLICE_X117Y149 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C + SLICE_X117Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q + net (fo=4, routed) 0.068 -0.458 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 + SLICE_X116Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.561 -0.386 + clock pessimism -0.213 -0.599 + SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.453 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB + ------------------------------------------------------------------- + required time 0.453 + arrival time -0.363 + ------------------------------------------------------------------- + slack 0.090 + +Slack (MET) : 0.090ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.252ns (logic 0.141ns (55.979%) route 0.111ns (44.021%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.615ns +======= + 1.506 -0.441 + clock pessimism -0.213 -0.654 + SLICE_X116Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.458 + ------------------------------------------------------------------- + slack 0.049 + +Slack (MET) : 0.049ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.233 -0.615 + SLICE_X69Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[22]/C + SLICE_X69Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_cpu/u_csr/csr_tlbelo1_reg[22]/Q + net (fo=4, routed) 0.111 -0.363 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIB0 + SLICE_X66Y50 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I +======= + 1.181 -0.667 + SLICE_X117Y149 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C + SLICE_X117Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.526 f u_cpu/u_csr/csr_tlbelo1_reg[20]/Q + net (fo=4, routed) 0.068 -0.458 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 + SLICE_X116Y149 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.561 -0.386 + clock pessimism -0.213 -0.599 + SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.453 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB + ------------------------------------------------------------------- + required time 0.453 + arrival time -0.363 + ------------------------------------------------------------------- + slack 0.090 + +Slack (MET) : 0.090ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[11]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.128ns (37.132%) route 0.217ns (62.868%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns +======= + 1.506 -0.441 + clock pessimism -0.213 -0.654 + SLICE_X116Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.458 + ------------------------------------------------------------------- + slack 0.049 + +Slack (MET) : 0.057ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.276ns (logic 0.141ns (51.000%) route 0.135ns (49.000%)) + Logic Levels: 0 + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.178 -0.670 + SLICE_X135Y114 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C + SLICE_X135Y114 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/Q + net (fo=7, routed) 0.135 -0.394 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[6] + SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.502 -0.445 + clock pessimism -0.189 -0.634 + SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) + 0.183 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.451 + arrival time -0.394 + ------------------------------------------------------------------- + slack 0.057 + +Slack (MET) : 0.057ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.276ns (logic 0.141ns (51.000%) route 0.135ns (49.000%)) + Logic Levels: 0 + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.178 -0.670 + SLICE_X135Y114 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C + SLICE_X135Y114 FDCE (Prop_fdce_C_Q) 0.141 -0.529 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/Q + net (fo=7, routed) 0.135 -0.394 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[6] + SLICE_X136Y113 SRL16E f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.502 -0.445 + clock pessimism -0.189 -0.634 + SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) + 0.183 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.451 + arrival time -0.394 + ------------------------------------------------------------------- + slack 0.057 + +Slack (MET) : 0.058ns (arrival time - required time) + Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.400ns (logic 0.164ns (40.951%) route 0.236ns (59.049%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.453ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): -0.045ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.313 -0.536 + SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[11]/C + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[11]/Q + net (fo=1, routed) 0.217 -0.191 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC1 + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I +======= + 1.164 -0.685 + SLICE_X98Y152 FDRE 0.000 -0.685 r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C + SLICE_X98Y152 FDRE (Prop_fdre_C_Q) 0.164 -0.521 r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/Q + net (fo=2, routed) 0.236 -0.284 u_cpu/wb_stage/ms_to_ws_bus[78] + SLICE_X99Y148 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.060 -0.281 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1 + ------------------------------------------------------------------- + required time 0.281 + arrival time -0.191 + ------------------------------------------------------------------- + slack 0.090 + +Slack (MET) : 0.090ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[11]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.128ns (37.132%) route 0.217ns (62.868%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns +======= + 1.494 -0.453 + clock pessimism 0.045 -0.408 + SLICE_X99Y148 FDRE (Hold_fdre_C_D) 0.066 -0.342 u_cpu/wb_stage/ms_to_ws_bus_r_reg[114] + ------------------------------------------------------------------- + required time 0.342 + arrival time -0.284 + ------------------------------------------------------------------- + slack 0.058 + +Slack (MET) : 0.058ns (arrival time - required time) + Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.400ns (logic 0.164ns (40.951%) route 0.236ns (59.049%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.453ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): -0.045ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.313 -0.536 + SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[11]/C + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 f u_cpu/axi_bridge/araddr_reg[11]/Q + net (fo=1, routed) 0.217 -0.191 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC1 + SLICE_X44Y52 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I +======= + 1.164 -0.685 + SLICE_X98Y152 FDRE 0.000 -0.685 r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C + SLICE_X98Y152 FDRE (Prop_fdre_C_Q) 0.164 -0.521 f u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/Q + net (fo=2, routed) 0.236 -0.284 u_cpu/wb_stage/ms_to_ws_bus[78] + SLICE_X99Y148 FDRE f u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.060 -0.281 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1 + ------------------------------------------------------------------- + required time 0.281 + arrival time -0.191 + ------------------------------------------------------------------- + slack 0.090 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.358ns (logic 0.128ns (35.706%) route 0.230ns (64.294%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.313 -0.536 + SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[9]/C + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[9]/Q + net (fo=1, routed) 0.230 -0.177 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIB1 + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.071 -0.270 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.270 + arrival time -0.177 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.358ns (logic 0.128ns (35.706%) route 0.230ns (64.294%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.313 -0.536 + SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[9]/C + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 f u_cpu/axi_bridge/araddr_reg[9]/Q + net (fo=1, routed) 0.230 -0.177 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIB1 + SLICE_X44Y52 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.071 -0.270 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.270 + arrival time -0.177 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q + net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[2] + RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q + net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[2] + RAMB18_X6Y27 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q + net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[2] + RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q + net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[2] + RAMB18_X6Y26 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.094ns (arrival time - required time) + Source: u_cpu/axi_bridge/awaddr_reg[10]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.251ns (logic 0.141ns (56.174%) route 0.110ns (43.826%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.496ns + Clock Pessimism Removal (CPR): 0.222ns +======= + 1.494 -0.453 + clock pessimism 0.045 -0.408 + SLICE_X99Y148 FDRE (Hold_fdre_C_D) 0.066 -0.342 u_cpu/wb_stage/ms_to_ws_bus_r_reg[114] + ------------------------------------------------------------------- + required time 0.342 + arrival time -0.284 + ------------------------------------------------------------------- + slack 0.058 + +Slack (MET) : 0.061ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.683ns + Clock Pessimism Removal (CPR): 0.212ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.353 -0.496 + SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C + SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q + net (fo=1, routed) 0.110 -0.245 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 + SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I +======= + 1.166 -0.683 + SLICE_X103Y161 FDRE 0.000 -0.683 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C + SLICE_X103Y161 FDRE (Prop_fdre_C_Q) 0.141 -0.542 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/Q + net (fo=6, routed) 0.080 -0.462 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/DIA0 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.686 -0.261 + clock pessimism -0.222 -0.483 + SLICE_X16Y49 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC + ------------------------------------------------------------------- + required time 0.339 + arrival time -0.245 + ------------------------------------------------------------------- + slack 0.094 + +Slack (MET) : 0.094ns (arrival time - required time) + Source: u_cpu/axi_bridge/awaddr_reg[10]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.251ns (logic 0.141ns (56.174%) route 0.110ns (43.826%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.496ns + Clock Pessimism Removal (CPR): 0.222ns +======= + 1.489 -0.458 + clock pessimism -0.212 -0.670 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.523 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA + ------------------------------------------------------------------- + required time 0.523 + arrival time -0.462 + ------------------------------------------------------------------- + slack 0.061 + +Slack (MET) : 0.061ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.683ns + Clock Pessimism Removal (CPR): 0.212ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.353 -0.496 + SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C + SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 f u_cpu/axi_bridge/awaddr_reg[10]/Q + net (fo=1, routed) 0.110 -0.245 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 + SLICE_X16Y49 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I +======= + 1.166 -0.683 + SLICE_X103Y161 FDRE 0.000 -0.683 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C + SLICE_X103Y161 FDRE (Prop_fdre_C_Q) 0.141 -0.542 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/Q + net (fo=6, routed) 0.080 -0.462 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/DIA0 + SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.686 -0.261 + clock pessimism -0.222 -0.483 + SLICE_X16Y49 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC + ------------------------------------------------------------------- + required time 0.339 + arrival time -0.245 + ------------------------------------------------------------------- + slack 0.094 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns +======= + 1.489 -0.458 + clock pessimism -0.212 -0.670 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.523 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA + ------------------------------------------------------------------- + required time 0.523 + arrival time -0.462 + ------------------------------------------------------------------- + slack 0.061 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.355ns (logic 0.128ns (36.084%) route 0.227ns (63.916%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.172 -0.677 + SLICE_X105Y150 FDRE 0.000 -0.677 r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C + SLICE_X105Y150 FDRE (Prop_fdre_C_Q) 0.128 -0.549 r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/Q + net (fo=1, routed) 0.227 -0.322 u_cpu/mem_stage/D[126] + SLICE_X106Y149 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.502 -0.445 + clock pessimism 0.045 -0.400 + SLICE_X106Y149 FDRE (Hold_fdre_C_D) 0.016 -0.384 u_cpu/mem_stage/es_to_ms_bus_r_reg[126] + ------------------------------------------------------------------- + required time 0.384 + arrival time -0.322 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.355ns (logic 0.128ns (36.084%) route 0.227ns (63.916%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.172 -0.677 + SLICE_X105Y150 FDRE 0.000 -0.677 r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C + SLICE_X105Y150 FDRE (Prop_fdre_C_Q) 0.128 -0.549 f u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/Q + net (fo=1, routed) 0.227 -0.322 u_cpu/mem_stage/D[126] + SLICE_X106Y149 FDRE f u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.502 -0.445 + clock pessimism 0.045 -0.400 + SLICE_X106Y149 FDRE (Hold_fdre_C_D) 0.016 -0.384 u_cpu/mem_stage/es_to_ms_bus_r_reg[126] + ------------------------------------------------------------------- + required time 0.384 + arrival time -0.322 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMS32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X97Y146 FDRE 0.000 -0.680 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMS32 f u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.487 -0.460 + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.455ns (logic 0.164ns (36.015%) route 0.291ns (63.985%)) + Logic Levels: 0 + Clock Path Skew: 0.334ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.375ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.179 -0.669 + SLICE_X108Y101 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C + SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/Q + net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[16] + SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.572 -0.375 + clock pessimism 0.040 -0.335 + SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.059 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16] + ------------------------------------------------------------------- + required time 0.276 + arrival time -0.214 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.455ns (logic 0.164ns (36.015%) route 0.291ns (63.985%)) + Logic Levels: 0 + Clock Path Skew: 0.334ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.375ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.179 -0.669 + SLICE_X108Y101 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C + SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/Q + net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[16] + SLICE_X104Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.572 -0.375 + clock pessimism 0.040 -0.335 + SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.059 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16] + ------------------------------------------------------------------- + required time 0.276 + arrival time -0.214 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.063ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.223ns (logic 0.141ns (63.098%) route 0.082ns (36.902%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.181 -0.667 + SLICE_X121Y148 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo0_reg[26]/C + SLICE_X121Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo0_reg[26]/Q + net (fo=4, routed) 0.082 -0.444 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/DIA0 + SLICE_X120Y148 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.506 -0.441 + clock pessimism -0.213 -0.654 + SLICE_X120Y148 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.444 + ------------------------------------------------------------------- + slack 0.063 + +Slack (MET) : 0.063ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.223ns (logic 0.141ns (63.098%) route 0.082ns (36.902%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.181 -0.667 + SLICE_X121Y148 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo0_reg[26]/C + SLICE_X121Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.526 f u_cpu/u_csr/csr_tlbelo0_reg[26]/Q + net (fo=4, routed) 0.082 -0.444 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/DIA0 + SLICE_X120Y148 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.506 -0.441 + clock pessimism -0.213 -0.654 + SLICE_X120Y148 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.444 + ------------------------------------------------------------------- + slack 0.063 + +Slack (MET) : 0.064ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.443ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.179 -0.669 + SLICE_X109Y149 FDRE 0.000 -0.669 r u_cpu/u_csr/csr_tlbelo0_reg[5]/C + SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 r u_cpu/u_csr/csr_tlbelo0_reg[5]/Q + net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D + SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.504 -0.443 + clock pessimism -0.213 -0.656 + SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.512 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP + ------------------------------------------------------------------- + required time 0.512 + arrival time -0.448 + ------------------------------------------------------------------- + slack 0.064 + +Slack (MET) : 0.064ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.443ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.179 -0.669 + SLICE_X109Y149 FDRE 0.000 -0.669 r u_cpu/u_csr/csr_tlbelo0_reg[5]/C + SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 f u_cpu/u_csr/csr_tlbelo0_reg[5]/Q + net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D + SLICE_X108Y149 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.504 -0.443 + clock pessimism -0.213 -0.656 + SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.512 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP + ------------------------------------------------------------------- + required time 0.512 + arrival time -0.448 + ------------------------------------------------------------------- + slack 0.064 + +Slack (MET) : 0.066ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.226ns (logic 0.141ns (62.492%) route 0.085ns (37.508%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.181 -0.667 + SLICE_X117Y147 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo1_reg[14]/C + SLICE_X117Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[14]/Q + net (fo=4, routed) 0.085 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIA0 + SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.506 -0.441 + clock pessimism -0.213 -0.654 + SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.441 + ------------------------------------------------------------------- + slack 0.066 + +Slack (MET) : 0.066ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.226ns (logic 0.141ns (62.492%) route 0.085ns (37.508%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.181 -0.667 + SLICE_X117Y147 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo1_reg[14]/C + SLICE_X117Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 f u_cpu/u_csr/csr_tlbelo1_reg[14]/Q + net (fo=4, routed) 0.085 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIA0 + SLICE_X116Y147 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.506 -0.441 + clock pessimism -0.213 -0.654 + SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.441 + ------------------------------------------------------------------- + slack 0.066 + +Slack (MET) : 0.067ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[19]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[3] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.063 -0.269 r u_axi_uart_controller/uart0/regs/M_next_carry/O[3] + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.067 + +Slack (MET) : 0.067ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[19]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[3] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.063 -0.269 r u_axi_uart_controller/uart0/regs/M_next_carry/O[3] + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.067 + +Slack (MET) : 0.067ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[19]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[3] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.063 -0.269 r u_axi_uart_controller/uart0/regs/M_next_carry/O[3] + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.067 + +Slack (MET) : 0.067ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[19]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[3] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.063 -0.269 r u_axi_uart_controller/uart0/regs/M_next_carry/O[3] + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.067 + +Slack (MET) : 0.067ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[19]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[3] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.063 -0.269 f u_axi_uart_controller/uart0/regs/M_next_carry/O[3] + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] + SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.067 + +Slack (MET) : 0.067ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[19]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[3] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.063 -0.269 f u_axi_uart_controller/uart0/regs/M_next_carry/O[3] + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] + SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.067 + +Slack (MET) : 0.067ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[19]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[3] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.063 -0.269 f u_axi_uart_controller/uart0/regs/M_next_carry/O[3] + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] + SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.067 + +Slack (MET) : 0.067ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[19]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[19]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[3] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.063 -0.269 f u_axi_uart_controller/uart0/regs/M_next_carry/O[3] + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] + SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.067 + +Slack (MET) : 0.069ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.455ns (logic 0.164ns (36.017%) route 0.291ns (63.983%)) + Logic Levels: 0 + Clock Path Skew: 0.334ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.375ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.179 -0.669 + SLICE_X108Y101 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C + SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/Q + net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[17] + SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.572 -0.375 + clock pessimism 0.040 -0.335 + SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.052 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17] + ------------------------------------------------------------------- + required time 0.283 + arrival time -0.214 + ------------------------------------------------------------------- + slack 0.069 + +Slack (MET) : 0.069ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.455ns (logic 0.164ns (36.017%) route 0.291ns (63.983%)) + Logic Levels: 0 + Clock Path Skew: 0.334ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.375ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.179 -0.669 + SLICE_X108Y101 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C + SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/Q + net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[17] + SLICE_X104Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.572 -0.375 + clock pessimism 0.040 -0.335 + SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.052 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17] + ------------------------------------------------------------------- + required time 0.283 + arrival time -0.214 + ------------------------------------------------------------------- + slack 0.069 + +Slack (MET) : 0.071ns (arrival time - required time) + Source: u_matmul_axi_slave/req_1_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/busy_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.362ns (logic 0.186ns (51.410%) route 0.176ns (48.590%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.448ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.241 -0.607 + SLICE_X45Y99 FDRE 0.000 -0.607 r u_matmul_axi_slave/req_1_reg/C + SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r u_matmul_axi_slave/req_1_reg/Q + net (fo=19, routed) 0.176 -0.291 u_matmul_axi_slave/p_5_in[1] + SLICE_X45Y100 r u_matmul_axi_slave/busy_i_1/I2 + SLICE_X45Y100 LUT6 (Prop_lut6_I2_O) 0.045 -0.246 r u_matmul_axi_slave/busy_i_1/O + net (fo=1, routed) 0.000 -0.246 u_matmul_axi_slave/busy_i_1_n_0 + SLICE_X45Y100 FDRE r u_matmul_axi_slave/busy_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.499 -0.448 + clock pessimism 0.040 -0.408 + SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.091 -0.317 u_matmul_axi_slave/busy_reg + ------------------------------------------------------------------- + required time 0.317 + arrival time -0.246 + ------------------------------------------------------------------- + slack 0.071 + +Slack (MET) : 0.071ns (arrival time - required time) + Source: u_matmul_axi_slave/req_1_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/busy_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.362ns (logic 0.186ns (51.410%) route 0.176ns (48.590%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.448ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.241 -0.607 + SLICE_X45Y99 FDRE 0.000 -0.607 r u_matmul_axi_slave/req_1_reg/C + SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 f u_matmul_axi_slave/req_1_reg/Q + net (fo=19, routed) 0.176 -0.291 u_matmul_axi_slave/p_5_in[1] + SLICE_X45Y100 f u_matmul_axi_slave/busy_i_1/I2 + SLICE_X45Y100 LUT6 (Prop_lut6_I2_O) 0.045 -0.246 f u_matmul_axi_slave/busy_i_1/O + net (fo=1, routed) 0.000 -0.246 u_matmul_axi_slave/busy_i_1_n_0 + SLICE_X45Y100 FDRE f u_matmul_axi_slave/busy_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.499 -0.448 + clock pessimism 0.040 -0.408 + SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.091 -0.317 u_matmul_axi_slave/busy_reg + ------------------------------------------------------------------- + required time 0.317 + arrival time -0.246 + ------------------------------------------------------------------- + slack 0.071 + +Slack (MET) : 0.073ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.393ns (logic 0.227ns (57.716%) route 0.166ns (42.284%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.453ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.236 -0.612 + SLICE_X63Y98 FDRE 0.000 -0.612 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C + SLICE_X63Y98 FDRE (Prop_fdre_C_Q) 0.128 -0.484 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/Q + net (fo=7, routed) 0.166 -0.318 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[1] + SLICE_X62Y100 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/I1 + SLICE_X62Y100 LUT6 (Prop_lut6_I1_O) 0.099 -0.219 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/O + net (fo=1, routed) 0.000 -0.219 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/p_1_in[2] + SLICE_X62Y100 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.494 -0.453 + clock pessimism 0.040 -0.413 + SLICE_X62Y100 FDRE (Hold_fdre_C_D) 0.121 -0.292 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2] + ------------------------------------------------------------------- + required time 0.292 + arrival time -0.219 + ------------------------------------------------------------------- + slack 0.073 + +Slack (MET) : 0.073ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.393ns (logic 0.227ns (57.716%) route 0.166ns (42.284%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.453ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.236 -0.612 + SLICE_X63Y98 FDRE 0.000 -0.612 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C + SLICE_X63Y98 FDRE (Prop_fdre_C_Q) 0.128 -0.484 f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/Q + net (fo=7, routed) 0.166 -0.318 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[1] + SLICE_X62Y100 f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/I1 + SLICE_X62Y100 LUT6 (Prop_lut6_I1_O) 0.099 -0.219 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/O + net (fo=1, routed) 0.000 -0.219 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/p_1_in[2] + SLICE_X62Y100 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.494 -0.453 + clock pessimism 0.040 -0.413 + SLICE_X62Y100 FDRE (Hold_fdre_C_D) 0.121 -0.292 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2] + ------------------------------------------------------------------- + required time 0.292 + arrival time -0.219 + ------------------------------------------------------------------- + slack 0.073 + +Slack (MET) : 0.073ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.393ns (logic 0.227ns (57.716%) route 0.166ns (42.284%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.453ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.236 -0.612 + SLICE_X63Y98 FDRE 0.000 -0.612 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C + SLICE_X63Y98 FDRE (Prop_fdre_C_Q) 0.128 -0.484 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/Q + net (fo=7, routed) 0.166 -0.318 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[1] + SLICE_X62Y100 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/I1 + SLICE_X62Y100 LUT6 (Prop_lut6_I1_O) 0.099 -0.219 f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/O + net (fo=1, routed) 0.000 -0.219 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/p_1_in[2] + SLICE_X62Y100 FDRE f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.494 -0.453 + clock pessimism 0.040 -0.413 + SLICE_X62Y100 FDRE (Hold_fdre_C_D) 0.121 -0.292 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2] + ------------------------------------------------------------------- + required time 0.292 + arrival time -0.219 + ------------------------------------------------------------------- + slack 0.073 + +Slack (MET) : 0.073ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.393ns (logic 0.227ns (57.716%) route 0.166ns (42.284%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.453ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.236 -0.612 + SLICE_X63Y98 FDRE 0.000 -0.612 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C + SLICE_X63Y98 FDRE (Prop_fdre_C_Q) 0.128 -0.484 f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/Q + net (fo=7, routed) 0.166 -0.318 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[1] + SLICE_X62Y100 f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/I1 + SLICE_X62Y100 LUT6 (Prop_lut6_I1_O) 0.099 -0.219 f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/O + net (fo=1, routed) 0.000 -0.219 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/p_1_in[2] + SLICE_X62Y100 FDRE f u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.494 -0.453 + clock pessimism 0.040 -0.413 + SLICE_X62Y100 FDRE (Hold_fdre_C_D) 0.121 -0.292 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2] + ------------------------------------------------------------------- + required time 0.292 + arrival time -0.219 + ------------------------------------------------------------------- + slack 0.073 + +Slack (MET) : 0.073ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.437ns (logic 0.189ns (43.230%) route 0.248ns (56.770%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.257ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.486ns + Source Clock Delay (SCD): -0.703ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.145 -0.703 + SLICE_X87Y130 FDRE 0.000 -0.703 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q + net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] + SLICE_X82Y126 r u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/I2 + SLICE_X82Y126 LUT4 (Prop_lut4_I2_O) 0.048 -0.266 r u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/O + net (fo=1, routed) 0.000 -0.266 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[19] + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.461 -0.486 + clock pessimism 0.040 -0.446 + SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.107 -0.339 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19] + ------------------------------------------------------------------- + required time 0.339 + arrival time -0.266 + ------------------------------------------------------------------- + slack 0.073 + +Slack (MET) : 0.073ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.437ns (logic 0.189ns (43.230%) route 0.248ns (56.770%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.257ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.486ns + Source Clock Delay (SCD): -0.703ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.145 -0.703 + SLICE_X87Y130 FDRE 0.000 -0.703 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 f u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q + net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] + SLICE_X82Y126 f u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/I2 + SLICE_X82Y126 LUT4 (Prop_lut4_I2_O) 0.048 -0.266 f u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/O + net (fo=1, routed) 0.000 -0.266 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[19] + SLICE_X82Y126 FDRE f u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.461 -0.486 + clock pessimism 0.040 -0.446 + SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.107 -0.339 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19] + ------------------------------------------------------------------- + required time 0.339 + arrival time -0.266 + ------------------------------------------------------------------- + slack 0.073 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[0] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) + 0.070 -0.262 r u_axi_uart_controller/uart0/regs/M_next_carry/O[0] + net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.262 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[0] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) + 0.070 -0.262 r u_axi_uart_controller/uart0/regs/M_next_carry/O[0] + net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.262 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[0] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) + 0.070 -0.262 r u_axi_uart_controller/uart0/regs/M_next_carry/O[0] + net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.262 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[0] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) + 0.070 -0.262 r u_axi_uart_controller/uart0/regs/M_next_carry/O[0] + net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.262 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[0] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) + 0.070 -0.262 f u_axi_uart_controller/uart0/regs/M_next_carry/O[0] + net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] + SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.262 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[0] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) + 0.070 -0.262 f u_axi_uart_controller/uart0/regs/M_next_carry/O[0] + net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] + SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.262 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[0] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) + 0.070 -0.262 f u_axi_uart_controller/uart0/regs/M_next_carry/O[0] + net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] + SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.262 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 f u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[0] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) + 0.070 -0.262 f u_axi_uart_controller/uart0/regs/M_next_carry/O[0] + net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] + SLICE_X85Y129 FDRE f u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.262 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.425ns (logic 0.209ns (49.172%) route 0.216ns (50.828%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.259ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.486ns + Source Clock Delay (SCD): -0.705ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.143 -0.705 + SLICE_X84Y128 FDRE 0.000 -0.705 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C + SLICE_X84Y128 FDRE (Prop_fdre_C_Q) 0.164 -0.541 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/Q + net (fo=23, routed) 0.216 -0.325 u_Axi_CDC/wFifo/Q[19] + SLICE_X82Y126 r u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/I3 + SLICE_X82Y126 LUT6 (Prop_lut6_I3_O) 0.045 -0.280 r u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/O + net (fo=1, routed) 0.000 -0.280 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[3] + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.461 -0.486 + clock pessimism 0.040 -0.446 + SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.092 -0.354 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3] + ------------------------------------------------------------------- + required time 0.354 + arrival time -0.280 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.425ns (logic 0.209ns (49.172%) route 0.216ns (50.828%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.259ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.486ns + Source Clock Delay (SCD): -0.705ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.143 -0.705 + SLICE_X84Y128 FDRE 0.000 -0.705 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C + SLICE_X84Y128 FDRE (Prop_fdre_C_Q) 0.164 -0.541 f u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/Q + net (fo=23, routed) 0.216 -0.325 u_Axi_CDC/wFifo/Q[19] + SLICE_X82Y126 f u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/I3 + SLICE_X82Y126 LUT6 (Prop_lut6_I3_O) 0.045 -0.280 f u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/O + net (fo=1, routed) 0.000 -0.280 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[3] + SLICE_X82Y126 FDRE f u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.461 -0.486 + clock pessimism 0.040 -0.446 + SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.092 -0.354 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3] + ------------------------------------------------------------------- + required time 0.354 + arrival time -0.280 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.080ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/ier_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.436ns (logic 0.209ns (47.943%) route 0.227ns (52.057%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.476ns + Source Clock Delay (SCD): -0.700ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.148 -0.700 + SLICE_X84Y133 FDRE 0.000 -0.700 r u_axi_uart_controller/uart0/regs/ier_reg[3]/C + SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/ier_reg[3]/Q + net (fo=3, routed) 0.227 -0.309 u_axi_uart_controller/uart0/regs/transmitter/Q[0] + SLICE_X83Y135 r u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/I1 + SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.264 r u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/O + net (fo=1, routed) 0.000 -0.264 u_axi_uart_controller/uart0/regs/transmitter_n_1 + SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.471 -0.476 + clock pessimism 0.040 -0.436 + SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ms_int_pnd_reg + ------------------------------------------------------------------- + required time 0.344 + arrival time -0.264 + ------------------------------------------------------------------- + slack 0.080 + +Slack (MET) : 0.080ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/ier_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.436ns (logic 0.209ns (47.943%) route 0.227ns (52.057%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.476ns + Source Clock Delay (SCD): -0.700ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.148 -0.700 + SLICE_X84Y133 FDRE 0.000 -0.700 r u_axi_uart_controller/uart0/regs/ier_reg[3]/C + SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 f u_axi_uart_controller/uart0/regs/ier_reg[3]/Q + net (fo=3, routed) 0.227 -0.309 u_axi_uart_controller/uart0/regs/transmitter/Q[0] + SLICE_X83Y135 f u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/I1 + SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.264 f u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/O + net (fo=1, routed) 0.000 -0.264 u_axi_uart_controller/uart0/regs/transmitter_n_1 + SLICE_X83Y135 FDRE f u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.471 -0.476 + clock pessimism 0.040 -0.436 + SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ms_int_pnd_reg + ------------------------------------------------------------------- + required time 0.344 + arrival time -0.264 + ------------------------------------------------------------------- + slack 0.080 + +Slack (MET) : 0.081ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.465ns (logic 0.186ns (40.004%) route 0.279ns (59.996%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.705ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.143 -0.705 + SLICE_X85Y128 FDRE 0.000 -0.705 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C + SLICE_X85Y128 FDRE (Prop_fdre_C_Q) 0.141 -0.564 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/Q + net (fo=20, routed) 0.279 -0.285 u_Axi_CDC/wFifo/Q[14] + SLICE_X80Y128 r u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/I4 + SLICE_X80Y128 LUT5 (Prop_lut5_I4_O) 0.045 -0.240 r u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/O + net (fo=1, routed) 0.000 -0.240 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[14] + SLICE_X80Y128 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X80Y128 FDRE (Hold_fdre_C_D) 0.120 -0.321 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14] + ------------------------------------------------------------------- + required time 0.321 + arrival time -0.240 + ------------------------------------------------------------------- + slack 0.081 + +Slack (MET) : 0.081ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.465ns (logic 0.186ns (40.004%) route 0.279ns (59.996%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.705ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.143 -0.705 + SLICE_X85Y128 FDRE 0.000 -0.705 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C + SLICE_X85Y128 FDRE (Prop_fdre_C_Q) 0.141 -0.564 f u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/Q + net (fo=20, routed) 0.279 -0.285 u_Axi_CDC/wFifo/Q[14] + SLICE_X80Y128 f u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/I4 + SLICE_X80Y128 LUT5 (Prop_lut5_I4_O) 0.045 -0.240 f u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/O + net (fo=1, routed) 0.000 -0.240 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[14] + SLICE_X80Y128 FDRE f u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X80Y128 FDRE (Hold_fdre_C_D) 0.120 -0.321 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14] + ------------------------------------------------------------------- + required time 0.321 + arrival time -0.240 + ------------------------------------------------------------------- + slack 0.081 + +Slack (MET) : 0.083ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/ier_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.439ns (logic 0.209ns (47.634%) route 0.230ns (52.366%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.476ns + Source Clock Delay (SCD): -0.700ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.148 -0.700 + SLICE_X84Y133 FDRE 0.000 -0.700 r u_axi_uart_controller/uart0/regs/ier_reg[0]/C + SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/ier_reg[0]/Q + net (fo=6, routed) 0.230 -0.306 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/Q[0] + SLICE_X83Y135 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/I1 + SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.261 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/O + net (fo=1, routed) 0.000 -0.261 u_axi_uart_controller/uart0/regs/receiver_n_1 + SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.471 -0.476 + clock pessimism 0.040 -0.436 + SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ti_int_pnd_reg + ------------------------------------------------------------------- + required time 0.344 + arrival time -0.261 + ------------------------------------------------------------------- + slack 0.083 + +Slack (MET) : 0.083ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/ier_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.439ns (logic 0.209ns (47.634%) route 0.230ns (52.366%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.476ns + Source Clock Delay (SCD): -0.700ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.148 -0.700 + SLICE_X84Y133 FDRE 0.000 -0.700 r u_axi_uart_controller/uart0/regs/ier_reg[0]/C + SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 f u_axi_uart_controller/uart0/regs/ier_reg[0]/Q + net (fo=6, routed) 0.230 -0.306 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/Q[0] + SLICE_X83Y135 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/I1 + SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.261 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/O + net (fo=1, routed) 0.000 -0.261 u_axi_uart_controller/uart0/regs/receiver_n_1 + SLICE_X83Y135 FDRE f u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.471 -0.476 + clock pessimism 0.040 -0.436 + SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ti_int_pnd_reg + ------------------------------------------------------------------- + required time 0.344 + arrival time -0.261 + ------------------------------------------------------------------- + slack 0.083 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X43Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q + net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/Q[7] + RAMB18_X2Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.602 -0.346 + clock pessimism -0.213 -0.559 + RAMB18_X2Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.292 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X43Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q + net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/Q[7] + RAMB18_X2Y26 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.602 -0.346 + clock pessimism -0.213 -0.559 + RAMB18_X2Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.292 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X43Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q + net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/Q[7] + RAMB18_X2Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.602 -0.346 + clock pessimism -0.213 -0.559 + RAMB18_X2Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.292 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X43Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q + net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/Q[7] + RAMB18_X2Y27 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.602 -0.346 + clock pessimism -0.213 -0.559 + RAMB18_X2Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.292 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.403ns (logic 0.164ns (40.684%) route 0.239ns (59.316%)) + Logic Levels: 0 + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns + Source Clock Delay (SCD): -0.679ns + Clock Pessimism Removal (CPR): -0.045ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 +======= + 1.169 -0.679 + SLICE_X98Y148 FDRE 0.000 -0.679 r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C + SLICE_X98Y148 FDRE (Prop_fdre_C_Q) 0.164 -0.515 r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/Q + net (fo=2, routed) 0.239 -0.276 u_cpu/wb_stage/ms_to_ws_bus[69] + SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 +======= + 1.490 -0.457 + clock pessimism 0.045 -0.412 + SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.052 -0.360 u_cpu/wb_stage/ms_to_ws_bus_r_reg[105] + ------------------------------------------------------------------- + required time 0.360 + arrival time -0.276 +>>>>>>> Stashed changes + ------------------------------------------------------------------- + slack 0.084 + +<<<<<<< Updated upstream +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns +======= +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.403ns (logic 0.164ns (40.684%) route 0.239ns (59.316%)) + Logic Levels: 0 + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns + Source Clock Delay (SCD): -0.679ns + Clock Pessimism Removal (CPR): -0.045ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 +======= + 1.169 -0.679 + SLICE_X98Y148 FDRE 0.000 -0.679 r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C + SLICE_X98Y148 FDRE (Prop_fdre_C_Q) 0.164 -0.515 f u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/Q + net (fo=2, routed) 0.239 -0.276 u_cpu/wb_stage/ms_to_ws_bus[69] + SLICE_X100Y150 FDRE f u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 +======= + 1.490 -0.457 + clock pessimism 0.045 -0.412 + SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.052 -0.360 u_cpu/wb_stage/ms_to_ws_bus_r_reg[105] + ------------------------------------------------------------------- + required time 0.360 + arrival time -0.276 +>>>>>>> Stashed changes + ------------------------------------------------------------------- + slack 0.084 + +<<<<<<< Updated upstream +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMS32 f u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMS32 f u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.097ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.141ns (31.804%) route 0.302ns (68.196%)) + Logic Levels: 0 + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns +======= +Slack (MET) : 0.085ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.479ns (logic 0.141ns (29.406%) route 0.338ns (70.594%)) + Logic Levels: 0 + Clock Path Skew: 0.275ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.444ns + Source Clock Delay (SCD): -0.674ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.619 + SLICE_X157Y150 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C + SLICE_X157Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/Q + net (fo=14, routed) 0.302 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[13] + SLICE_X159Y138 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + clock pessimism 0.045 -0.343 + SLICE_X159Y138 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13] + ------------------------------------------------------------------- + required time 0.273 + arrival time -0.176 + ------------------------------------------------------------------- + slack 0.097 + +Slack (MET) : 0.097ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.141ns (31.804%) route 0.302ns (68.196%)) + Logic Levels: 0 + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns +======= + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.175 -0.674 + SLICE_X115Y150 FDRE 0.000 -0.674 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C + SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q + net (fo=4, routed) 0.338 -0.194 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 + SLICE_X112Y141 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.503 -0.444 + clock pessimism 0.045 -0.399 + SLICE_X112Y141 RAMD32 (Hold_ramd32_CLK_I) + 0.120 -0.279 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 + ------------------------------------------------------------------- + required time 0.279 + arrival time -0.194 + ------------------------------------------------------------------- + slack 0.085 + +Slack (MET) : 0.085ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.479ns (logic 0.141ns (29.406%) route 0.338ns (70.594%)) + Logic Levels: 0 + Clock Path Skew: 0.275ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.444ns + Source Clock Delay (SCD): -0.674ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.619 + SLICE_X157Y150 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C + SLICE_X157Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/Q + net (fo=14, routed) 0.302 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[13] + SLICE_X159Y138 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D +======= + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.175 -0.674 + SLICE_X115Y150 FDRE 0.000 -0.674 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C + SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/u_csr/csr_tlbelo1_reg[27]/Q + net (fo=4, routed) 0.338 -0.194 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 + SLICE_X112Y141 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.503 -0.444 + clock pessimism 0.045 -0.399 + SLICE_X112Y141 RAMD32 (Hold_ramd32_CLK_I) + 0.120 -0.279 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 + ------------------------------------------------------------------- + required time 0.279 + arrival time -0.194 + ------------------------------------------------------------------- + slack 0.085 + +Slack (MET) : 0.085ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.281ns (logic 0.141ns (50.089%) route 0.140ns (49.911%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.211ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.178 -0.670 + SLICE_X133Y115 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C + SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/Q + net (fo=6, routed) 0.140 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[7] + SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.559 -0.388 + clock pessimism 0.045 -0.343 + SLICE_X159Y138 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13] + ------------------------------------------------------------------- + required time 0.273 + arrival time -0.176 + ------------------------------------------------------------------- + slack 0.097 + +Slack (MET) : 0.098ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns +======= + 1.501 -0.446 + clock pessimism -0.211 -0.657 + SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) + 0.183 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.474 + arrival time -0.388 + ------------------------------------------------------------------- + slack 0.085 + +Slack (MET) : 0.085ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.281ns (logic 0.141ns (50.089%) route 0.140ns (49.911%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.211ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.178 -0.670 + SLICE_X133Y115 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C + SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/Q + net (fo=6, routed) 0.140 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[7] + SLICE_X132Y115 SRL16E f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.501 -0.446 + clock pessimism -0.211 -0.657 + SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) + 0.183 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.474 + arrival time -0.388 + ------------------------------------------------------------------- + slack 0.085 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X79Y131 FDRE 0.000 -0.702 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.470 -0.477 + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.434ns (logic 0.186ns (42.838%) route 0.248ns (57.162%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.257ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.486ns + Source Clock Delay (SCD): -0.703ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.145 -0.703 + SLICE_X87Y130 FDRE 0.000 -0.703 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q + net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] + SLICE_X82Y126 r u_Axi_CDC/wFifo/reg_datai_32[11]_i_1/I2 + SLICE_X82Y126 LUT5 (Prop_lut5_I2_O) 0.045 -0.269 r u_Axi_CDC/wFifo/reg_datai_32[11]_i_1/O + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[11] + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.461 -0.486 + clock pessimism 0.040 -0.446 + SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.091 -0.355 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11] + ------------------------------------------------------------------- + required time 0.355 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.434ns (logic 0.186ns (42.838%) route 0.248ns (57.162%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.257ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.486ns + Source Clock Delay (SCD): -0.703ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.145 -0.703 + SLICE_X87Y130 FDRE 0.000 -0.703 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 f u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q + net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] + SLICE_X82Y126 f u_Axi_CDC/wFifo/reg_datai_32[11]_i_1/I2 + SLICE_X82Y126 LUT5 (Prop_lut5_I2_O) 0.045 -0.269 f u_Axi_CDC/wFifo/reg_datai_32[11]_i_1/O + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[11] + SLICE_X82Y126 FDRE f u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.461 -0.486 + clock pessimism 0.040 -0.446 + SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.091 -0.355 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11] + ------------------------------------------------------------------- + required time 0.355 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_matmul_axi_slave/req_0_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/req_0_reg_rep__0/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.378ns (logic 0.186ns (49.193%) route 0.192ns (50.807%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.448ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.241 -0.607 + SLICE_X45Y99 FDRE 0.000 -0.607 r u_matmul_axi_slave/req_0_reg/C + SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r u_matmul_axi_slave/req_0_reg/Q + net (fo=96, routed) 0.192 -0.274 u_matmul_axi_slave/p_5_in[0] + SLICE_X45Y100 r u_matmul_axi_slave/req_0_rep_i_1__0/I4 + SLICE_X45Y100 LUT6 (Prop_lut6_I4_O) 0.045 -0.229 r u_matmul_axi_slave/req_0_rep_i_1__0/O + net (fo=1, routed) 0.000 -0.229 u_matmul_axi_slave/req_0_rep_i_1__0_n_0 + SLICE_X45Y100 FDRE r u_matmul_axi_slave/req_0_reg_rep__0/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.499 -0.448 + clock pessimism 0.040 -0.408 + SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.092 -0.316 u_matmul_axi_slave/req_0_reg_rep__0 + ------------------------------------------------------------------- + required time 0.316 + arrival time -0.229 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_matmul_axi_slave/req_0_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/req_0_reg_rep__0/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.378ns (logic 0.186ns (49.193%) route 0.192ns (50.807%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.448ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.241 -0.607 + SLICE_X45Y99 FDRE 0.000 -0.607 r u_matmul_axi_slave/req_0_reg/C + SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 f u_matmul_axi_slave/req_0_reg/Q + net (fo=96, routed) 0.192 -0.274 u_matmul_axi_slave/p_5_in[0] + SLICE_X45Y100 f u_matmul_axi_slave/req_0_rep_i_1__0/I4 + SLICE_X45Y100 LUT6 (Prop_lut6_I4_O) 0.045 -0.229 f u_matmul_axi_slave/req_0_rep_i_1__0/O + net (fo=1, routed) 0.000 -0.229 u_matmul_axi_slave/req_0_rep_i_1__0_n_0 + SLICE_X45Y100 FDRE f u_matmul_axi_slave/req_0_reg_rep__0/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.499 -0.448 + clock pessimism 0.040 -0.408 + SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.092 -0.316 u_matmul_axi_slave/req_0_reg_rep__0 + ------------------------------------------------------------------- + required time 0.316 + arrival time -0.229 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/enable_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.186ns (42.057%) route 0.256ns (57.943%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.478ns +>>>>>>> Stashed changes + Source Clock Delay (SCD): -0.701ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.148 -0.701 + SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q + net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 + SLICE_X87Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/I3 + SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/O + net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1_n_0 + SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D +======= + 1.147 -0.701 + SLICE_X86Y132 FDRE 0.000 -0.701 r u_axi_uart_controller/uart0/regs/enable_reg/C + SLICE_X86Y132 FDRE (Prop_fdre_C_Q) 0.141 -0.560 r u_axi_uart_controller/uart0/regs/enable_reg/Q + net (fo=12, routed) 0.256 -0.304 u_axi_uart_controller/uart0/regs/enable + SLICE_X83Y133 r u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/I1 + SLICE_X83Y133 LUT4 (Prop_lut4_I1_O) 0.045 -0.259 r u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/O + net (fo=1, routed) 0.000 -0.259 u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1_n_0 + SLICE_X83Y133 FDRE r u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.472 -0.475 + clock pessimism 0.040 -0.435 + SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.092 -0.343 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4] + ------------------------------------------------------------------- + required time 0.343 + arrival time -0.245 + ------------------------------------------------------------------- + slack 0.098 + +Slack (MET) : 0.098ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns +======= + 1.469 -0.478 + clock pessimism 0.040 -0.438 + SLICE_X83Y133 FDRE (Hold_fdre_C_D) 0.092 -0.346 u_axi_uart_controller/uart0/regs/sclk_en_reg_reg + ------------------------------------------------------------------- + required time 0.346 + arrival time -0.259 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/enable_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.186ns (42.057%) route 0.256ns (57.943%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.478ns +>>>>>>> Stashed changes + Source Clock Delay (SCD): -0.701ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.148 -0.701 + SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q + net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 + SLICE_X87Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/I3 + SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/O + net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1_n_0 + SLICE_X87Y152 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D +======= + 1.147 -0.701 + SLICE_X86Y132 FDRE 0.000 -0.701 r u_axi_uart_controller/uart0/regs/enable_reg/C + SLICE_X86Y132 FDRE (Prop_fdre_C_Q) 0.141 -0.560 f u_axi_uart_controller/uart0/regs/enable_reg/Q + net (fo=12, routed) 0.256 -0.304 u_axi_uart_controller/uart0/regs/enable + SLICE_X83Y133 f u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/I1 + SLICE_X83Y133 LUT4 (Prop_lut4_I1_O) 0.045 -0.259 r u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/O + net (fo=1, routed) 0.000 -0.259 u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1_n_0 + SLICE_X83Y133 FDRE r u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.472 -0.475 + clock pessimism 0.040 -0.435 + SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.092 -0.343 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4] + ------------------------------------------------------------------- + required time 0.343 + arrival time -0.245 + ------------------------------------------------------------------- + slack 0.098 + +Slack (MET) : 0.099ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns +======= + 1.469 -0.478 + clock pessimism 0.040 -0.438 + SLICE_X83Y133 FDRE (Hold_fdre_C_D) 0.092 -0.346 u_axi_uart_controller/uart0/regs/sclk_en_reg_reg + ------------------------------------------------------------------- + required time 0.346 + arrival time -0.259 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/enable_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.186ns (42.057%) route 0.256ns (57.943%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.478ns +>>>>>>> Stashed changes + Source Clock Delay (SCD): -0.701ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.148 -0.701 + SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q + net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 + SLICE_X87Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/I3 + SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/O + net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1_n_0 + SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D +======= + 1.147 -0.701 + SLICE_X86Y132 FDRE 0.000 -0.701 r u_axi_uart_controller/uart0/regs/enable_reg/C + SLICE_X86Y132 FDRE (Prop_fdre_C_Q) 0.141 -0.560 r u_axi_uart_controller/uart0/regs/enable_reg/Q + net (fo=12, routed) 0.256 -0.304 u_axi_uart_controller/uart0/regs/enable + SLICE_X83Y133 r u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/I1 + SLICE_X83Y133 LUT4 (Prop_lut4_I1_O) 0.045 -0.259 f u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/O + net (fo=1, routed) 0.000 -0.259 u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1_n_0 + SLICE_X83Y133 FDRE f u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.472 -0.475 + clock pessimism 0.040 -0.435 + SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.091 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3] + ------------------------------------------------------------------- + required time 0.344 + arrival time -0.245 + ------------------------------------------------------------------- + slack 0.099 + +Slack (MET) : 0.099ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns +======= + 1.469 -0.478 + clock pessimism 0.040 -0.438 + SLICE_X83Y133 FDRE (Hold_fdre_C_D) 0.092 -0.346 u_axi_uart_controller/uart0/regs/sclk_en_reg_reg + ------------------------------------------------------------------- + required time 0.346 + arrival time -0.259 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/enable_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.186ns (42.057%) route 0.256ns (57.943%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.478ns +>>>>>>> Stashed changes + Source Clock Delay (SCD): -0.701ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.148 -0.701 + SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q + net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 + SLICE_X87Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/I3 + SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/O + net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1_n_0 + SLICE_X87Y152 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D +======= + 1.147 -0.701 + SLICE_X86Y132 FDRE 0.000 -0.701 r u_axi_uart_controller/uart0/regs/enable_reg/C + SLICE_X86Y132 FDRE (Prop_fdre_C_Q) 0.141 -0.560 f u_axi_uart_controller/uart0/regs/enable_reg/Q + net (fo=12, routed) 0.256 -0.304 u_axi_uart_controller/uart0/regs/enable + SLICE_X83Y133 f u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/I1 + SLICE_X83Y133 LUT4 (Prop_lut4_I1_O) 0.045 -0.259 f u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/O + net (fo=1, routed) 0.000 -0.259 u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1_n_0 + SLICE_X83Y133 FDRE f u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.472 -0.475 + clock pessimism 0.040 -0.435 + SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.091 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3] + ------------------------------------------------------------------- + required time 0.344 + arrival time -0.245 + ------------------------------------------------------------------- + slack 0.099 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.366ns (logic 0.164ns (44.815%) route 0.202ns (55.185%)) + Logic Levels: 0 + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.506ns + Clock Pessimism Removal (CPR): -0.037ns +======= + 1.469 -0.478 + clock pessimism 0.040 -0.438 + SLICE_X83Y133 FDRE (Hold_fdre_C_D) 0.092 -0.346 u_axi_uart_controller/uart0/regs/sclk_en_reg_reg + ------------------------------------------------------------------- + required time 0.346 + arrival time -0.259 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q + net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[5] + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.374 + clock pessimism 0.040 -0.333 + RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.061 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q + net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[5] + RAMB18_X7Y40 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.374 + clock pessimism 0.040 -0.333 + RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.061 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q + net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[5] + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.374 + clock pessimism 0.040 -0.333 + RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.061 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q + net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[5] + RAMB18_X7Y41 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.374 + clock pessimism 0.040 -0.333 + RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.061 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.415ns (logic 0.141ns (33.953%) route 0.274ns (66.047%)) + Logic Levels: 0 + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns + Source Clock Delay (SCD): -0.679ns + Clock Pessimism Removal (CPR): -0.045ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.343 -0.506 + SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C + SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q + net (fo=33, routed) 0.202 -0.140 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] + SLICE_X37Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D +======= + 1.169 -0.679 + SLICE_X97Y148 FDRE 0.000 -0.679 r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C + SLICE_X97Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.538 r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/Q + net (fo=2, routed) 0.274 -0.264 u_cpu/wb_stage/ms_to_ws_bus[68] + SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.609 -0.338 - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] +<<<<<<< Updated upstream + 1.601 -0.346 + clock pessimism 0.037 -0.309 + SLICE_X37Y51 FDRE (Hold_fdre_C_D) 0.070 -0.239 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 + required time 0.239 + arrival time -0.140 ------------------------------------------------------------------- - slack 0.885 + slack 0.100 -Slack (MET) : 0.885ns (arrival time - required time) +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.366ns (logic 0.164ns (44.815%) route 0.202ns (55.185%)) + Logic Levels: 0 + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.506ns + Clock Pessimism Removal (CPR): -0.037ns +======= + 1.490 -0.457 + clock pessimism 0.045 -0.412 + SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.059 -0.353 u_cpu/wb_stage/ms_to_ws_bus_r_reg[104] + ------------------------------------------------------------------- + required time 0.353 + arrival time -0.264 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.415ns (logic 0.141ns (33.953%) route 0.274ns (66.047%)) + Logic Levels: 0 + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns + Source Clock Delay (SCD): -0.679ns + Clock Pessimism Removal (CPR): -0.045ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.343 -0.506 + SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C + SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 f u_cpu/u_csr/csr_tlbidx_reg[26]/Q + net (fo=33, routed) 0.202 -0.140 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] + SLICE_X37Y51 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D +======= + 1.169 -0.679 + SLICE_X97Y148 FDRE 0.000 -0.679 r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C + SLICE_X97Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.538 f u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/Q + net (fo=2, routed) 0.274 -0.264 u_cpu/wb_stage/ms_to_ws_bus[68] + SLICE_X100Y150 FDRE f u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.601 -0.346 + clock pessimism 0.037 -0.309 + SLICE_X37Y51 FDRE (Hold_fdre_C_D) 0.070 -0.239 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2] + ------------------------------------------------------------------- + required time 0.239 + arrival time -0.140 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns +======= + 1.490 -0.457 + clock pessimism 0.045 -0.412 + SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.059 -0.353 u_cpu/wb_stage/ms_to_ws_bus_r_reg[104] + ------------------------------------------------------------------- + required time 0.353 + arrival time -0.264 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.091ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.443ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.179 -0.669 + SLICE_X109Y149 FDRE 0.000 -0.669 r u_cpu/u_csr/csr_tlbelo0_reg[5]/C + SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 r u_cpu/u_csr/csr_tlbelo0_reg[5]/Q + net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D + SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.504 -0.443 + clock pessimism -0.213 -0.656 + SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.117 -0.539 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP + ------------------------------------------------------------------- + required time 0.539 + arrival time -0.448 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.091ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.443ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.179 -0.669 + SLICE_X109Y149 FDRE 0.000 -0.669 r u_cpu/u_csr/csr_tlbelo0_reg[5]/C + SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 f u_cpu/u_csr/csr_tlbelo0_reg[5]/Q + net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D + SLICE_X108Y149 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.504 -0.443 + clock pessimism -0.213 -0.656 + SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.117 -0.539 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP + ------------------------------------------------------------------- + required time 0.539 + arrival time -0.448 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.809ns (logic 0.367ns (45.351%) route 0.442ns (54.649%)) + Logic Levels: 0 + Clock Path Skew: 0.022ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.499ns + Source Clock Delay (SCD): -2.113ns + Clock Pessimism Removal (CPR): -0.407ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -5.674 -5.674 + propagated clock network latency + 3.561 -2.113 + SLICE_X57Y90 FDCE 0.000 -2.113 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=8, routed) 0.442 -1.304 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.777 -2.499 + clock pessimism 0.407 -2.091 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.694 -1.397 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 1.397 + arrival time -1.304 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.809ns (logic 0.367ns (45.351%) route 0.442ns (54.649%)) + Logic Levels: 0 + Clock Path Skew: 0.022ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.499ns + Source Clock Delay (SCD): -2.113ns + Clock Pessimism Removal (CPR): -0.407ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -5.674 -5.674 + propagated clock network latency + 3.561 -2.113 + SLICE_X57Y90 FDCE 0.000 -2.113 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=8, routed) 0.442 -1.304 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X56Y90 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.777 -2.499 + clock pessimism 0.407 -2.091 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.694 -1.397 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 1.397 + arrival time -1.304 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.809ns (logic 0.367ns (45.351%) route 0.442ns (54.649%)) + Logic Levels: 0 + Clock Path Skew: 0.022ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.499ns + Source Clock Delay (SCD): -2.113ns + Clock Pessimism Removal (CPR): -0.407ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -5.674 -5.674 + propagated clock network latency + 3.561 -2.113 + SLICE_X57Y90 FDCE 0.000 -2.113 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=8, routed) 0.442 -1.304 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.777 -2.499 + clock pessimism 0.407 -2.091 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.694 -1.397 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 1.397 + arrival time -1.304 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.809ns (logic 0.367ns (45.351%) route 0.442ns (54.649%)) + Logic Levels: 0 + Clock Path Skew: 0.022ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.499ns + Source Clock Delay (SCD): -2.113ns + Clock Pessimism Removal (CPR): -0.407ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -5.674 -5.674 + propagated clock network latency + 3.561 -2.113 + SLICE_X57Y90 FDCE 0.000 -2.113 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=8, routed) 0.442 -1.304 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X56Y90 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.777 -2.499 + clock pessimism 0.407 -2.091 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.694 -1.397 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 1.397 + arrival time -1.304 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_csr/csr_cntc_reg[1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.141ns (31.802%) route 0.302ns (68.198%)) + Logic Levels: 0 + Clock Path Skew: 0.278ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.684ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.165 -0.684 + SLICE_X101Y154 FDRE 0.000 -0.684 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/C + SLICE_X101Y154 FDRE (Prop_fdre_C_Q) 0.141 -0.543 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/Q + net (fo=21, routed) 0.302 -0.241 u_cpu/u_csr/wr_csr_data[1] + SLICE_X101Y149 FDRE r u_cpu/u_csr/csr_cntc_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism 0.045 -0.406 + SLICE_X101Y149 FDRE (Hold_fdre_C_D) 0.070 -0.336 u_cpu/u_csr/csr_cntc_reg[1] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.241 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_csr/csr_cntc_reg[1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.141ns (31.802%) route 0.302ns (68.198%)) + Logic Levels: 0 + Clock Path Skew: 0.278ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.684ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.165 -0.684 + SLICE_X101Y154 FDRE 0.000 -0.684 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/C + SLICE_X101Y154 FDRE (Prop_fdre_C_Q) 0.141 -0.543 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/Q + net (fo=21, routed) 0.302 -0.241 u_cpu/u_csr/wr_csr_data[1] + SLICE_X101Y149 FDRE f u_cpu/u_csr/csr_cntc_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism 0.045 -0.406 + SLICE_X101Y149 FDRE (Hold_fdre_C_D) 0.070 -0.336 u_cpu/u_csr/csr_cntc_reg[1] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.241 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.281ns (logic 0.141ns (50.221%) route 0.140ns (49.779%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.447ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.175 -0.674 + SLICE_X115Y150 FDRE 0.000 -0.674 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C + SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q + net (fo=4, routed) 0.140 -0.393 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/DIA0 + SLICE_X116Y151 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.500 -0.447 + clock pessimism -0.189 -0.636 + SLICE_X116Y151 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.489 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA + ------------------------------------------------------------------- + required time 0.489 + arrival time -0.393 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.281ns (logic 0.141ns (50.221%) route 0.140ns (49.779%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.447ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.175 -0.674 + SLICE_X115Y150 FDRE 0.000 -0.674 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C + SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/u_csr/csr_tlbelo1_reg[26]/Q + net (fo=4, routed) 0.140 -0.393 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/DIA0 + SLICE_X116Y151 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.500 -0.447 + clock pessimism -0.189 -0.636 + SLICE_X116Y151 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.489 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA + ------------------------------------------------------------------- + required time 0.489 + arrival time -0.393 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.258ns (logic 0.141ns (54.698%) route 0.117ns (45.302%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.671ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.177 -0.671 + SLICE_X106Y147 FDRE 0.000 -0.671 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C + SLICE_X106Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.530 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q + net (fo=7, routed) 0.117 -0.413 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/D + SLICE_X104Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.502 -0.445 + clock pessimism -0.210 -0.655 + SLICE_X104Y147 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.509 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP + ------------------------------------------------------------------- + required time 0.509 + arrival time -0.413 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.258ns (logic 0.141ns (54.698%) route 0.117ns (45.302%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.671ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.177 -0.671 + SLICE_X106Y147 FDRE 0.000 -0.671 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C + SLICE_X106Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.530 f u_cpu/u_csr/csr_tlbelo1_reg[2]/Q + net (fo=7, routed) 0.117 -0.413 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/D + SLICE_X104Y147 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.502 -0.445 + clock pessimism -0.210 -0.655 + SLICE_X104Y147 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.509 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP + ------------------------------------------------------------------- + required time 0.509 + arrival time -0.413 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[18]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.256ns (logic 0.141ns (55.072%) route 0.115ns (44.928%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.181 -0.667 + SLICE_X118Y147 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo1_reg[18]/C + SLICE_X118Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[18]/Q + net (fo=4, routed) 0.115 -0.411 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIC0 + SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.506 -0.441 + clock pessimism -0.210 -0.651 + SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.411 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[18]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.256ns (logic 0.141ns (55.072%) route 0.115ns (44.928%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.181 -0.667 + SLICE_X118Y147 FDRE 0.000 -0.667 r u_cpu/u_csr/csr_tlbelo1_reg[18]/C + SLICE_X118Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 f u_cpu/u_csr/csr_tlbelo1_reg[18]/Q + net (fo=4, routed) 0.115 -0.411 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIC0 + SLICE_X116Y147 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.506 -0.441 + clock pessimism -0.210 -0.651 + SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.411 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.128 -0.482 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.236 -0.246 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.255 -0.342 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.342 + arrival time -0.246 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.128 -0.482 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.236 -0.246 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X56Y90 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.255 -0.342 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.342 + arrival time -0.246 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.128 -0.482 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.236 -0.246 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.255 -0.342 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.342 + arrival time -0.246 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + SLICE_X57Y90 FDCE 0.000 -0.610 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.128 -0.482 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.236 -0.246 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X56Y90 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.255 -0.342 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.342 + arrival time -0.246 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.098ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[24]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.258ns (logic 0.141ns (54.609%) route 0.117ns (45.391%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.442ns + Source Clock Delay (SCD): -0.668ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 +======= + 1.180 -0.668 + SLICE_X114Y149 FDRE 0.000 -0.668 r u_cpu/u_csr/csr_tlbelo0_reg[24]/C + SLICE_X114Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.527 r u_cpu/u_csr/csr_tlbelo0_reg[24]/Q + net (fo=4, routed) 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIC0 + SLICE_X112Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/I +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns +======= + 1.505 -0.442 + clock pessimism -0.210 -0.652 + SLICE_X112Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.508 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC + ------------------------------------------------------------------- + required time 0.508 + arrival time -0.410 + ------------------------------------------------------------------- + slack 0.098 + +Slack (MET) : 0.098ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[24]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.258ns (logic 0.141ns (54.609%) route 0.117ns (45.391%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.442ns + Source Clock Delay (SCD): -0.668ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 +======= + 1.180 -0.668 + SLICE_X114Y149 FDRE 0.000 -0.668 r u_cpu/u_csr/csr_tlbelo0_reg[24]/C + SLICE_X114Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.527 f u_cpu/u_csr/csr_tlbelo0_reg[24]/Q + net (fo=4, routed) 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIC0 + SLICE_X112Y149 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/I +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.101ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_a_reg[1][28]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D +======= + 1.505 -0.442 + clock pessimism -0.210 -0.652 + SLICE_X112Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.508 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC + ------------------------------------------------------------------- + required time 0.508 + arrival time -0.410 + ------------------------------------------------------------------- + slack 0.098 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_a_reg[1][14]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/D +>>>>>>> Stashed changes + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.496ns (logic 0.164ns (33.088%) route 0.332ns (66.911%)) + Logic Levels: 0 + Clock Path Skew: 0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.675ns +======= + Data Path Delay: 0.368ns (logic 0.141ns (38.301%) route 0.227ns (61.699%)) + Logic Levels: 0 + Clock Path Skew: 0.198ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.411ns + Source Clock Delay (SCD): -0.569ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.173 -0.675 + SLICE_X44Y105 FDRE 0.000 -0.675 r u_matmul_axi_slave/m_in_a_reg[1][28]/C + SLICE_X44Y105 FDRE (Prop_fdre_C_Q) 0.164 -0.511 r u_matmul_axi_slave/m_in_a_reg[1][28]/Q + net (fo=1, routed) 0.332 -0.179 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[28] + SLICE_X56Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D +======= + 1.279 -0.569 + SLICE_X23Y99 FDRE 0.000 -0.569 r u_matmul_axi_slave/m_in_a_reg[1][14]/C + SLICE_X23Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.428 r u_matmul_axi_slave/m_in_a_reg[1][14]/Q + net (fo=1, routed) 0.227 -0.201 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[14] + SLICE_X23Y107 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X56Y98 FDRE (Hold_fdre_C_D) 0.059 -0.280 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28] + ------------------------------------------------------------------- + required time 0.280 + arrival time -0.179 + ------------------------------------------------------------------- + slack 0.101 + +Slack (MET) : 0.101ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_a_reg[1][28]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D +======= + 1.536 -0.411 + clock pessimism 0.040 -0.371 + SLICE_X23Y107 FDRE (Hold_fdre_C_D) 0.070 -0.301 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14] + ------------------------------------------------------------------- + required time 0.301 + arrival time -0.201 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_a_reg[1][14]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/D +>>>>>>> Stashed changes + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.496ns (logic 0.164ns (33.088%) route 0.332ns (66.911%)) + Logic Levels: 0 + Clock Path Skew: 0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.675ns + Clock Pessimism Removal (CPR): -0.040ns +======= + Data Path Delay: 0.368ns (logic 0.141ns (38.301%) route 0.227ns (61.699%)) + Logic Levels: 0 + Clock Path Skew: 0.198ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.411ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.279 -0.569 + SLICE_X23Y99 FDRE 0.000 -0.569 r u_matmul_axi_slave/m_in_a_reg[1][14]/C + SLICE_X23Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.428 f u_matmul_axi_slave/m_in_a_reg[1][14]/Q + net (fo=1, routed) 0.227 -0.201 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[14] + SLICE_X23Y107 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.536 -0.411 + clock pessimism 0.040 -0.371 + SLICE_X23Y107 FDRE (Hold_fdre_C_D) 0.070 -0.301 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14] + ------------------------------------------------------------------- + required time 0.301 + arrival time -0.201 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.453ns (logic 0.186ns (41.032%) route 0.267ns (58.968%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.262ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.480ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X87Y131 FDRE 0.000 -0.702 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C + SLICE_X87Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/Q + net (fo=20, routed) 0.267 -0.294 u_Axi_CDC/wFifo/Q[6] + SLICE_X81Y129 r u_Axi_CDC/wFifo/reg_datai_32[6]_i_1/I5 + SLICE_X81Y129 LUT6 (Prop_lut6_I5_O) 0.045 -0.249 r u_Axi_CDC/wFifo/reg_datai_32[6]_i_1/O + net (fo=1, routed) 0.000 -0.249 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[6] + SLICE_X81Y129 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.467 -0.480 + clock pessimism 0.040 -0.440 + SLICE_X81Y129 FDRE (Hold_fdre_C_D) 0.091 -0.349 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6] + ------------------------------------------------------------------- + required time 0.349 + arrival time -0.249 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.453ns (logic 0.186ns (41.032%) route 0.267ns (58.968%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.262ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.480ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.146 -0.702 + SLICE_X87Y131 FDRE 0.000 -0.702 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C + SLICE_X87Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 f u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/Q + net (fo=20, routed) 0.267 -0.294 u_Axi_CDC/wFifo/Q[6] + SLICE_X81Y129 f u_Axi_CDC/wFifo/reg_datai_32[6]_i_1/I5 + SLICE_X81Y129 LUT6 (Prop_lut6_I5_O) 0.045 -0.249 f u_Axi_CDC/wFifo/reg_datai_32[6]_i_1/O + net (fo=1, routed) 0.000 -0.249 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[6] + SLICE_X81Y129 FDRE f u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.467 -0.480 + clock pessimism 0.040 -0.440 + SLICE_X81Y129 FDRE (Hold_fdre_C_D) 0.091 -0.349 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6] + ------------------------------------------------------------------- + required time 0.349 + arrival time -0.249 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.102ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.455ns (logic 0.186ns (40.841%) route 0.269ns (59.159%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.482ns + Source Clock Delay (SCD): -0.703ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.145 -0.703 + SLICE_X86Y130 FDRE 0.000 -0.703 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C + SLICE_X86Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/Q + net (fo=20, routed) 0.269 -0.293 u_Axi_CDC/wFifo/Q[0] + SLICE_X79Y127 r u_Axi_CDC/wFifo/reg_datai_32[0]_i_1/I5 + SLICE_X79Y127 LUT6 (Prop_lut6_I5_O) 0.045 -0.248 r u_Axi_CDC/wFifo/reg_datai_32[0]_i_1/O + net (fo=1, routed) 0.000 -0.248 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[0] + SLICE_X79Y127 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.465 -0.482 + clock pessimism 0.040 -0.442 + SLICE_X79Y127 FDRE (Hold_fdre_C_D) 0.092 -0.350 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0] + ------------------------------------------------------------------- + required time 0.350 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.102 + +Slack (MET) : 0.102ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.455ns (logic 0.186ns (40.841%) route 0.269ns (59.159%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.482ns + Source Clock Delay (SCD): -0.703ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.145 -0.703 + SLICE_X86Y130 FDRE 0.000 -0.703 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C + SLICE_X86Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 f u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/Q + net (fo=20, routed) 0.269 -0.293 u_Axi_CDC/wFifo/Q[0] + SLICE_X79Y127 f u_Axi_CDC/wFifo/reg_datai_32[0]_i_1/I5 + SLICE_X79Y127 LUT6 (Prop_lut6_I5_O) 0.045 -0.248 f u_Axi_CDC/wFifo/reg_datai_32[0]_i_1/O + net (fo=1, routed) 0.000 -0.248 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[0] + SLICE_X79Y127 FDRE f u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.465 -0.482 + clock pessimism 0.040 -0.442 + SLICE_X79Y127 FDRE (Hold_fdre_C_D) 0.092 -0.350 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0] + ------------------------------------------------------------------- + required time 0.350 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.102 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMA + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 f u_cpu/btb/ras_reg_0_7_12_17/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMA + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1 + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 f u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1 + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMB + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 f u_cpu/btb/ras_reg_0_7_12_17/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMB + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1 + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 f u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1 + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMC + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 f u_cpu/btb/ras_reg_0_7_12_17/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMC + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1 + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 f u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1 + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMS32 r u_cpu/btb/ras_reg_0_7_12_17/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMD + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMS32 f u_cpu/btb/ras_reg_0_7_12_17/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMD + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMS32 r u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1 + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMS32 f u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.496 -0.451 + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1 + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.233ns (logic 0.141ns (60.420%) route 0.092ns (39.580%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.211ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.178 -0.670 + SLICE_X133Y115 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C + SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/Q + net (fo=7, routed) 0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[2] + SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.501 -0.446 + clock pessimism -0.211 -0.657 + SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) + 0.117 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.540 + arrival time -0.437 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.233ns (logic 0.141ns (60.420%) route 0.092ns (39.580%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.211ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.173 -0.675 + SLICE_X44Y105 FDRE 0.000 -0.675 r u_matmul_axi_slave/m_in_a_reg[1][28]/C + SLICE_X44Y105 FDRE (Prop_fdre_C_Q) 0.164 -0.511 f u_matmul_axi_slave/m_in_a_reg[1][28]/Q + net (fo=1, routed) 0.332 -0.179 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[28] + SLICE_X56Y98 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D +======= + 1.178 -0.670 + SLICE_X133Y115 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C + SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/Q + net (fo=7, routed) 0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[2] + SLICE_X132Y115 SRL16E f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X56Y98 FDRE (Hold_fdre_C_D) 0.059 -0.280 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28] + ------------------------------------------------------------------- + required time 0.280 + arrival time -0.179 + ------------------------------------------------------------------- + slack 0.101 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[4]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.286ns (logic 0.141ns (49.244%) route 0.145ns (50.756%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.537ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.312 -0.537 + SLICE_X50Y43 FDRE 0.000 -0.537 r u_cpu/u_csr/csr_tlbelo0_reg[4]/C + SLICE_X50Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_cpu/u_csr/csr_tlbelo0_reg[4]/Q + net (fo=7, routed) 0.145 -0.250 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/D + SLICE_X48Y43 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.643 -0.304 + clock pessimism -0.196 -0.500 + SLICE_X48Y43 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.354 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP + ------------------------------------------------------------------- + required time 0.354 + arrival time -0.250 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[4]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.286ns (logic 0.141ns (49.244%) route 0.145ns (50.756%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.537ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.312 -0.537 + SLICE_X50Y43 FDRE 0.000 -0.537 r u_cpu/u_csr/csr_tlbelo0_reg[4]/C + SLICE_X50Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.396 f u_cpu/u_csr/csr_tlbelo0_reg[4]/Q + net (fo=7, routed) 0.145 -0.250 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/D + SLICE_X48Y43 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.643 -0.304 + clock pessimism -0.196 -0.500 + SLICE_X48Y43 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.354 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP + ------------------------------------------------------------------- + required time 0.354 + arrival time -0.250 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[10]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.141ns (31.876%) route 0.301ns (68.124%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.313 -0.536 + SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[10]/C + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_cpu/axi_bridge/araddr_reg[10]/Q + net (fo=1, routed) 0.301 -0.093 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC0 + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.197 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC + ------------------------------------------------------------------- + required time 0.197 + arrival time -0.093 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[10]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.141ns (31.876%) route 0.301ns (68.124%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.313 -0.536 + SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[10]/C + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.395 f u_cpu/axi_bridge/araddr_reg[10]/Q + net (fo=1, routed) 0.301 -0.093 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC0 + SLICE_X44Y52 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.197 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC + ------------------------------------------------------------------- + required time 0.197 + arrival time -0.093 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.451ns (logic 0.141ns (31.244%) route 0.310ns (68.756%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.619 + SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/Q + net (fo=15, routed) 0.310 -0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[18] + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.070 -0.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18] + ------------------------------------------------------------------- + required time 0.272 + arrival time -0.168 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.451ns (logic 0.141ns (31.244%) route 0.310ns (68.756%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.619 + SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/Q + net (fo=15, routed) 0.310 -0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[18] + SLICE_X159Y140 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.070 -0.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18] + ------------------------------------------------------------------- + required time 0.272 + arrival time -0.168 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q + net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[4] + RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.270 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q + net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[4] + RAMB18_X6Y27 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.270 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q + net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[4] + RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.270 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q + net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[4] + RAMB18_X6Y26 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.270 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.449ns (logic 0.141ns (31.381%) route 0.308ns (68.619%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.619 + SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/Q + net (fo=15, routed) 0.308 -0.170 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[17] + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.066 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17] + ------------------------------------------------------------------- + required time 0.276 + arrival time -0.170 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.449ns (logic 0.141ns (31.381%) route 0.308ns (68.619%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.619 + SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/Q + net (fo=15, routed) 0.308 -0.170 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[17] + SLICE_X159Y140 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.066 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17] + ------------------------------------------------------------------- + required time 0.276 + arrival time -0.170 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/buf_addr_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.425ns (logic 0.186ns (43.780%) route 0.239ns (56.220%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X13Y45 FDRE 0.000 -0.495 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C + SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/Q + net (fo=13, routed) 0.239 -0.115 u_Axi_CDC/arFifo/_zz_ram_port1[2] + SLICE_X16Y51 r u_Axi_CDC/arFifo/buf_addr[2]_i_1/I1 + SLICE_X16Y51 LUT5 (Prop_lut5_I1_O) 0.045 -0.070 r u_Axi_CDC/arFifo/buf_addr[2]_i_1/O + net (fo=1, routed) 0.000 -0.070 u_confreg/buf_addr_reg[15]_0[2] + SLICE_X16Y51 FDRE r u_confreg/buf_addr_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.611 -0.336 + clock pessimism 0.037 -0.299 + SLICE_X16Y51 FDRE (Hold_fdre_C_D) 0.121 -0.178 u_confreg/buf_addr_reg[2] + ------------------------------------------------------------------- + required time 0.178 + arrival time -0.070 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/buf_addr_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.425ns (logic 0.186ns (43.780%) route 0.239ns (56.220%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X13Y45 FDRE 0.000 -0.495 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C + SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.354 f u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/Q + net (fo=13, routed) 0.239 -0.115 u_Axi_CDC/arFifo/_zz_ram_port1[2] + SLICE_X16Y51 f u_Axi_CDC/arFifo/buf_addr[2]_i_1/I1 + SLICE_X16Y51 LUT5 (Prop_lut5_I1_O) 0.045 -0.070 f u_Axi_CDC/arFifo/buf_addr[2]_i_1/O + net (fo=1, routed) 0.000 -0.070 u_confreg/buf_addr_reg[15]_0[2] + SLICE_X16Y51 FDRE f u_confreg/buf_addr_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.611 -0.336 + clock pessimism 0.037 -0.299 + SLICE_X16Y51 FDRE (Hold_fdre_C_D) 0.121 -0.178 u_confreg/buf_addr_reg[2] + ------------------------------------------------------------------- + required time 0.178 + arrival time -0.070 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_confreg/digital_data_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.353ns (logic 0.141ns (39.954%) route 0.212ns (60.046%)) + Logic Levels: 0 + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.384 -0.465 + SLICE_X0Y49 FDRE 0.000 -0.465 r u_confreg/digital_data_reg[1]/C + SLICE_X0Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.324 r u_confreg/digital_data_reg[1]/Q + net (fo=2, routed) 0.212 -0.112 u_confreg/u_digitaltube_controller/dpy1_data_reg[3]_0[1] + SLICE_X0Y54 FDRE r u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism 0.037 -0.269 + SLICE_X0Y54 FDRE (Hold_fdre_C_D) 0.047 -0.222 u_confreg/u_digitaltube_controller/dpy0_data_reg[1] + ------------------------------------------------------------------- + required time 0.222 + arrival time -0.112 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_confreg/digital_data_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.353ns (logic 0.141ns (39.954%) route 0.212ns (60.046%)) + Logic Levels: 0 + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.384 -0.465 + SLICE_X0Y49 FDRE 0.000 -0.465 r u_confreg/digital_data_reg[1]/C + SLICE_X0Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.324 f u_confreg/digital_data_reg[1]/Q + net (fo=2, routed) 0.212 -0.112 u_confreg/u_digitaltube_controller/dpy1_data_reg[3]_0[1] + SLICE_X0Y54 FDRE f u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism 0.037 -0.269 + SLICE_X0Y54 FDRE (Hold_fdre_C_D) 0.047 -0.222 u_confreg/u_digitaltube_controller/dpy0_data_reg[1] + ------------------------------------------------------------------- + required time 0.222 + arrival time -0.112 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.410ns (logic 0.209ns (50.949%) route 0.201ns (49.051%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.192ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.371ns + Source Clock Delay (SCD): -0.527ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.322 -0.527 + SLICE_X116Y49 FDRE 0.000 -0.527 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C + SLICE_X116Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.363 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/Q + net (fo=5, routed) 0.201 -0.162 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[3] + SLICE_X118Y50 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/I2 + SLICE_X118Y50 LUT3 (Prop_lut3_I2_O) 0.045 -0.117 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/O + net (fo=1, routed) 0.000 -0.117 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[3] + SLICE_X118Y50 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.576 -0.371 + clock pessimism 0.037 -0.334 + SLICE_X118Y50 FDRE (Hold_fdre_C_D) 0.107 -0.227 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3] + ------------------------------------------------------------------- + required time 0.227 + arrival time -0.117 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.410ns (logic 0.209ns (50.949%) route 0.201ns (49.051%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.192ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.371ns + Source Clock Delay (SCD): -0.527ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.322 -0.527 + SLICE_X116Y49 FDRE 0.000 -0.527 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C + SLICE_X116Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.363 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/Q + net (fo=5, routed) 0.201 -0.162 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[3] + SLICE_X118Y50 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/I2 + SLICE_X118Y50 LUT3 (Prop_lut3_I2_O) 0.045 -0.117 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/O + net (fo=1, routed) 0.000 -0.117 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[3] + SLICE_X118Y50 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.576 -0.371 + clock pessimism 0.037 -0.334 + SLICE_X118Y50 FDRE (Hold_fdre_C_D) 0.107 -0.227 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3] + ------------------------------------------------------------------- + required time 0.227 + arrival time -0.117 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[24]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.376ns (logic 0.141ns (37.453%) route 0.235ns (62.547%)) + Logic Levels: 0 + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.345ns + Source Clock Delay (SCD): -0.504ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.345 -0.504 + SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[24]/C + SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[24]/Q + net (fo=33, routed) 0.235 -0.127 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[5] + SLICE_X32Y53 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.602 -0.345 + clock pessimism 0.037 -0.308 + SLICE_X32Y53 FDRE (Hold_fdre_C_D) 0.070 -0.238 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0] + ------------------------------------------------------------------- + required time 0.238 + arrival time -0.127 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[24]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.376ns (logic 0.141ns (37.453%) route 0.235ns (62.547%)) + Logic Levels: 0 + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.345ns + Source Clock Delay (SCD): -0.504ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.345 -0.504 + SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[24]/C + SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/u_csr/csr_tlbidx_reg[24]/Q + net (fo=33, routed) 0.235 -0.127 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[5] + SLICE_X32Y53 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.602 -0.345 + clock pessimism 0.037 -0.308 + SLICE_X32Y53 FDRE (Hold_fdre_C_D) 0.070 -0.238 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0] + ------------------------------------------------------------------- + required time 0.238 + arrival time -0.127 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.928%) route 0.287ns (67.072%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.490ns + Source Clock Delay (SCD): -0.711ns +======= + 1.501 -0.446 + clock pessimism -0.211 -0.657 + SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) + 0.117 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.540 + arrival time -0.437 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMS32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMS32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMS32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y147 FDRE 0.000 -0.674 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMS32 f u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1 + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1 + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1 + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1 + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1 + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1 + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1 + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X69Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1 + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.240ns (logic 0.186ns (77.466%) route 0.054ns (22.534%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.456ns + Source Clock Delay (SCD): -0.682ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.166 -0.682 + SLICE_X63Y110 FDRE 0.000 -0.682 r u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/C + SLICE_X63Y110 FDRE (Prop_fdre_C_Q) 0.141 -0.541 r u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/Q + net (fo=1, routed) 0.054 -0.487 u_cdma_matmul_bridge/bank_dst_addr_reg[1]_3[20] + SLICE_X62Y110 r u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1/I0 + SLICE_X62Y110 LUT6 (Prop_lut6_I0_O) 0.045 -0.442 r u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1/O + net (fo=1, routed) 0.000 -0.442 u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1_n_0 + SLICE_X62Y110 FDRE r u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.491 -0.456 + clock pessimism -0.213 -0.669 + SLICE_X62Y110 FDRE (Hold_fdre_C_D) 0.121 -0.548 u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20] + ------------------------------------------------------------------- + required time 0.548 + arrival time -0.442 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.240ns (logic 0.186ns (77.466%) route 0.054ns (22.534%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.456ns + Source Clock Delay (SCD): -0.682ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.166 -0.682 + SLICE_X63Y110 FDRE 0.000 -0.682 r u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/C + SLICE_X63Y110 FDRE (Prop_fdre_C_Q) 0.141 -0.541 f u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/Q + net (fo=1, routed) 0.054 -0.487 u_cdma_matmul_bridge/bank_dst_addr_reg[1]_3[20] + SLICE_X62Y110 f u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1/I0 + SLICE_X62Y110 LUT6 (Prop_lut6_I0_O) 0.045 -0.442 f u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1/O + net (fo=1, routed) 0.000 -0.442 u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1_n_0 + SLICE_X62Y110 FDRE f u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.491 -0.456 + clock pessimism -0.213 -0.669 + SLICE_X62Y110 FDRE (Hold_fdre_C_D) 0.121 -0.548 u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20] + ------------------------------------------------------------------- + required time 0.548 + arrival time -0.442 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.107ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[22]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.269ns (logic 0.141ns (52.500%) route 0.128ns (47.500%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.442ns + Source Clock Delay (SCD): -0.668ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.180 -0.668 + SLICE_X115Y149 FDRE 0.000 -0.668 r u_cpu/u_csr/csr_tlbelo0_reg[22]/C + SLICE_X115Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.527 r u_cpu/u_csr/csr_tlbelo0_reg[22]/Q + net (fo=4, routed) 0.128 -0.399 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIB0 + SLICE_X112Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.505 -0.442 + clock pessimism -0.210 -0.652 + SLICE_X112Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.506 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB + ------------------------------------------------------------------- + required time 0.506 + arrival time -0.399 + ------------------------------------------------------------------- + slack 0.107 + +Slack (MET) : 0.107ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[22]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.269ns (logic 0.141ns (52.500%) route 0.128ns (47.500%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.442ns + Source Clock Delay (SCD): -0.668ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.180 -0.668 + SLICE_X115Y149 FDRE 0.000 -0.668 r u_cpu/u_csr/csr_tlbelo0_reg[22]/C + SLICE_X115Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.527 f u_cpu/u_csr/csr_tlbelo0_reg[22]/Q + net (fo=4, routed) 0.128 -0.399 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIB0 + SLICE_X112Y149 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.505 -0.442 + clock pessimism -0.210 -0.652 + SLICE_X112Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.506 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB + ------------------------------------------------------------------- + required time 0.506 + arrival time -0.399 + ------------------------------------------------------------------- + slack 0.107 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/u_csr/timer_64_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.172 -0.677 + SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C + SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q + net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] + SLICE_X106Y146 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 + SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O + net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/A1 + SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.501 -0.446 + clock pessimism 0.045 -0.401 + SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP + ------------------------------------------------------------------- + required time 0.092 + arrival time 0.016 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/u_csr/timer_64_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.172 -0.677 + SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C + SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 f u_cpu/u_csr/timer_64_reg[1]/Q + net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] + SLICE_X106Y146 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 + SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O + net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/A1 + SLICE_X104Y145 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.501 -0.446 + clock pessimism 0.045 -0.401 + SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP + ------------------------------------------------------------------- + required time 0.092 + arrival time 0.016 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/u_csr/timer_64_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.172 -0.677 + SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C + SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q + net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] + SLICE_X106Y146 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 + SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O + net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/A1 + SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.501 -0.446 + clock pessimism 0.045 -0.401 + SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP + ------------------------------------------------------------------- + required time 0.092 + arrival time 0.016 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/u_csr/timer_64_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.172 -0.677 + SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C + SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 f u_cpu/u_csr/timer_64_reg[1]/Q + net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] + SLICE_X106Y146 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 + SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O + net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/A1 + SLICE_X104Y145 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.501 -0.446 + clock pessimism 0.045 -0.401 + SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP + ------------------------------------------------------------------- + required time 0.092 + arrival time 0.016 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/u_csr/timer_64_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.172 -0.677 + SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C + SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q + net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] + SLICE_X106Y146 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 + SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O + net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/A1 + SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.501 -0.446 + clock pessimism 0.045 -0.401 + SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP + ------------------------------------------------------------------- + required time 0.092 + arrival time 0.016 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/u_csr/timer_64_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.172 -0.677 + SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C + SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 f u_cpu/u_csr/timer_64_reg[1]/Q + net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] + SLICE_X106Y146 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 + SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O + net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/A1 + SLICE_X104Y145 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.501 -0.446 + clock pessimism 0.045 -0.401 + SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP + ------------------------------------------------------------------- + required time 0.092 + arrival time 0.016 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/u_csr/timer_64_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.172 -0.677 + SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C + SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q + net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] + SLICE_X106Y146 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 + SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O + net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/A1 + SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.501 -0.446 + clock pessimism 0.045 -0.401 + SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP + ------------------------------------------------------------------- + required time 0.092 + arrival time 0.016 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/u_csr/timer_64_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.172 -0.677 + SLICE_X106Y151 FDRE 0.000 -0.677 r u_cpu/u_csr/timer_64_reg[1]/C + SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 f u_cpu/u_csr/timer_64_reg[1]/Q + net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] + SLICE_X106Y146 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/I0 + SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 f u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O + net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/A1 + SLICE_X104Y145 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.501 -0.446 + clock pessimism 0.045 -0.401 + SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP + ------------------------------------------------------------------- + required time 0.092 + arrival time 0.016 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 + SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.495 -0.452 + clock pessimism -0.210 -0.662 + SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMA + ------------------------------------------------------------------- + required time 0.352 + arrival time -0.244 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 + SLICE_X132Y165 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.495 -0.452 + clock pessimism -0.210 -0.662 + SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMA + ------------------------------------------------------------------- + required time 0.352 + arrival time -0.244 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 + SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.495 -0.452 + clock pessimism -0.210 -0.662 + SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 + ------------------------------------------------------------------- + required time 0.352 + arrival time -0.244 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 + SLICE_X132Y165 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.495 -0.452 + clock pessimism -0.210 -0.662 + SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 + ------------------------------------------------------------------- + required time 0.352 + arrival time -0.244 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 + SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.495 -0.452 + clock pessimism -0.210 -0.662 + SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMB + ------------------------------------------------------------------- + required time 0.352 + arrival time -0.244 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 + SLICE_X132Y165 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.495 -0.452 + clock pessimism -0.210 -0.662 + SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMB + ------------------------------------------------------------------- + required time 0.352 + arrival time -0.244 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 + SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.495 -0.452 + clock pessimism -0.210 -0.662 + SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 + ------------------------------------------------------------------- + required time 0.352 + arrival time -0.244 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.173 -0.676 + SLICE_X133Y163 FDRE 0.000 -0.676 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 + SLICE_X132Y165 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.495 -0.452 + clock pessimism -0.210 -0.662 + SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 + ------------------------------------------------------------------- + required time 0.352 + arrival time -0.244 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.540ns (logic 0.186ns (34.444%) route 0.354ns (65.556%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.340ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.683ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.165 -0.683 + SLICE_X71Y100 FDRE 0.000 -0.683 r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C + SLICE_X71Y100 FDRE (Prop_fdre_C_Q) 0.141 -0.542 r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/Q + net (fo=8, routed) 0.354 -0.188 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/_zz_ram_port1_reg[49][1] + SLICE_X63Y97 r u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/ar_id_reg[1]_i_1/I5 + SLICE_X63Y97 LUT6 (Prop_lut6_I5_O) 0.045 -0.143 r u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/ar_id_reg[1]_i_1/O + net (fo=2, routed) 0.000 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/I172[3] + SLICE_X63Y97 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism 0.040 -0.343 + SLICE_X63Y97 FDRE (Hold_fdre_C_D) 0.092 -0.251 u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1] + ------------------------------------------------------------------- + required time 0.251 + arrival time -0.143 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.540ns (logic 0.186ns (34.444%) route 0.354ns (65.556%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.340ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.683ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.165 -0.683 + SLICE_X71Y100 FDRE 0.000 -0.683 r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C + SLICE_X71Y100 FDRE (Prop_fdre_C_Q) 0.141 -0.542 f u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/Q + net (fo=8, routed) 0.354 -0.188 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/_zz_ram_port1_reg[49][1] + SLICE_X63Y97 f u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/ar_id_reg[1]_i_1/I5 + SLICE_X63Y97 LUT6 (Prop_lut6_I5_O) 0.045 -0.143 f u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/ar_id_reg[1]_i_1/O + net (fo=2, routed) 0.000 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/I172[3] + SLICE_X63Y97 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism 0.040 -0.343 + SLICE_X63Y97 FDRE (Hold_fdre_C_D) 0.092 -0.251 u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1] + ------------------------------------------------------------------- + required time 0.251 + arrival time -0.143 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.110ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.478ns (logic 0.292ns (61.119%) route 0.186ns (38.881%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[0] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[1]) + 0.106 -0.226 r u_axi_uart_controller/uart0/regs/M_next_carry/O[1] + net (fo=1, routed) 0.000 -0.226 u_axi_uart_controller/uart0/regs/M_next[1] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[1] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.226 + ------------------------------------------------------------------- + slack 0.110 + +Slack (MET) : 0.110ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.478ns (logic 0.292ns (61.119%) route 0.186ns (38.881%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.144 -0.704 + SLICE_X82Y130 FDRE 0.000 -0.704 r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 f u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 f u_axi_uart_controller/uart0/regs/M_next_carry/S[0] + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[1]) + 0.106 -0.226 r u_axi_uart_controller/uart0/regs/M_next_carry/O[1] + net (fo=1, routed) 0.000 -0.226 u_axi_uart_controller/uart0/regs/M_next[1] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.466 -0.481 + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[1] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.226 + ------------------------------------------------------------------- + slack 0.110 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[7] + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.374 + clock pessimism 0.040 -0.333 + RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.040 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[7] + RAMB18_X7Y40 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.374 + clock pessimism 0.040 -0.333 + RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.040 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[7] + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.374 + clock pessimism 0.040 -0.333 + RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.040 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[7] + RAMB18_X7Y41 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.374 + clock pessimism 0.040 -0.333 + RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.040 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) + Logic Levels: 0 + Clock Path Skew: 0.058ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.303ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): 0.214ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/Q[6] + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.645 -0.303 + clock pessimism -0.214 -0.517 + RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg + ------------------------------------------------------------------- + required time 0.334 + arrival time -0.223 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) + Logic Levels: 0 + Clock Path Skew: 0.058ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.303ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): 0.214ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/Q[6] + RAMB18_X7Y39 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.645 -0.303 + clock pessimism -0.214 -0.517 + RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg + ------------------------------------------------------------------- + required time 0.334 + arrival time -0.223 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) + Logic Levels: 0 + Clock Path Skew: 0.058ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.303ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): 0.214ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/Q[6] + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.645 -0.303 + clock pessimism -0.214 -0.517 + RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg + ------------------------------------------------------------------- + required time 0.334 + arrival time -0.223 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) + Logic Levels: 0 + Clock Path Skew: 0.058ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.303ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): 0.214ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/Q[6] + RAMB18_X7Y38 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.645 -0.303 + clock pessimism -0.214 -0.517 + RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg + ------------------------------------------------------------------- + required time 0.334 + arrival time -0.223 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X115Y95 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C + SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[19] + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.373 + clock pessimism -0.229 -0.602 + SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.078 -0.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19] + ------------------------------------------------------------------- + required time 0.524 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.119 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X115Y95 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C + SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[19] + SLICE_X115Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.373 + clock pessimism -0.229 -0.602 + SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.078 -0.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19] + ------------------------------------------------------------------- + required time 0.524 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.119 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.301ns (logic 0.141ns (46.859%) route 0.160ns (53.141%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + SLICE_X57Y91 FDRE 0.000 -0.610 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C + SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/Q + net (fo=1, routed) 0.160 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIC0 + SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism -0.192 -0.573 + SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.429 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC + ------------------------------------------------------------------- + required time 0.429 + arrival time -0.309 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.301ns (logic 0.141ns (46.859%) route 0.160ns (53.141%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + SLICE_X57Y91 FDRE 0.000 -0.610 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C + SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/Q + net (fo=1, routed) 0.160 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIC0 + SLICE_X52Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism -0.192 -0.573 + SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.429 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC + ------------------------------------------------------------------- + required time 0.429 + arrival time -0.309 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.410ns (logic 0.186ns (45.405%) route 0.224ns (54.595%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.198ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.442ns + Source Clock Delay (SCD): -0.600ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.248 -0.600 + SLICE_X118Y99 FDCE 0.000 -0.600 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C + SLICE_X118Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.459 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/Q + net (fo=29, routed) 0.224 -0.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0[0] + SLICE_X114Y100 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/I1 + SLICE_X114Y100 LUT6 (Prop_lut6_I1_O) 0.045 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/O + net (fo=1, routed) 0.000 -0.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_next0[5] + SLICE_X114Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.505 -0.442 + clock pessimism 0.040 -0.402 + SLICE_X114Y100 FDCE (Hold_fdce_C_D) 0.091 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5] + ------------------------------------------------------------------- + required time 0.311 + arrival time -0.191 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.410ns (logic 0.186ns (45.405%) route 0.224ns (54.595%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.198ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.442ns + Source Clock Delay (SCD): -0.600ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.248 -0.600 + SLICE_X118Y99 FDCE 0.000 -0.600 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C + SLICE_X118Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.459 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/Q + net (fo=29, routed) 0.224 -0.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0[0] + SLICE_X114Y100 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/I1 + SLICE_X114Y100 LUT6 (Prop_lut6_I1_O) 0.045 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/O + net (fo=1, routed) 0.000 -0.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_next0[5] + SLICE_X114Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.505 -0.442 + clock pessimism 0.040 -0.402 + SLICE_X114Y100 FDCE (Hold_fdce_C_D) 0.091 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5] + ------------------------------------------------------------------- + required time 0.311 + arrival time -0.191 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.410ns (logic 0.186ns (45.405%) route 0.224ns (54.595%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.198ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.442ns + Source Clock Delay (SCD): -0.600ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.248 -0.600 + SLICE_X118Y99 FDCE 0.000 -0.600 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C + SLICE_X118Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.459 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/Q + net (fo=29, routed) 0.224 -0.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0[0] + SLICE_X114Y100 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/I1 + SLICE_X114Y100 LUT6 (Prop_lut6_I1_O) 0.045 -0.191 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/O + net (fo=1, routed) 0.000 -0.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_next0[5] + SLICE_X114Y100 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.505 -0.442 + clock pessimism 0.040 -0.402 + SLICE_X114Y100 FDCE (Hold_fdce_C_D) 0.091 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5] + ------------------------------------------------------------------- + required time 0.311 + arrival time -0.191 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.410ns (logic 0.186ns (45.405%) route 0.224ns (54.595%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.198ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.442ns + Source Clock Delay (SCD): -0.600ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.248 -0.600 + SLICE_X118Y99 FDCE 0.000 -0.600 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C + SLICE_X118Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.459 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/Q + net (fo=29, routed) 0.224 -0.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0[0] + SLICE_X114Y100 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/I1 + SLICE_X114Y100 LUT6 (Prop_lut6_I1_O) 0.045 -0.191 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/O + net (fo=1, routed) 0.000 -0.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_next0[5] + SLICE_X114Y100 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.505 -0.442 + clock pessimism 0.040 -0.402 + SLICE_X114Y100 FDCE (Hold_fdce_C_D) 0.091 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5] + ------------------------------------------------------------------- + required time 0.311 + arrival time -0.191 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.183 -0.665 + SLICE_X138Y100 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q + net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[4] + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.644 -0.304 + clock pessimism 0.040 -0.263 + RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.040 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.183 -0.665 + SLICE_X138Y100 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q + net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[4] + RAMB18_X7Y39 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.644 -0.304 + clock pessimism 0.040 -0.263 + RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.040 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.183 -0.665 + SLICE_X138Y100 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q + net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[4] + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.644 -0.304 + clock pessimism 0.040 -0.263 + RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.040 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.183 -0.665 + SLICE_X138Y100 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q + net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[4] + RAMB18_X7Y38 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.644 -0.304 + clock pessimism 0.040 -0.263 + RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.040 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.121ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X115Y95 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C + SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[18] + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.373 + clock pessimism -0.229 -0.602 + SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.076 -0.526 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18] + ------------------------------------------------------------------- + required time 0.526 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.121 + +Slack (MET) : 0.121ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X115Y95 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C + SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[18] + SLICE_X115Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.373 + clock pessimism -0.229 -0.602 + SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.076 -0.526 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18] + ------------------------------------------------------------------- + required time 0.526 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.121 + +Slack (MET) : 0.121ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.138 -0.711 + SLICE_X85Y171 FDCE 0.000 -0.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C + SLICE_X85Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/Q + net (fo=14, routed) 0.287 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[12] + SLICE_X81Y173 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.457 -0.490 + clock pessimism 0.040 -0.450 + SLICE_X81Y173 FDCE (Hold_fdce_C_D) 0.055 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12] + ------------------------------------------------------------------- + required time 0.395 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.112 + +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.928%) route 0.287ns (67.072%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.490ns + Source Clock Delay (SCD): -0.711ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q + net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[1] + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.374 + clock pessimism 0.040 -0.333 + RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.029 + ------------------------------------------------------------------- + slack 0.121 + +Slack (MET) : 0.121ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.138 -0.711 + SLICE_X85Y171 FDCE 0.000 -0.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C + SLICE_X85Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/Q + net (fo=14, routed) 0.287 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[12] + SLICE_X81Y173 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.457 -0.490 + clock pessimism 0.040 -0.450 + SLICE_X81Y173 FDCE (Hold_fdce_C_D) 0.055 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12] + ------------------------------------------------------------------- + required time 0.395 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.112 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1 + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1 + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.114ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.488ns (logic 0.231ns (47.314%) route 0.257ns (52.686%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.399ns + Source Clock Delay (SCD): -0.629ns + Clock Pessimism Removal (CPR): -0.037ns +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q + net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[1] + RAMB18_X7Y40 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.374 + clock pessimism 0.040 -0.333 + RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.029 + ------------------------------------------------------------------- + slack 0.121 + +Slack (MET) : 0.121ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q + net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[1] + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.374 + clock pessimism 0.040 -0.333 + RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.029 + ------------------------------------------------------------------- + slack 0.121 + +Slack (MET) : 0.121ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.273 -0.575 + SLICE_X140Y97 FDCE 0.000 -0.575 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q + net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[1] + RAMB18_X7Y41 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.374 + clock pessimism 0.040 -0.333 + RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.029 + ------------------------------------------------------------------- + slack 0.121 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1 + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1 + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1 + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1 + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1 + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1 + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1 + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.618 + SLICE_X67Y88 FDCE 0.000 -0.618 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1 + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.236 -0.612 + SLICE_X59Y91 FDCE 0.000 -0.612 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + SLICE_X59Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q + net (fo=1, routed) 0.056 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0] + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.229 -0.612 + SLICE_X59Y91 FDCE (Hold_fdce_C_D) 0.075 -0.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.537 + arrival time -0.415 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.236 -0.612 + SLICE_X59Y91 FDCE 0.000 -0.612 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + SLICE_X59Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.471 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q + net (fo=1, routed) 0.056 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0] + SLICE_X59Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.229 -0.612 + SLICE_X59Y91 FDCE (Hold_fdce_C_D) 0.075 -0.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.537 + arrival time -0.415 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X67Y95 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q + net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[1] + SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.229 -0.616 + SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.075 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.541 + arrival time -0.419 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.232 -0.616 + SLICE_X67Y95 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q + net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[1] + SLICE_X67Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.229 -0.616 + SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.075 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.541 + arrival time -0.419 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.617ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.231 -0.617 + SLICE_X69Y91 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q + net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[2] + SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + clock pessimism -0.229 -0.617 + SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.542 + arrival time -0.420 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.617ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.231 -0.617 + SLICE_X69Y91 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q + net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[2] + SLICE_X69Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + clock pessimism -0.229 -0.617 + SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.542 + arrival time -0.420 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.454ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): 0.226ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/Q + net (fo=1, routed) 0.056 -0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0 + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.493 -0.454 + clock pessimism -0.226 -0.680 + SLICE_X65Y102 FDCE (Hold_fdce_C_D) 0.075 -0.605 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg + ------------------------------------------------------------------- + required time 0.605 + arrival time -0.483 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.454ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): 0.226ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/Q + net (fo=1, routed) 0.056 -0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0 + SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.493 -0.454 + clock pessimism -0.226 -0.680 + SLICE_X65Y102 FDCE (Hold_fdce_C_D) 0.075 -0.605 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg + ------------------------------------------------------------------- + required time 0.605 + arrival time -0.483 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.124ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.200ns (logic 0.141ns (70.589%) route 0.059ns (29.411%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.226ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X50Y83 FDCE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q + net (fo=1, routed) 0.059 -0.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[2] + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.226 -0.613 + SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.076 -0.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.537 + arrival time -0.414 + ------------------------------------------------------------------- + slack 0.124 + +Slack (MET) : 0.124ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.200ns (logic 0.141ns (70.589%) route 0.059ns (29.411%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.226ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X50Y83 FDCE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q + net (fo=1, routed) 0.059 -0.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[2] + SLICE_X50Y83 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.226 -0.613 + SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.076 -0.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.537 + arrival time -0.414 + ------------------------------------------------------------------- + slack 0.124 + +Slack (MET) : 0.125ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.577ns (logic 0.231ns (40.066%) route 0.346ns (59.934%)) + Logic Levels: 2 (LUT3=1 LUT6=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.290ns + Source Clock Delay (SCD): -0.598ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.250 -0.598 + SLICE_X135Y50 FDCE 0.000 -0.598 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/C + SLICE_X135Y50 FDCE (Prop_fdce_C_Q) 0.141 -0.457 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/Q + net (fo=2, routed) 0.126 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/data31[9] + SLICE_X135Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[753]_i_2/I0 + SLICE_X135Y48 LUT6 (Prop_lut6_I0_O) 0.045 -0.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[753]_i_2/O + net (fo=1, routed) 0.220 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[493] + SLICE_X135Y48 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[753]_i_1/I1 + SLICE_X135Y48 LUT3 (Prop_lut3_I1_O) 0.045 -0.022 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[753]_i_1/O + net (fo=1, routed) 0.000 -0.022 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[753] + SLICE_X135Y48 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.657 -0.290 + clock pessimism 0.037 -0.253 + SLICE_X135Y48 FDCE (Hold_fdce_C_D) 0.107 -0.146 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753] + ------------------------------------------------------------------- + required time 0.146 + arrival time -0.022 + ------------------------------------------------------------------- + slack 0.125 + +Slack (MET) : 0.125ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.577ns (logic 0.231ns (40.066%) route 0.346ns (59.934%)) + Logic Levels: 2 (LUT3=1 LUT6=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.290ns + Source Clock Delay (SCD): -0.598ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.250 -0.598 + SLICE_X135Y50 FDCE 0.000 -0.598 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/C + SLICE_X135Y50 FDCE (Prop_fdce_C_Q) 0.141 -0.457 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/Q + net (fo=2, routed) 0.126 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/data31[9] + SLICE_X135Y48 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[753]_i_2/I0 + SLICE_X135Y48 LUT6 (Prop_lut6_I0_O) 0.045 -0.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[753]_i_2/O + net (fo=1, routed) 0.220 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[493] + SLICE_X135Y48 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[753]_i_1/I1 + SLICE_X135Y48 LUT3 (Prop_lut3_I1_O) 0.045 -0.022 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[753]_i_1/O + net (fo=1, routed) 0.000 -0.022 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[753] + SLICE_X135Y48 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.657 -0.290 + clock pessimism 0.037 -0.253 + SLICE_X135Y48 FDCE (Hold_fdce_C_D) 0.107 -0.146 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753] + ------------------------------------------------------------------- + required time 0.146 + arrival time -0.022 + ------------------------------------------------------------------- + slack 0.125 + +Slack (MET) : 0.125ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.512ns (logic 0.164ns (32.024%) route 0.348ns (67.976%)) + Logic Levels: 0 + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.179 -0.669 + SLICE_X108Y100 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/C + SLICE_X108Y100 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/Q + net (fo=1, routed) 0.348 -0.157 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[15] + SLICE_X103Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X103Y99 FDCE (Hold_fdce_C_D) 0.057 -0.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15] + ------------------------------------------------------------------- + required time 0.282 + arrival time -0.157 + ------------------------------------------------------------------- + slack 0.125 + +Slack (MET) : 0.125ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.512ns (logic 0.164ns (32.024%) route 0.348ns (67.976%)) + Logic Levels: 0 + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.179 -0.669 + SLICE_X108Y100 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/C + SLICE_X108Y100 FDCE (Prop_fdce_C_Q) 0.164 -0.505 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/Q + net (fo=1, routed) 0.348 -0.157 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[15] + SLICE_X103Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X103Y99 FDCE (Hold_fdce_C_D) 0.057 -0.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15] + ------------------------------------------------------------------- + required time 0.282 + arrival time -0.157 + ------------------------------------------------------------------- + slack 0.125 + +Slack (MET) : 0.126ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.236 -0.612 + SLICE_X59Y91 FDCE 0.000 -0.612 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + SLICE_X59Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q + net (fo=1, routed) 0.056 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2] + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.229 -0.612 + SLICE_X59Y91 FDCE (Hold_fdce_C_D) 0.071 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.541 + arrival time -0.415 + ------------------------------------------------------------------- + slack 0.126 + +Slack (MET) : 0.126ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.236 -0.612 + SLICE_X59Y91 FDCE 0.000 -0.612 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + SLICE_X59Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.471 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q + net (fo=1, routed) 0.056 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2] + SLICE_X59Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.229 -0.612 + SLICE_X59Y91 FDCE (Hold_fdce_C_D) 0.071 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.541 + arrival time -0.415 + ------------------------------------------------------------------- + slack 0.126 + +Slack (MET) : 0.126ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X115Y95 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/C + SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[17] + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.373 + clock pessimism -0.229 -0.602 + SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.071 -0.531 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17] + ------------------------------------------------------------------- + required time 0.531 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.126 + +Slack (MET) : 0.126ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X115Y95 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/C + SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[17] + SLICE_X115Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.373 + clock pessimism -0.229 -0.602 + SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.071 -0.531 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17] + ------------------------------------------------------------------- + required time 0.531 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.126 + +Slack (MET) : 0.126ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.603ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.245 -0.603 + SLICE_X115Y91 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/C + SLICE_X115Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/Q + net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[1] + SLICE_X115Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.573 -0.374 + clock pessimism -0.229 -0.603 + SLICE_X115Y91 FDCE (Hold_fdce_C_D) 0.071 -0.532 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1] + ------------------------------------------------------------------- + required time 0.532 + arrival time -0.406 + ------------------------------------------------------------------- + slack 0.126 + +Slack (MET) : 0.126ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.603ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.245 -0.603 + SLICE_X115Y91 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/C + SLICE_X115Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.462 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/Q + net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[1] + SLICE_X115Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.573 -0.374 + clock pessimism -0.229 -0.603 + SLICE_X115Y91 FDCE (Hold_fdce_C_D) 0.071 -0.532 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1] + ------------------------------------------------------------------- + required time 0.532 + arrival time -0.406 + ------------------------------------------------------------------- + slack 0.126 + +Slack (MET) : 0.126ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X115Y96 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/C + SLICE_X115Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[21] + SLICE_X115Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.373 + clock pessimism -0.229 -0.602 + SLICE_X115Y96 FDCE (Hold_fdce_C_D) 0.071 -0.531 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21] + ------------------------------------------------------------------- + required time 0.531 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.126 + +Slack (MET) : 0.126ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X115Y96 FDCE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/C + SLICE_X115Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.461 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[21] + SLICE_X115Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.574 -0.373 + clock pessimism -0.229 -0.602 + SLICE_X115Y96 FDCE (Hold_fdce_C_D) 0.071 -0.531 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21] + ------------------------------------------------------------------- + required time 0.531 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.126 + +Slack (MET) : 0.127ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.711ns (logic 0.141ns (19.823%) route 0.570ns (80.177%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.183 -0.665 + SLICE_X137Y102 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C + SLICE_X137Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/Q + net (fo=10, routed) 0.570 0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[1] + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.644 -0.304 + clock pessimism 0.040 -0.263 + RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.046 + ------------------------------------------------------------------- + slack 0.127 + +Slack (MET) : 0.127ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.711ns (logic 0.141ns (19.823%) route 0.570ns (80.177%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.183 -0.665 + SLICE_X137Y102 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C + SLICE_X137Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.524 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/Q + net (fo=10, routed) 0.570 0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[1] + RAMB18_X7Y39 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.644 -0.304 + clock pessimism 0.040 -0.263 + RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.046 + ------------------------------------------------------------------- + slack 0.127 + +Slack (MET) : 0.127ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.711ns (logic 0.141ns (19.823%) route 0.570ns (80.177%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.183 -0.665 + SLICE_X137Y102 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C + SLICE_X137Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/Q + net (fo=10, routed) 0.570 0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[1] + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.644 -0.304 + clock pessimism 0.040 -0.263 + RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.046 + ------------------------------------------------------------------- + slack 0.127 + +Slack (MET) : 0.127ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.711ns (logic 0.141ns (19.823%) route 0.570ns (80.177%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.183 -0.665 + SLICE_X137Y102 FDCE 0.000 -0.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C + SLICE_X137Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.524 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/Q + net (fo=10, routed) 0.570 0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[1] + RAMB18_X7Y38 RAMB18E1 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.644 -0.304 + clock pessimism 0.040 -0.263 + RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.046 + ------------------------------------------------------------------- + slack 0.127 + +Slack (MET) : 0.128ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.226ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X50Y83 FDCE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q + net (fo=1, routed) 0.058 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[1] + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.226 -0.613 + SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.071 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.542 + arrival time -0.415 + ------------------------------------------------------------------- + slack 0.128 + +Slack (MET) : 0.128ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.226ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X50Y83 FDCE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q + net (fo=1, routed) 0.058 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[1] + SLICE_X50Y83 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.226 -0.613 + SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.071 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.542 + arrival time -0.415 + ------------------------------------------------------------------- + slack 0.128 + +Slack (MET) : 0.129ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.255ns (logic 0.141ns (55.379%) route 0.114ns (44.621%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.443ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.178 -0.670 + SLICE_X123Y110 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/C + SLICE_X123Y110 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/Q + net (fo=7, routed) 0.114 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r[3] + SLICE_X120Y109 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.504 -0.443 + clock pessimism -0.210 -0.653 + SLICE_X120Y109 SRL16E (Hold_srl16e_CLK_D) + 0.109 -0.544 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.544 + arrival time -0.415 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.255ns (logic 0.141ns (55.379%) route 0.114ns (44.621%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.443ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.178 -0.670 + SLICE_X123Y110 FDCE 0.000 -0.670 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/C + SLICE_X123Y110 FDCE (Prop_fdce_C_Q) 0.141 -0.529 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/Q + net (fo=7, routed) 0.114 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r[3] + SLICE_X120Y109 SRL16E f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.504 -0.443 + clock pessimism -0.210 -0.653 + SLICE_X120Y109 SRL16E (Hold_srl16e_CLK_D) + 0.109 -0.544 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.544 + arrival time -0.415 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.130ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.282ns (logic 0.141ns (49.987%) route 0.141ns (50.013%)) + Logic Levels: 0 + Clock Path Skew: 0.035ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.179 -0.669 + SLICE_X134Y112 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/C + SLICE_X134Y112 FDCE (Prop_fdce_C_Q) 0.141 -0.528 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/Q + net (fo=5, routed) 0.141 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[0] + SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.502 -0.445 + clock pessimism -0.189 -0.634 + SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) + 0.117 -0.517 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.517 + arrival time -0.387 + ------------------------------------------------------------------- + slack 0.130 + +Slack (MET) : 0.130ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.282ns (logic 0.141ns (49.987%) route 0.141ns (50.013%)) + Logic Levels: 0 + Clock Path Skew: 0.035ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.179 -0.669 + SLICE_X134Y112 FDCE 0.000 -0.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/C + SLICE_X134Y112 FDCE (Prop_fdce_C_Q) 0.141 -0.528 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/Q + net (fo=5, routed) 0.141 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[0] + SLICE_X136Y113 SRL16E f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.502 -0.445 + clock pessimism -0.189 -0.634 + SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) + 0.117 -0.517 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.517 + arrival time -0.387 + ------------------------------------------------------------------- + slack 0.130 + +Slack (MET) : 0.130ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/I + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.313ns (logic 0.141ns (45.032%) route 0.172ns (54.968%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + SLICE_X57Y91 FDRE 0.000 -0.610 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/C + SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/Q + net (fo=1, routed) 0.172 -0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIB0 + SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism -0.192 -0.573 + SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.427 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB + ------------------------------------------------------------------- + required time 0.427 + arrival time -0.297 + ------------------------------------------------------------------- + slack 0.130 + +Slack (MET) : 0.130ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/I + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.313ns (logic 0.141ns (45.032%) route 0.172ns (54.968%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.238 -0.610 + SLICE_X57Y91 FDRE 0.000 -0.610 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/C + SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/Q + net (fo=1, routed) 0.172 -0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIB0 + SLICE_X52Y90 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism -0.192 -0.573 + SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.427 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB + ------------------------------------------------------------------- + required time 0.427 + arrival time -0.297 + ------------------------------------------------------------------- + slack 0.130 + +Slack (MET) : 0.130ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.544ns (logic 0.141ns (25.911%) route 0.403ns (74.090%)) + Logic Levels: 0 + Clock Path Skew: 0.343ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.371ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y102 FDCE 0.000 -0.674 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/C + SLICE_X103Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.533 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/Q + net (fo=1, routed) 0.403 -0.130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0_n_0 + SLICE_X117Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.576 -0.371 + clock pessimism 0.040 -0.331 + SLICE_X117Y99 FDCE (Hold_fdce_C_D) 0.071 -0.260 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1 + ------------------------------------------------------------------- + required time 0.260 + arrival time -0.130 + ------------------------------------------------------------------- + slack 0.130 + +Slack (MET) : 0.130ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.544ns (logic 0.141ns (25.911%) route 0.403ns (74.090%)) + Logic Levels: 0 + Clock Path Skew: 0.343ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.371ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.174 -0.674 + SLICE_X103Y102 FDCE 0.000 -0.674 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/C + SLICE_X103Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.533 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/Q + net (fo=1, routed) 0.403 -0.130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0_n_0 + SLICE_X117Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.576 -0.371 + clock pessimism 0.040 -0.331 + SLICE_X117Y99 FDCE (Hold_fdce_C_D) 0.071 -0.260 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1 + ------------------------------------------------------------------- + required time 0.260 + arrival time -0.130 + ------------------------------------------------------------------- + slack 0.130 + +Slack (MET) : 0.131ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.226ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X50Y83 FDCE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q + net (fo=1, routed) 0.065 -0.407 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[0] + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.226 -0.613 + SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.075 -0.538 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.538 + arrival time -0.407 + ------------------------------------------------------------------- + slack 0.131 + +Slack (MET) : 0.131ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.226ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X50Y83 FDCE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q + net (fo=1, routed) 0.065 -0.407 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[0] + SLICE_X50Y83 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.226 -0.613 + SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.075 -0.538 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.538 + arrival time -0.407 + ------------------------------------------------------------------- + slack 0.131 + +Slack (MET) : 0.131ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.382ns + Source Clock Delay (SCD): -0.611ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.237 -0.611 + SLICE_X54Y88 FDCE 0.000 -0.611 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + SLICE_X54Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.470 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q + net (fo=1, routed) 0.065 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[1] + SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.565 -0.382 + clock pessimism -0.229 -0.611 + SLICE_X54Y88 FDCE (Hold_fdce_C_D) 0.075 -0.536 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.536 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.131 + +Slack (MET) : 0.131ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.382ns + Source Clock Delay (SCD): -0.611ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.237 -0.611 + SLICE_X54Y88 FDCE 0.000 -0.611 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + SLICE_X54Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.470 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q + net (fo=1, routed) 0.065 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[1] + SLICE_X54Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.565 -0.382 + clock pessimism -0.229 -0.611 + SLICE_X54Y88 FDCE (Hold_fdce_C_D) 0.075 -0.536 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.536 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.131 + +Slack (MET) : 0.132ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.237ns (logic 0.186ns (78.504%) route 0.051ns (21.496%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.215ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X54Y85 FDRE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C + SLICE_X54Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/Q + net (fo=1, routed) 0.051 -0.421 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_burst_reg[1]_0[14] + SLICE_X55Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1/I0 + SLICE_X55Y85 LUT4 (Prop_lut4_I0_O) 0.045 -0.376 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1/O + net (fo=1, routed) 0.000 -0.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1_n_0 + SLICE_X55Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + clock pessimism -0.215 -0.600 + SLICE_X55Y85 FDRE (Hold_fdre_C_D) 0.092 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14] + ------------------------------------------------------------------- + required time 0.508 + arrival time -0.376 + ------------------------------------------------------------------- + slack 0.132 + +Slack (MET) : 0.132ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.237ns (logic 0.186ns (78.504%) route 0.051ns (21.496%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.215ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X54Y85 FDRE 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C + SLICE_X54Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.472 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/Q + net (fo=1, routed) 0.051 -0.421 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_burst_reg[1]_0[14] + SLICE_X55Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1/I0 + SLICE_X55Y85 LUT4 (Prop_lut4_I0_O) 0.045 -0.376 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1/O + net (fo=1, routed) 0.000 -0.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1_n_0 + SLICE_X55Y85 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + clock pessimism -0.215 -0.600 + SLICE_X55Y85 FDRE (Hold_fdre_C_D) 0.092 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14] + ------------------------------------------------------------------- + required time 0.508 + arrival time -0.376 + ------------------------------------------------------------------- + slack 0.132 + +Slack (MET) : 0.133ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.530ns (logic 0.141ns (26.621%) route 0.389ns (73.379%)) + Logic Levels: 0 + Clock Path Skew: 0.338ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.370ns + Source Clock Delay (SCD): -0.668ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.180 -0.668 + SLICE_X122Y105 FDCE 0.000 -0.668 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/C + SLICE_X122Y105 FDCE (Prop_fdce_C_Q) 0.141 -0.527 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/Q + net (fo=14, routed) 0.389 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[23]_1[16] + SLICE_X128Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.577 -0.370 + clock pessimism 0.040 -0.330 + SLICE_X128Y99 FDCE (Hold_fdce_C_D) 0.059 -0.271 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16] + ------------------------------------------------------------------- + required time 0.271 + arrival time -0.138 + ------------------------------------------------------------------- + slack 0.133 + +Slack (MET) : 0.133ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.530ns (logic 0.141ns (26.621%) route 0.389ns (73.379%)) + Logic Levels: 0 + Clock Path Skew: 0.338ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.370ns + Source Clock Delay (SCD): -0.668ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.180 -0.668 + SLICE_X122Y105 FDCE 0.000 -0.668 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/C + SLICE_X122Y105 FDCE (Prop_fdce_C_Q) 0.141 -0.527 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/Q + net (fo=14, routed) 0.389 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[23]_1[16] + SLICE_X128Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.577 -0.370 + clock pessimism 0.040 -0.330 + SLICE_X128Y99 FDCE (Hold_fdce_C_D) 0.059 -0.271 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16] + ------------------------------------------------------------------- + required time 0.271 + arrival time -0.138 + ------------------------------------------------------------------- + slack 0.133 + +Slack (MET) : 0.573ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.019ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.229 -0.619 + SLICE_X67Y87 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.213 -0.600 + SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.667 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.573 + +Slack (MET) : 0.573ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.019ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.229 -0.619 + SLICE_X67Y87 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.213 -0.600 + SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.667 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.573 + +Slack (MET) : 0.573ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.019ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.229 -0.619 + SLICE_X67Y87 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism -0.213 -0.600 + SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.667 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.573 + +Slack (MET) : 0.658ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.923ns (logic 0.227ns (24.583%) route 0.696ns (75.417%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.332ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.414 0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X72Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.559 -0.388 + clock pessimism 0.040 -0.348 + SLICE_X72Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.415 + arrival time 0.243 + ------------------------------------------------------------------- + slack 0.658 + +Slack (MET) : 0.681ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.596ns (logic 0.246ns (41.259%) route 0.350ns (58.741%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.293 -0.089 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X93Y122 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.478 -0.469 + clock pessimism -0.209 -0.678 + SLICE_X93Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.770 + arrival time -0.089 + ------------------------------------------------------------------- + slack 0.681 + +Slack (MET) : 0.692ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.480 -0.467 + clock pessimism -0.189 -0.656 + SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.723 + arrival time -0.031 + ------------------------------------------------------------------- + slack 0.692 + +Slack (MET) : 0.692ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.480 -0.467 + clock pessimism -0.189 -0.656 + SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.723 + arrival time -0.031 + ------------------------------------------------------------------- + slack 0.692 + +Slack (MET) : 0.692ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.480 -0.467 + clock pessimism -0.189 -0.656 + SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.723 + arrival time -0.031 + ------------------------------------------------------------------- + slack 0.692 + +Slack (MET) : 0.692ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.480 -0.467 + clock pessimism -0.189 -0.656 + SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.723 + arrival time -0.031 + ------------------------------------------------------------------- + slack 0.692 + +Slack (MET) : 0.750ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.478 -0.469 + clock pessimism -0.209 -0.678 + SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 0.770 + arrival time -0.020 + ------------------------------------------------------------------- + slack 0.750 + +Slack (MET) : 0.750ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.478 -0.469 + clock pessimism -0.209 -0.678 + SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.770 + arrival time -0.020 + ------------------------------------------------------------------- + slack 0.750 + +Slack (MET) : 0.750ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.478 -0.469 + clock pessimism -0.209 -0.678 + SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.770 + arrival time -0.020 + ------------------------------------------------------------------- + slack 0.750 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.486 -0.461 + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.486 -0.461 + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.486 -0.461 + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.486 -0.461 + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.486 -0.461 + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.796ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.557 -0.390 + clock pessimism 0.040 -0.350 + SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.417 + arrival time 0.379 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.796ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.557 -0.390 + clock pessimism 0.040 -0.350 + SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.417 + arrival time 0.379 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.796ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.557 -0.390 + clock pessimism 0.040 -0.350 + SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.417 + arrival time 0.379 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.796ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.557 -0.390 + clock pessimism 0.040 -0.350 + SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.417 + arrival time 0.379 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.479 -0.468 + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.479 -0.468 + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.479 -0.468 + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.479 -0.468 + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.479 -0.468 + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.479 -0.468 + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.807ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.556 -0.391 + clock pessimism 0.040 -0.351 + SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.418 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.807 + +Slack (MET) : 0.807ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.556 -0.391 + clock pessimism 0.040 -0.351 + SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.418 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.807 + +Slack (MET) : 0.807ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.556 -0.391 + clock pessimism 0.040 -0.351 + SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.418 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.807 + +Slack (MET) : 0.807ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.556 -0.391 + clock pessimism 0.040 -0.351 + SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.418 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.807 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.074 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.074 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.074 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.074 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.074 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.163 -0.685 + SLICE_X92Y115 FDCE 0.000 -0.685 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.489 -0.458 + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.074 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.832ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.556 -0.391 + clock pessimism 0.040 -0.351 + SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.443 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.832 + +Slack (MET) : 0.832ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.556 -0.391 + clock pessimism 0.040 -0.351 + SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.443 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.832 + +Slack (MET) : 0.832ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.556 -0.391 + clock pessimism 0.040 -0.351 + SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 0.443 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.832 + +Slack (MET) : 0.832ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.556 -0.391 + clock pessimism 0.040 -0.351 + SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.443 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.832 + +Slack (MET) : 0.837ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.812ns (logic 0.227ns (27.961%) route 0.585ns (72.039%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.192ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.219 -0.629 + SLICE_X83Y93 FDCE 0.000 -0.629 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C + SLICE_X83Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.501 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/Q + net (fo=118, routed) 0.257 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10_n_0 + SLICE_X85Y98 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/I0 + SLICE_X85Y98 LUT2 (Prop_lut2_I0_O) 0.103 -0.141 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/O + net (fo=1, routed) 0.000 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1_n_0 + SLICE_X85Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D +======= + 1.229 -0.619 + SLICE_X67Y87 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.445 0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X64Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.548 -0.399 + clock pessimism 0.037 -0.362 + SLICE_X85Y98 FDCE (Hold_fdce_C_D) 0.107 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360] + ------------------------------------------------------------------- + required time 0.255 + arrival time -0.141 + ------------------------------------------------------------------- + slack 0.114 + +Slack (MET) : 0.114ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.488ns (logic 0.231ns (47.314%) route 0.257ns (52.686%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.399ns + Source Clock Delay (SCD): -0.629ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.219 -0.629 + SLICE_X83Y93 FDCE 0.000 -0.629 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C + SLICE_X83Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.501 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/Q + net (fo=118, routed) 0.257 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10_n_0 + SLICE_X85Y98 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/I0 + SLICE_X85Y98 LUT2 (Prop_lut2_I0_O) 0.103 -0.141 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/O + net (fo=1, routed) 0.000 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1_n_0 + SLICE_X85Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.548 -0.399 + clock pessimism 0.037 -0.362 + SLICE_X85Y98 FDCE (Hold_fdce_C_D) 0.107 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360] + ------------------------------------------------------------------- + required time 0.255 + arrival time -0.141 + ------------------------------------------------------------------- + slack 0.114 + +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/confreg_int_edge_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.384 -0.465 + SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C + SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 r u_confreg/confreg_int_edge_reg[3]/Q + net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] + SLICE_X3Y50 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0 + SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O + net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 + SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism 0.037 -0.268 + SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] + ------------------------------------------------------------------- + required time 0.177 + arrival time -0.063 + ------------------------------------------------------------------- + slack 0.115 + +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/confreg_int_edge_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns +======= + 1.562 -0.385 + clock pessimism -0.192 -0.577 + SLICE_X64Y95 FDCE (Remov_fdce_C_CLR) -0.067 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.644 + arrival time 0.192 + ------------------------------------------------------------------- + slack 0.837 + +Slack (MET) : 0.871ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.822ns (logic 0.227ns (27.605%) route 0.595ns (72.395%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.043ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.384ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.192ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.384 -0.465 + SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C + SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 f u_confreg/confreg_int_edge_reg[3]/Q + net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] + SLICE_X3Y50 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0 + SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O + net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 + SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/D +======= + 1.229 -0.619 + SLICE_X67Y87 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.456 0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X65Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.642 -0.305 + clock pessimism 0.037 -0.268 + SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] + ------------------------------------------------------------------- + required time 0.177 + arrival time -0.063 + ------------------------------------------------------------------- + slack 0.115 + +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/confreg_int_edge_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.384 -0.465 + SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C + SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 r u_confreg/confreg_int_edge_reg[3]/Q + net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] + SLICE_X3Y50 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0 + SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O + net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 + SLICE_X3Y50 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism 0.037 -0.268 + SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] + ------------------------------------------------------------------- + required time 0.177 + arrival time -0.063 + ------------------------------------------------------------------- + slack 0.115 + +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/confreg_int_edge_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.384 -0.465 + SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C + SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 f u_confreg/confreg_int_edge_reg[3]/Q + net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] + SLICE_X3Y50 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0 + SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O + net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 + SLICE_X3Y50 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism 0.037 -0.268 + SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] + ------------------------------------------------------------------- + required time 0.177 + arrival time -0.063 + ------------------------------------------------------------------- + slack 0.115 + +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.387ns (logic 0.141ns (36.445%) route 0.246ns (63.555%)) + Logic Levels: 0 + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns +======= + 1.563 -0.384 + clock pessimism -0.192 -0.576 + SLICE_X65Y99 FDCE (Remov_fdce_C_CLR) -0.092 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.203 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.871ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.822ns (logic 0.227ns (27.605%) route 0.595ns (72.395%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.043ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.384ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.192ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.384 -0.465 + SLICE_X1Y49 FDCE 0.000 -0.465 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C + SLICE_X1Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/Q + net (fo=3, routed) 0.246 -0.078 u_confreg/u_int_ctrl/int_in_sync_d2[5] + SLICE_X3Y51 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D +======= + 1.229 -0.619 + SLICE_X67Y87 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.456 0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X65Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.642 -0.305 + clock pessimism 0.037 -0.268 + SLICE_X3Y51 FDCE (Hold_fdce_C_D) 0.075 -0.193 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] + ------------------------------------------------------------------- + required time 0.193 + arrival time -0.078 + ------------------------------------------------------------------- + slack 0.115 + +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.387ns (logic 0.141ns (36.445%) route 0.246ns (63.555%)) + Logic Levels: 0 + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.384 -0.465 + SLICE_X1Y49 FDCE 0.000 -0.465 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C + SLICE_X1Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/Q + net (fo=3, routed) 0.246 -0.078 u_confreg/u_int_ctrl/int_in_sync_d2[5] + SLICE_X3Y51 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism 0.037 -0.268 + SLICE_X3Y51 FDCE (Hold_fdce_C_D) 0.075 -0.193 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] + ------------------------------------------------------------------- + required time 0.193 + arrival time -0.078 + ------------------------------------------------------------------- + slack 0.115 + +Slack (MET) : 0.116ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.465ns (logic 0.141ns (30.326%) route 0.324ns (69.674%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.619 + SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/Q + net (fo=15, routed) 0.324 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[19] + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.072 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19] + ------------------------------------------------------------------- + required time 0.270 + arrival time -0.154 + ------------------------------------------------------------------- + slack 0.116 + +Slack (MET) : 0.116ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.465ns (logic 0.141ns (30.326%) route 0.324ns (69.674%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.619 + SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/Q + net (fo=15, routed) 0.324 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[19] + SLICE_X159Y140 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.072 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19] + ------------------------------------------------------------------- + required time 0.270 + arrival time -0.154 + ------------------------------------------------------------------- + slack 0.116 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C +======= + 1.563 -0.384 + clock pessimism -0.192 -0.576 + SLICE_X65Y99 FDCE (Remov_fdce_C_CLR) -0.092 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.203 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.884ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg + SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + clock pessimism 0.040 -0.345 + SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.437 + arrival time 0.447 + ------------------------------------------------------------------- + slack 0.884 + +Slack (MET) : 0.884ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg + SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + clock pessimism 0.040 -0.345 + SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.437 + arrival time 0.447 + ------------------------------------------------------------------- + slack 0.884 + +Slack (MET) : 0.884ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg + SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + clock pessimism 0.040 -0.345 + SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 0.437 + arrival time 0.447 + ------------------------------------------------------------------- + slack 0.884 + +Slack (MET) : 0.884ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X65Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg + SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + clock pessimism 0.040 -0.345 + SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.437 + arrival time 0.447 + ------------------------------------------------------------------- + slack 0.884 + +Slack (MET) : 0.906ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.080ns (logic 0.226ns (20.934%) route 0.854ns (79.066%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.683 0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.040 -0.347 + SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15] + ------------------------------------------------------------------- + required time 0.506 + arrival time 0.400 + ------------------------------------------------------------------- + slack 0.906 + +Slack (MET) : 0.906ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.080ns (logic 0.226ns (20.934%) route 0.854ns (79.066%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.683 0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.040 -0.347 + SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53] + ------------------------------------------------------------------- + required time 0.506 + arrival time 0.400 + ------------------------------------------------------------------- + slack 0.906 + +Slack (MET) : 0.912ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 +======= + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C +======= + 1.470 -0.477 + clock pessimism -0.189 -0.666 + SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.912 + +Slack (MET) : 0.912ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 +======= + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C +======= + 1.470 -0.477 + clock pessimism -0.189 -0.666 + SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.912 + +Slack (MET) : 0.912ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 +======= + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C +======= + 1.470 -0.477 + clock pessimism -0.189 -0.666 + SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.912 + +Slack (MET) : 0.912ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 +======= + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C +======= + 1.470 -0.477 + clock pessimism -0.189 -0.666 + SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.912 + +Slack (MET) : 0.919ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.023ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.486 -0.461 + clock pessimism -0.209 -0.670 + SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.737 + arrival time 0.182 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.919ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.023ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.486 -0.461 + clock pessimism -0.209 -0.670 + SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.737 + arrival time 0.182 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.919ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.023ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.486 -0.461 + clock pessimism -0.209 -0.670 + SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.737 + arrival time 0.182 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.919ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.023ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.486 -0.461 + clock pessimism -0.209 -0.670 + SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.737 + arrival time 0.182 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.927ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.452 + ------------------------------------------------------------------- + slack 0.927 + +Slack (MET) : 0.927ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.452 + ------------------------------------------------------------------- + slack 0.927 + +Slack (MET) : 0.927ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.452 + ------------------------------------------------------------------- + slack 0.927 + +Slack (MET) : 0.927ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.452 + ------------------------------------------------------------------- + slack 0.927 + +Slack (MET) : 0.931ns (arrival time - required time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.105ns (logic 0.206ns (18.647%) route 0.899ns (81.353%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] + SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 + SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.683 0.425 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.040 -0.347 + SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15] + ------------------------------------------------------------------- + required time 0.506 + arrival time 0.425 + ------------------------------------------------------------------- + slack 0.931 + +Slack (MET) : 0.931ns (arrival time - required time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.105ns (logic 0.206ns (18.647%) route 0.899ns (81.353%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] + SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 + SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.683 0.425 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.040 -0.347 + SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53] + ------------------------------------------------------------------- + required time 0.506 + arrival time 0.425 + ------------------------------------------------------------------- + slack 0.931 + +Slack (MET) : 0.931ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0] + ------------------------------------------------------------------- + required time 0.473 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.931 + +Slack (MET) : 0.931ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16] + ------------------------------------------------------------------- + required time 0.473 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.931 + +Slack (MET) : 0.931ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17] + ------------------------------------------------------------------- + required time 0.473 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.931 + +Slack (MET) : 0.931ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18] + ------------------------------------------------------------------- + required time 0.473 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.931 + +Slack (MET) : 0.931ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19] + ------------------------------------------------------------------- + required time 0.473 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.931 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.460 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.460 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.460 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.460 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.936ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.113ns (logic 0.226ns (20.298%) route 0.887ns (79.702%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.384ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.717 0.433 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X99Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.563 -0.384 + clock pessimism 0.040 -0.344 + SLICE_X99Y96 FDCE (Remov_fdce_C_CLR) -0.159 -0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep + ------------------------------------------------------------------- + required time 0.503 + arrival time 0.433 + ------------------------------------------------------------------- + slack 0.936 + +Slack (MET) : 0.936ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.113ns (logic 0.226ns (20.298%) route 0.887ns (79.702%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.384ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.717 0.433 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X99Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.563 -0.384 + clock pessimism 0.040 -0.344 + SLICE_X99Y96 FDCE (Remov_fdce_C_CLR) -0.159 -0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2 + ------------------------------------------------------------------- + required time 0.503 + arrival time 0.433 + ------------------------------------------------------------------- + slack 0.936 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 +======= + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C +======= + 1.470 -0.477 + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 +======= + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C +======= + 1.470 -0.477 + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 +======= + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C +======= + 1.470 -0.477 + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 +======= + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C +======= + 1.470 -0.477 + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 +======= + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C +======= + 1.470 -0.477 + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMS32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 +======= + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C +======= + 1.470 -0.477 + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 +======= + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C +======= + 1.470 -0.477 + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency +<<<<<<< Updated upstream + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMS32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 +======= + 1.155 -0.693 + SLICE_X92Y123 FDCE 0.000 -0.693 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency +<<<<<<< Updated upstream + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.118ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.475ns (logic 0.209ns (44.013%) route 0.266ns (55.987%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.420ns + Source Clock Delay (SCD): -0.640ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.208 -0.640 + SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q + net (fo=127, routed) 0.266 -0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 + SLICE_X151Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/I1 + SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.165 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/O + net (fo=1, routed) 0.000 -0.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1_n_0 + SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.527 -0.420 + clock pessimism 0.045 -0.375 + SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.092 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8] + ------------------------------------------------------------------- + required time 0.283 + arrival time -0.165 + ------------------------------------------------------------------- + slack 0.118 + +Slack (MET) : 0.118ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.475ns (logic 0.209ns (44.013%) route 0.266ns (55.987%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.420ns + Source Clock Delay (SCD): -0.640ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.208 -0.640 + SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q + net (fo=127, routed) 0.266 -0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 + SLICE_X151Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/I1 + SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.165 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/O + net (fo=1, routed) 0.000 -0.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1_n_0 + SLICE_X151Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.527 -0.420 + clock pessimism 0.045 -0.375 + SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.092 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8] + ------------------------------------------------------------------- + required time 0.283 + arrival time -0.165 + ------------------------------------------------------------------- + slack 0.118 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.475ns (logic 0.209ns (44.040%) route 0.266ns (55.960%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.403ns + Source Clock Delay (SCD): -0.630ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.218 -0.630 + SLICE_X84Y61 FDRE 0.000 -0.630 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C + SLICE_X84Y61 FDRE (Prop_fdre_C_Q) 0.164 -0.466 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/Q + net (fo=6, routed) 0.266 -0.201 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][14]__0_0[7] + SLICE_X82Y61 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/I3 + SLICE_X82Y61 LUT6 (Prop_lut6_I3_O) 0.045 -0.156 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/O + net (fo=1, routed) 0.000 -0.156 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_re[7] + SLICE_X82Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.544 -0.403 + clock pessimism 0.037 -0.366 + SLICE_X82Y61 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7] + ------------------------------------------------------------------- + required time 0.274 + arrival time -0.156 + ------------------------------------------------------------------- + slack 0.119 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.475ns (logic 0.209ns (44.040%) route 0.266ns (55.960%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.403ns + Source Clock Delay (SCD): -0.630ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.218 -0.630 + SLICE_X84Y61 FDRE 0.000 -0.630 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C + SLICE_X84Y61 FDRE (Prop_fdre_C_Q) 0.164 -0.466 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/Q + net (fo=6, routed) 0.266 -0.201 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][14]__0_0[7] + SLICE_X82Y61 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/I3 + SLICE_X82Y61 LUT6 (Prop_lut6_I3_O) 0.045 -0.156 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/O + net (fo=1, routed) 0.000 -0.156 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_re[7] + SLICE_X82Y61 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.544 -0.403 + clock pessimism 0.037 -0.366 + SLICE_X82Y61 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7] + ------------------------------------------------------------------- + required time 0.274 + arrival time -0.156 + ------------------------------------------------------------------- + slack 0.119 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.418ns + Source Clock Delay (SCD): -0.645ns + Clock Pessimism Removal (CPR): 0.227ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.203 -0.645 + SLICE_X39Y105 FDRE 0.000 -0.645 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C + SLICE_X39Y105 FDRE (Prop_fdre_C_Q) 0.141 -0.504 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/Q + net (fo=1, routed) 0.056 -0.448 u_matmul_axi_slave/mult_inst[3].u_mult/prod[59] + SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.529 -0.418 + clock pessimism -0.227 -0.645 + SLICE_X39Y105 FDRE (Hold_fdre_C_D) 0.078 -0.567 u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59] + ------------------------------------------------------------------- + required time 0.567 + arrival time -0.448 + ------------------------------------------------------------------- + slack 0.119 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.418ns + Source Clock Delay (SCD): -0.645ns + Clock Pessimism Removal (CPR): 0.227ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.203 -0.645 + SLICE_X39Y105 FDRE 0.000 -0.645 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C + SLICE_X39Y105 FDRE (Prop_fdre_C_Q) 0.141 -0.504 f u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/Q + net (fo=1, routed) 0.056 -0.448 u_matmul_axi_slave/mult_inst[3].u_mult/prod[59] + SLICE_X39Y105 FDRE f u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.529 -0.418 + clock pessimism -0.227 -0.645 + SLICE_X39Y105 FDRE (Hold_fdre_C_D) 0.078 -0.567 u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59] + ------------------------------------------------------------------- + required time 0.567 + arrival time -0.448 + ------------------------------------------------------------------- + slack 0.119 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.476ns (logic 0.209ns (43.921%) route 0.267ns (56.079%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.420ns + Source Clock Delay (SCD): -0.640ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.208 -0.640 + SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q + net (fo=127, routed) 0.267 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 + SLICE_X151Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/I1 + SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.164 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/O + net (fo=1, routed) 0.000 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1_n_0 + SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.527 -0.420 + clock pessimism 0.045 -0.375 + SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.091 -0.284 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6] + ------------------------------------------------------------------- + required time 0.284 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.476ns (logic 0.209ns (43.921%) route 0.267ns (56.079%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.420ns + Source Clock Delay (SCD): -0.640ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.208 -0.640 + SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q + net (fo=127, routed) 0.267 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 + SLICE_X151Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/I1 + SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/O + net (fo=1, routed) 0.000 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1_n_0 + SLICE_X151Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.527 -0.420 + clock pessimism 0.045 -0.375 + SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.091 -0.284 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6] + ------------------------------------------------------------------- + required time 0.284 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.727ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR @@ -16837,41 +23734,251 @@ Slack (MET) : 0.885ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) + Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.263ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.609 -0.338 - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] + 1.684 -0.263 + clock pessimism -0.218 -0.481 + SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 + required time 0.573 + arrival time 0.154 ------------------------------------------------------------------- - slack 0.885 + slack 0.727 -Slack (MET) : 0.885ns (arrival time - required time) +Slack (MET) : 0.727ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.263ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.684 -0.263 + clock pessimism -0.218 -0.481 + SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.573 + arrival time 0.154 + ------------------------------------------------------------------- + slack 0.727 + +Slack (MET) : 0.761ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.236 + ------------------------------------------------------------------- + slack 0.761 + +Slack (MET) : 0.761ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.236 + ------------------------------------------------------------------- + slack 0.761 + +Slack (MET) : 0.761ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.236 + ------------------------------------------------------------------- + slack 0.761 + +Slack (MET) : 0.761ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.236 + ------------------------------------------------------------------- + slack 0.761 + +Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR @@ -16879,215 +23986,4703 @@ Slack (MET) : 0.885ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.609 -0.338 - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 + required time 0.547 + arrival time 0.218 ------------------------------------------------------------------- - slack 0.885 + slack 0.765 -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.765ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.547 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.765 + +Slack (MET) : 0.765ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.547 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.765 + +Slack (MET) : 0.765ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.547 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.765 + +Slack (MET) : 0.765ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.547 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.765 + +Slack (MET) : 0.765ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.547 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.765 + +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.736ns (logic 0.227ns (30.836%) route 0.509ns (69.164%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.263ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.228 0.239 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y39 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.684 -0.263 + clock pessimism -0.196 -0.459 + SLICE_X13Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.551 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.551 + arrival time 0.239 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.853ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.329 + ------------------------------------------------------------------- + slack 0.853 + +Slack (MET) : 0.853ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.329 + ------------------------------------------------------------------- + slack 0.853 + +Slack (MET) : 0.853ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.329 + ------------------------------------------------------------------- + slack 0.853 + +Slack (MET) : 0.853ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.329 + ------------------------------------------------------------------- + slack 0.853 + +Slack (MET) : 0.853ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.329 + ------------------------------------------------------------------- + slack 0.853 + +Slack (MET) : 0.860ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.310 + ------------------------------------------------------------------- + slack 0.860 + +Slack (MET) : 0.860ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.310 + ------------------------------------------------------------------- + slack 0.860 + +Slack (MET) : 0.860ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.310 + ------------------------------------------------------------------- + slack 0.860 + +Slack (MET) : 0.860ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.310 + ------------------------------------------------------------------- + slack 0.860 + +Slack (MET) : 0.871ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.299 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.871ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.299 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.872ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.301 + ------------------------------------------------------------------- + slack 0.872 + +Slack (MET) : 0.872ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.301 + ------------------------------------------------------------------- + slack 0.872 + +Slack (MET) : 0.872ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.301 + ------------------------------------------------------------------- + slack 0.872 + +Slack (MET) : 0.890ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.864ns (logic 0.186ns (21.517%) route 0.678ns (78.483%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.380ns + Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13]/CLR + 1.235 -0.613 + SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.372 0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13] + 1.567 -0.380 + clock pessimism -0.192 -0.572 + SLICE_X112Y66 FDCE (Remov_fdce_C_CLR) -0.067 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0] ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 + required time 0.639 + arrival time 0.251 ------------------------------------------------------------------- - slack 0.906 + slack 0.890 -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.914ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.786ns (logic 0.249ns (31.687%) route 0.537ns (68.313%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.377ns + Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21]/CLR + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.371 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X125Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21] + 1.570 -0.377 + clock pessimism -0.192 -0.569 + SLICE_X125Y65 FDCE (Remov_fdce_C_CLR) -0.165 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253] ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 + required time 0.734 + arrival time 0.179 ------------------------------------------------------------------- - slack 0.906 + slack 0.914 -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.918ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 1.021ns (logic 0.246ns (24.092%) route 0.775ns (75.908%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.489 0.526 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X11Y53 FDCE f u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.611 -0.336 + clock pessimism 0.037 -0.299 + SLICE_X11Y53 FDCE (Remov_fdce_C_CLR) -0.092 -0.391 u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.391 + arrival time 0.526 + ------------------------------------------------------------------- + slack 0.918 + +Slack (MET) : 0.928ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.357 + ------------------------------------------------------------------- + slack 0.928 + +Slack (MET) : 0.928ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.357 + ------------------------------------------------------------------- + slack 0.928 + +Slack (MET) : 0.928ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.357 + ------------------------------------------------------------------- + slack 0.928 + +Slack (MET) : 0.928ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.357 + ------------------------------------------------------------------- + slack 0.928 + +Slack (MET) : 0.932ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.389ns + Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29]/CLR + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X112Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29] + 1.558 -0.389 + clock pessimism -0.192 -0.581 + SLICE_X112Y75 FDCE (Remov_fdce_C_CLR) -0.140 -0.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10] ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 + required time 0.721 + arrival time 0.210 ------------------------------------------------------------------- - slack 0.906 + slack 0.932 -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5]/CLR + 1.235 -0.613 + SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0] + ------------------------------------------------------------------- + required time 0.638 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1] + ------------------------------------------------------------------- + required time 0.638 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2] + ------------------------------------------------------------------- + required time 0.638 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.638 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.944ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.208 + ------------------------------------------------------------------- + slack 0.944 + +Slack (MET) : 0.944ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.208 + ------------------------------------------------------------------- + slack 0.944 + +Slack (MET) : 0.947ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.211ns (25.751%) route 0.608ns (74.249%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.377ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.164 -0.442 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.237 -0.205 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.047 -0.158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.371 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X125Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.570 -0.377 + clock pessimism -0.192 -0.569 + SLICE_X125Y65 FDCE (Remov_fdce_C_CLR) -0.165 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.947 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.952ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.822ns (logic 0.249ns (30.308%) route 0.573ns (69.692%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.035ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.407 0.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X125Y67 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism -0.192 -0.571 + SLICE_X125Y67 FDCE (Remov_fdce_C_CLR) -0.165 -0.736 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37] + ------------------------------------------------------------------- + required time 0.736 + arrival time 0.215 + ------------------------------------------------------------------- + slack 0.952 + +Slack (MET) : 0.955ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.430 + ------------------------------------------------------------------- + slack 0.955 + +Slack (MET) : 0.955ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.430 + ------------------------------------------------------------------- + slack 0.955 + +Slack (MET) : 0.957ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.389ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X113Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + clock pessimism -0.192 -0.581 + SLICE_X113Y75 FDCE (Remov_fdce_C_CLR) -0.165 -0.746 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5] + ------------------------------------------------------------------- + required time 0.746 + arrival time 0.210 + ------------------------------------------------------------------- + slack 0.957 + +Slack (MET) : 0.957ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.224 + ------------------------------------------------------------------- + slack 0.957 + +Slack (MET) : 0.957ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.224 + ------------------------------------------------------------------- + slack 0.957 + +Slack (MET) : 0.960ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X113Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism -0.192 -0.571 + SLICE_X113Y65 FDCE (Remov_fdce_C_CLR) -0.092 -0.663 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2] + ------------------------------------------------------------------- + required time 0.663 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.960 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5] + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1] ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 + required time 0.740 + arrival time 0.221 ------------------------------------------------------------------- - slack 0.906 + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[7]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[7]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[7] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[8]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[8]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[8] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[9]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[9] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.962ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[251]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.835ns (logic 0.249ns (29.836%) route 0.586ns (70.164%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.420 0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X130Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[251]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X130Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[251] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.228 + ------------------------------------------------------------------- + slack 0.962 + +Slack (MET) : 0.962ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[254]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.835ns (logic 0.249ns (29.836%) route 0.586ns (70.164%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.420 0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X130Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[254]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X130Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[254] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.228 + ------------------------------------------------------------------- + slack 0.962 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[104]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[104]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[104] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[105]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[105]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[105] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[106]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[106]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[106] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[107]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[107]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[107] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[108]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[108]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[108] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[109]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[109]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[109] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[110]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[110]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[110] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[111]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[111]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[111] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.850ns (logic 0.211ns (24.816%) route 0.639ns (75.184%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.389ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.164 -0.442 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.237 -0.205 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.047 -0.158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.402 0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X112Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + clock pessimism -0.192 -0.581 + SLICE_X112Y75 FDCE (Remov_fdce_C_CLR) -0.140 -0.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10] + ------------------------------------------------------------------- + required time 0.721 + arrival time 0.244 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 +======= + 1.470 -0.477 + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.939ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.140ns (logic 0.226ns (19.816%) route 0.914ns (80.184%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.744 0.461 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/delay_reg[1] + SLICE_X98Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.562 -0.385 + clock pessimism 0.040 -0.345 + SLICE_X98Y91 FDCE (Remov_fdce_C_CLR) -0.134 -0.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55] + ------------------------------------------------------------------- + required time 0.479 + arrival time 0.461 + ------------------------------------------------------------------- + slack 0.939 + +Slack (MET) : 0.942ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.141ns (logic 0.226ns (19.800%) route 0.915ns (80.200%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.745 0.461 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X92Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.040 -0.347 + SLICE_X92Y90 FDCE (Remov_fdce_C_CLR) -0.134 -0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54] + ------------------------------------------------------------------- + required time 0.481 + arrival time 0.461 + ------------------------------------------------------------------- + slack 0.942 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.122ns (logic 0.190ns (16.937%) route 0.932ns (83.063%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.249 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[0] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I3 + SLICE_X95Y102 LUT5 (Prop_lut5_I3_O) 0.049 -0.241 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.683 0.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.040 -0.347 + SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15] + ------------------------------------------------------------------- + required time 0.506 + arrival time 0.442 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.122ns (logic 0.190ns (16.937%) route 0.932ns (83.063%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.249 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[0] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I3 + SLICE_X95Y102 LUT5 (Prop_lut5_I3_O) 0.049 -0.241 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.683 0.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.040 -0.347 + SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53] + ------------------------------------------------------------------- + required time 0.506 + arrival time 0.442 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.952ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.148ns (logic 0.226ns (19.693%) route 0.922ns (80.307%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.751 0.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X90Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.557 -0.390 + clock pessimism 0.040 -0.350 + SLICE_X90Y91 FDCE (Remov_fdce_C_CLR) -0.134 -0.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25] + ------------------------------------------------------------------- + required time 0.484 + arrival time 0.468 + ------------------------------------------------------------------- + slack 0.952 + +Slack (MET) : 0.952ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.148ns (logic 0.226ns (19.693%) route 0.922ns (80.307%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.751 0.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X90Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.557 -0.390 + clock pessimism 0.040 -0.350 + SLICE_X90Y91 FDCE (Remov_fdce_C_CLR) -0.134 -0.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56] + ------------------------------------------------------------------- + required time 0.484 + arrival time 0.468 + ------------------------------------------------------------------- + slack 0.952 + +Slack (MET) : 0.952ns (arrival time - required time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.157ns (logic 0.206ns (17.801%) route 0.951ns (82.199%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] + SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 + SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.477 + ------------------------------------------------------------------- + slack 0.952 + +Slack (MET) : 0.952ns (arrival time - required time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.157ns (logic 0.206ns (17.801%) route 0.951ns (82.199%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] + SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 + SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.477 + ------------------------------------------------------------------- + slack 0.952 + +Slack (MET) : 0.952ns (arrival time - required time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.157ns (logic 0.206ns (17.801%) route 0.951ns (82.199%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] + SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 + SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.477 + ------------------------------------------------------------------- + slack 0.952 + +Slack (MET) : 0.952ns (arrival time - required time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.157ns (logic 0.206ns (17.801%) route 0.951ns (82.199%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] + SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 + SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.477 + ------------------------------------------------------------------- + slack 0.952 + +Slack (MET) : 0.956ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X103Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X103Y98 FDCE (Remov_fdce_C_CLR) -0.159 -0.498 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12] + ------------------------------------------------------------------- + required time 0.498 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.956 + +Slack (MET) : 0.956ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X103Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X103Y98 FDCE (Remov_fdce_C_CLR) -0.159 -0.498 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13] + ------------------------------------------------------------------- + required time 0.498 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.956 + +Slack (MET) : 0.956ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X95Y102 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X103Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X103Y98 FDCE (Remov_fdce_C_CLR) -0.159 -0.498 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19] + ------------------------------------------------------------------- + required time 0.498 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.956 + +Slack (MET) : 0.956ns (arrival time - required time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.163ns (logic 0.206ns (17.713%) route 0.957ns (82.287%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] + SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 + SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0] + ------------------------------------------------------------------- + required time 0.473 + arrival time 0.483 + ------------------------------------------------------------------- + slack 0.956 + +Slack (MET) : 0.956ns (arrival time - required time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.163ns (logic 0.206ns (17.713%) route 0.957ns (82.287%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] + SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 + SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16] + ------------------------------------------------------------------- + required time 0.473 + arrival time 0.483 + ------------------------------------------------------------------- + slack 0.956 + +Slack (MET) : 0.956ns (arrival time - required time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.163ns (logic 0.206ns (17.713%) route 0.957ns (82.287%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] + SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 + SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17] + ------------------------------------------------------------------- + required time 0.473 + arrival time 0.483 + ------------------------------------------------------------------- + slack 0.956 + +Slack (MET) : 0.956ns (arrival time - required time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.163ns (logic 0.206ns (17.713%) route 0.957ns (82.287%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.168 -0.680 + SLICE_X92Y102 FDCE 0.000 -0.680 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.164 -0.516 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 0.216 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/coeff_cnt_reg[1][0] + SLICE_X95Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I0 + SLICE_X95Y102 LUT5 (Prop_lut5_I0_O) 0.042 -0.258 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18] + ------------------------------------------------------------------- + required time 0.473 + arrival time 0.483 + ------------------------------------------------------------------- + slack 0.956 +>>>>>>> Stashed changes diff --git a/fpga/vivado_reports_nodsp/timing_setup_paths.rpt b/fpga/vivado_reports_nodsp/timing_setup_paths.rpt index 090a5ca..c4c4dea 100644 --- a/fpga/vivado_reports_nodsp/timing_setup_paths.rpt +++ b/fpga/vivado_reports_nodsp/timing_setup_paths.rpt @@ -1,34 +1,1990 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:12 2026 +| Date : Sat Jul 11 09:34:17 2026 | Host : fedora running 64-bit unknown -| Command : report_timing -delay_type max -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/timing_setup_paths.rpt +| Command : report_timing -delay_type max -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_setup_paths.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Report -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.070ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O + net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732] + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.555 + ------------------------------------------------------------------- + slack 0.070 + +Slack (MET) : 0.070ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O + net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732] + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.555 + ------------------------------------------------------------------- + slack 0.070 + +Slack (MET) : 0.070ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O + net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732] + SLICE_X145Y37 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.555 + ------------------------------------------------------------------- + slack 0.070 + +Slack (MET) : 0.070ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O + net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732] + SLICE_X145Y37 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.555 + ------------------------------------------------------------------- + slack 0.070 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.080 + ------------------------------------------------------------------- + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.080 + ------------------------------------------------------------------- + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.080 + ------------------------------------------------------------------- + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.080 + ------------------------------------------------------------------- + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.080 + ------------------------------------------------------------------- + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.080 + ------------------------------------------------------------------- + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.080 + ------------------------------------------------------------------- + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.080 + ------------------------------------------------------------------- + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.080 + ------------------------------------------------------------------- + slack 0.088 + +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.080 + ------------------------------------------------------------------- + slack 0.088 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.077 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.077 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.077 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.077 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.077 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.077 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.077 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.077 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.077 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.077 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.125ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -36,38 +1992,38 @@ Slack (MET) : 0.167ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] + AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 r ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.197 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- @@ -76,32 +2032,32 @@ Slack (MET) : 0.167ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 + required time 13.322 + arrival time -13.197 ------------------------------------------------------------------- - slack 0.167 + slack 0.125 -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.125ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -109,38 +2065,38 @@ Slack (MET) : 0.167ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] + AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 r ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.197 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- @@ -149,32 +2105,32 @@ Slack (MET) : 0.167ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 + required time 13.322 + arrival time -13.197 ------------------------------------------------------------------- - slack 0.167 + slack 0.125 -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.125ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -182,38 +2138,38 @@ Slack (MET) : 0.167ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 + SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] + AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 r ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.197 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- @@ -222,32 +2178,32 @@ Slack (MET) : 0.167ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 + required time 13.322 + arrival time -13.197 ------------------------------------------------------------------- - slack 0.167 + slack 0.125 -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.125ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -255,38 +2211,38 @@ Slack (MET) : 0.167ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 + SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] + AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 r ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.197 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- @@ -295,32 +2251,32 @@ Slack (MET) : 0.167ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 + required time 13.322 + arrival time -13.197 ------------------------------------------------------------------- - slack 0.167 + slack 0.125 -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.125ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -328,38 +2284,7178 @@ Slack (MET) : 0.167ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.146 2.414 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I + AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/I + AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 f ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.197 ext_ram_data[18] + AB17 f ext_ram_data[18] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.197 + ------------------------------------------------------------------- + slack 0.125 + +Slack (MET) : 0.125ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[18] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.146 2.414 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I + AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/I + AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 f ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.197 ext_ram_data[18] + AB17 f ext_ram_data[18] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.197 + ------------------------------------------------------------------- + slack 0.125 + +Slack (MET) : 0.125ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[18] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 + SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.146 2.414 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I + AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/I + AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 f ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.197 ext_ram_data[18] + AB17 f ext_ram_data[18] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.197 + ------------------------------------------------------------------- + slack 0.125 + +Slack (MET) : 0.125ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[18] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 + SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.146 2.414 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I + AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/I + AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 f ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.197 ext_ram_data[18] + AB17 f ext_ram_data[18] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.197 + ------------------------------------------------------------------- + slack 0.125 + +Slack (MET) : 0.128ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948] + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948] + ------------------------------------------------------------------- + required time 10.701 + arrival time -10.573 + ------------------------------------------------------------------- + slack 0.128 + +Slack (MET) : 0.128ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948] + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948] + ------------------------------------------------------------------- + required time 10.701 + arrival time -10.573 + ------------------------------------------------------------------- + slack 0.128 + +Slack (MET) : 0.128ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948] + SLICE_X163Y34 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948] + ------------------------------------------------------------------- + required time 10.701 + arrival time -10.573 + ------------------------------------------------------------------- + slack 0.128 + +Slack (MET) : 0.128ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948] + SLICE_X163Y34 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948] + ------------------------------------------------------------------- + required time 10.701 + arrival time -10.573 + ------------------------------------------------------------------- + slack 0.128 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.038 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.135ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O + net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731] + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.491 + ------------------------------------------------------------------- + slack 0.135 + +Slack (MET) : 0.135ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O + net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731] + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.491 + ------------------------------------------------------------------- + slack 0.135 + +Slack (MET) : 0.135ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O + net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731] + SLICE_X145Y37 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.491 + ------------------------------------------------------------------- + slack 0.135 + +Slack (MET) : 0.135ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O + net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731] + SLICE_X145Y37 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.828 11.153 + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731] + ------------------------------------------------------------------- + required time 10.626 + arrival time -10.491 + ------------------------------------------------------------------- + slack 0.135 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.101 + ------------------------------------------------------------------- + slack 0.151 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.013 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.756 -2.520 + SLICE_X74Y66 FDCE 0.000 -2.520 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.675 11.000 + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg + ------------------------------------------------------------------- + required time 10.168 + arrival time -10.011 + ------------------------------------------------------------------- + slack 0.157 + +Slack (MET) : 0.159ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S + SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O + net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943] + SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943] + ------------------------------------------------------------------- + required time 10.750 + arrival time -10.591 + ------------------------------------------------------------------- + slack 0.159 + +Slack (MET) : 0.159ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S + SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O + net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943] + SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943] + ------------------------------------------------------------------- + required time 10.750 + arrival time -10.591 + ------------------------------------------------------------------- + slack 0.159 + +Slack (MET) : 0.159ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S + SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O + net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943] + SLICE_X162Y34 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943] + ------------------------------------------------------------------- + required time 10.750 + arrival time -10.591 + ------------------------------------------------------------------- + slack 0.159 + +Slack (MET) : 0.159ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S + SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O + net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943] + SLICE_X162Y34 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943] + ------------------------------------------------------------------- + required time 10.750 + arrival time -10.591 + ------------------------------------------------------------------- + slack 0.159 + +Slack (MET) : 0.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2 + SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O + net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0 + SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0 + SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O + net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975] + SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.833 11.158 + clock pessimism -0.498 10.660 + clock uncertainty -0.093 10.567 + SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975] + ------------------------------------------------------------------- + required time 10.631 + arrival time -10.455 + ------------------------------------------------------------------- + slack 0.175 + +Slack (MET) : 0.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X155Y43 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2 + SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O + net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0 + SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0 + SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O + net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975] + SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.833 11.158 + clock pessimism -0.498 10.660 + clock uncertainty -0.093 10.567 + SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975] + ------------------------------------------------------------------- + required time 10.631 + arrival time -10.455 + ------------------------------------------------------------------- + slack 0.175 + +Slack (MET) : 0.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2 + SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O + net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0 + SLICE_X155Y43 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0 + SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O + net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975] + SLICE_X155Y43 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.833 11.158 + clock pessimism -0.498 10.660 + clock uncertainty -0.093 10.567 + SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975] + ------------------------------------------------------------------- + required time 10.631 + arrival time -10.455 + ------------------------------------------------------------------- + slack 0.175 + +Slack (MET) : 0.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X155Y43 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2 + SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O + net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0 + SLICE_X155Y43 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0 + SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O + net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975] + SLICE_X155Y43 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.833 11.158 + clock pessimism -0.498 10.660 + clock uncertainty -0.093 10.567 + SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975] + ------------------------------------------------------------------- + required time 10.631 + arrival time -10.455 + ------------------------------------------------------------------- + slack 0.175 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.214ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2 + SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O + net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0 + SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0 + SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888] + SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.907 11.232 + clock pessimism -0.498 10.734 + clock uncertainty -0.093 10.641 + SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888] + ------------------------------------------------------------------- + required time 10.754 + arrival time -10.573 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.214ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X162Y40 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2 + SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O + net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0 + SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0 + SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888] + SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.907 11.232 + clock pessimism -0.498 10.734 + clock uncertainty -0.093 10.641 + SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888] + ------------------------------------------------------------------- + required time 10.754 + arrival time -10.573 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.214ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2 + SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O + net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0 + SLICE_X162Y40 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0 + SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888] + SLICE_X162Y40 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.907 11.232 + clock pessimism -0.498 10.734 + clock uncertainty -0.093 10.641 + SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888] + ------------------------------------------------------------------- + required time 10.754 + arrival time -10.573 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.214ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X162Y40 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2 + SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O + net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0 + SLICE_X162Y40 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0 + SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888] + SLICE_X162Y40 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.907 11.232 + clock pessimism -0.498 10.734 + clock uncertainty -0.093 10.641 + SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888] + ------------------------------------------------------------------- + required time 10.754 + arrival time -10.573 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.795 -2.481 + SLICE_X118Y91 FDCE 0.000 -2.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.687 11.012 + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg + ------------------------------------------------------------------- + required time 10.252 + arrival time -10.071 + ------------------------------------------------------------------- + slack 0.181 + +Slack (MET) : 0.185ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y33 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S + SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O + net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812] + SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.902 11.227 + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] + ------------------------------------------------------------------- + required time 10.700 + arrival time -10.515 + ------------------------------------------------------------------- + slack 0.185 + +Slack (MET) : 0.185ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y33 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S + SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O + net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812] + SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.902 11.227 + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] + ------------------------------------------------------------------- + required time 10.700 + arrival time -10.515 + ------------------------------------------------------------------- + slack 0.185 + +Slack (MET) : 0.185ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y33 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S + SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O + net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812] + SLICE_X160Y33 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.902 11.227 + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] + ------------------------------------------------------------------- + required time 10.700 + arrival time -10.515 + ------------------------------------------------------------------- + slack 0.185 + +Slack (MET) : 0.185ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y33 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S + SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O + net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812] + SLICE_X160Y33 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.902 11.227 + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] + ------------------------------------------------------------------- + required time 10.700 + arrival time -10.515 + ------------------------------------------------------------------- + slack 0.185 + +Slack (MET) : 0.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.992ns (logic 0.732ns (5.634%) route 12.260ns (94.366%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.513 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/O + net (fo=1, routed) 0.000 10.513 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[946] + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946] + ------------------------------------------------------------------- + required time 10.701 + arrival time -10.513 + ------------------------------------------------------------------- + slack 0.188 + +Slack (MET) : 0.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.992ns (logic 0.732ns (5.634%) route 12.260ns (94.366%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.796 -2.480 + SLICE_X125Y88 FDRE 0.000 -2.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/S + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.513 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/O + net (fo=1, routed) 0.000 10.513 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[946] + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 + propagated clock network latency + 3.903 11.228 + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946] + ------------------------------------------------------------------- + required time 10.701 + arrival time -10.513 + ------------------------------------------------------------------- + slack 0.188 + +Slack (MET) : 0.253ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.069 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.069 + ------------------------------------------------------------------- + slack 0.253 + +Slack (MET) : 0.253ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.069 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.069 + ------------------------------------------------------------------- + slack 0.253 + +Slack (MET) : 0.253ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.069 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.069 + ------------------------------------------------------------------- + slack 0.253 + +Slack (MET) : 0.253ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.069 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.069 + ------------------------------------------------------------------- + slack 0.253 + +Slack (MET) : 0.253ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.069 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.069 + ------------------------------------------------------------------- + slack 0.253 + +Slack (MET) : 0.253ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.069 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.069 + ------------------------------------------------------------------- + slack 0.253 + +Slack (MET) : 0.253ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.069 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.069 + ------------------------------------------------------------------- + slack 0.253 + +Slack (MET) : 0.253ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.069 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.069 + ------------------------------------------------------------------- + slack 0.253 + +Slack (MET) : 0.253ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.069 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.069 + ------------------------------------------------------------------- + slack 0.253 + +Slack (MET) : 0.253ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.069 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -13.069 + ------------------------------------------------------------------- + slack 0.253 + +Slack (MET) : 0.323ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[18] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.407ns (logic 5.205ns (33.780%) route 10.202ns (66.220%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 0.977 2.066 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR0_O) + 0.150 2.216 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 2.877 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.205 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 3.877 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.001 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.578 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.702 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.334 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.458 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 4.015 9.473 ext_ram_data_IOBUF[18]_inst/I AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] + AB17 OBUFT (Prop_obuft_I_O) 3.527 12.999 r ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.999 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- @@ -368,32 +9464,32 @@ Slack (MET) : 0.167ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 + required time 13.322 + arrival time -12.999 ------------------------------------------------------------------- - slack 0.167 + slack 0.323 -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.323ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.407ns (logic 5.205ns (33.780%) route 10.202ns (66.220%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -401,38 +9497,38 @@ Slack (MET) : 0.167ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 0.977 2.066 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR0_O) + 0.150 2.216 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 2.877 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.205 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 3.877 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.001 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.578 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.702 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.334 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.458 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 4.015 9.473 ext_ram_data_IOBUF[18]_inst/I AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] + AB17 OBUFT (Prop_obuft_I_O) 3.527 12.999 r ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.999 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- @@ -441,324 +9537,32 @@ Slack (MET) : 0.167ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 + required time 13.322 + arrival time -12.999 ------------------------------------------------------------------- - slack 0.167 + slack 0.323 -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.342ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -766,38 +9570,56 @@ Slack (MET) : 0.284ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T + Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.980 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- @@ -806,32 +9628,32 @@ Slack (MET) : 0.284ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 + required time 13.322 + arrival time -12.980 ------------------------------------------------------------------- - slack 0.284 + slack 0.342 -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.342ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -839,38 +9661,56 @@ Slack (MET) : 0.284ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T + Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.980 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- @@ -879,32 +9719,32 @@ Slack (MET) : 0.284ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 + required time 13.322 + arrival time -12.980 ------------------------------------------------------------------- - slack 0.284 + slack 0.342 -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.342ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -912,38 +9752,56 @@ Slack (MET) : 0.284ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T + Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.980 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- @@ -952,32 +9810,32 @@ Slack (MET) : 0.284ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 + required time 13.322 + arrival time -12.980 ------------------------------------------------------------------- - slack 0.284 + slack 0.342 -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.342ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -985,38 +9843,56 @@ Slack (MET) : 0.284ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T + Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.980 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- @@ -1025,32 +9901,32 @@ Slack (MET) : 0.284ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 + required time 13.322 + arrival time -12.980 ------------------------------------------------------------------- - slack 0.284 + slack 0.342 -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.342ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1058,38 +9934,56 @@ Slack (MET) : 0.284ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T + Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.980 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- @@ -1098,32 +9992,32 @@ Slack (MET) : 0.284ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 + required time 13.322 + arrival time -12.980 ------------------------------------------------------------------- - slack 0.284 + slack 0.342 -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.342ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1131,38 +10025,56 @@ Slack (MET) : 0.284ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T + Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.980 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- @@ -1171,32 +10083,32 @@ Slack (MET) : 0.284ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 + required time 13.322 + arrival time -12.980 ------------------------------------------------------------------- - slack 0.284 + slack 0.342 -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.342ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1204,38 +10116,56 @@ Slack (MET) : 0.284ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T + Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.980 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- @@ -1244,32 +10174,32 @@ Slack (MET) : 0.284ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 + required time 13.322 + arrival time -12.980 ------------------------------------------------------------------- - slack 0.284 + slack 0.342 -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.342ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1277,38 +10207,56 @@ Slack (MET) : 0.284ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T + Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.980 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- @@ -1317,32 +10265,32 @@ Slack (MET) : 0.284ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 + required time 13.322 + arrival time -12.980 ------------------------------------------------------------------- - slack 0.284 + slack 0.342 -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.342ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1350,38 +10298,56 @@ Slack (MET) : 0.284ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T + Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.980 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- @@ -1390,32 +10356,32 @@ Slack (MET) : 0.284ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 + required time 13.322 + arrival time -12.980 ------------------------------------------------------------------- - slack 0.284 + slack 0.342 -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.342ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1423,38 +10389,56 @@ Slack (MET) : 0.284ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T + Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.980 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- @@ -1463,2662 +10447,32 @@ Slack (MET) : 0.284ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 + required time 13.322 + arrival time -12.980 ------------------------------------------------------------------- - slack 0.284 + slack 0.342 -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.395ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4126,38 +10480,38 @@ Slack (MET) : 0.431ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O + net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] + SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0 + SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O + net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 + SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4 + SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O + net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] + SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5 + SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O + net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] + SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 + SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O + net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] + AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 r ext_ram_data_IOBUF[20]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.927 ext_ram_data[20] AD18 r ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- @@ -4166,32 +10520,32 @@ Slack (MET) : 0.431ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 + required time 13.322 + arrival time -12.927 ------------------------------------------------------------------- - slack 0.431 + slack 0.395 -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.395ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4199,38 +10553,38 @@ Slack (MET) : 0.431ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O + net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] + SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0 + SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O + net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 + SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4 + SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O + net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] + SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5 + SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O + net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] + SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 + SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O + net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] + AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 r ext_ram_data_IOBUF[20]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.927 ext_ram_data[20] AD18 r ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- @@ -4239,32 +10593,32 @@ Slack (MET) : 0.431ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 + required time 13.322 + arrival time -12.927 ------------------------------------------------------------------- - slack 0.431 + slack 0.395 -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.395ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4272,38 +10626,38 @@ Slack (MET) : 0.431ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 + SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O + net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] + SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0 + SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O + net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 + SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4 + SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O + net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] + SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5 + SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O + net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] + SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 + SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O + net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] + AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 r ext_ram_data_IOBUF[20]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.927 ext_ram_data[20] AD18 r ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- @@ -4312,32 +10666,32 @@ Slack (MET) : 0.431ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 + required time 13.322 + arrival time -12.927 ------------------------------------------------------------------- - slack 0.431 + slack 0.395 -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.395ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4345,38 +10699,38 @@ Slack (MET) : 0.431ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 + SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O + net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] + SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0 + SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O + net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 + SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4 + SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O + net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] + SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5 + SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O + net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] + SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 + SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O + net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] + AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 r ext_ram_data_IOBUF[20]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.927 ext_ram_data[20] AD18 r ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- @@ -4385,32 +10739,32 @@ Slack (MET) : 0.431ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 + required time 13.322 + arrival time -12.927 ------------------------------------------------------------------- - slack 0.431 + slack 0.395 -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.395ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4418,39 +10772,39 @@ Slack (MET) : 0.431ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.452 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O + net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] + SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0 + SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O + net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 + SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4 + SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O + net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] + SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5 + SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O + net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] + SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 + SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O + net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I + AD18 f ext_ram_data_IOBUF[20]_inst/OBUFT/I + AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 f ext_ram_data_IOBUF[20]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.927 ext_ram_data[20] + AD18 f ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -4458,32 +10812,32 @@ Slack (MET) : 0.431ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 + required time 13.322 + arrival time -12.927 ------------------------------------------------------------------- - slack 0.431 + slack 0.395 -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.395ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4491,39 +10845,39 @@ Slack (MET) : 0.431ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 + SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.452 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O + net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] + SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0 + SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O + net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 + SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4 + SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O + net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] + SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5 + SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O + net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] + SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 + SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O + net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I + AD18 f ext_ram_data_IOBUF[20]_inst/OBUFT/I + AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 f ext_ram_data_IOBUF[20]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.927 ext_ram_data[20] + AD18 f ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -4531,32 +10885,32 @@ Slack (MET) : 0.431ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 + required time 13.322 + arrival time -12.927 ------------------------------------------------------------------- - slack 0.431 + slack 0.395 -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.395ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -4564,39 +10918,39 @@ Slack (MET) : 0.431ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 + SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.452 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O + net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] + SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0 + SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O + net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 + SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4 + SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O + net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] + SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5 + SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O + net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] + SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 + SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O + net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I + AD18 f ext_ram_data_IOBUF[20]_inst/OBUFT/I + AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 f ext_ram_data_IOBUF[20]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.927 ext_ram_data[20] + AD18 f ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -4604,1201 +10958,32 @@ Slack (MET) : 0.431ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 + required time 13.322 + arrival time -12.927 ------------------------------------------------------------------- - slack 0.431 + slack 0.395 -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.395ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) + Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -5806,39 +10991,39 @@ Slack (MET) : 0.477ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 + SLICE_X20Y79 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.452 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O + net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] + SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0 + SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O + net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 + SLICE_X24Y78 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4 + SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 f u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O + net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] + SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5 + SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O + net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] + SLICE_X28Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 + SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O + net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I + AD18 f ext_ram_data_IOBUF[20]_inst/OBUFT/I + AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 f ext_ram_data_IOBUF[20]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.927 ext_ram_data[20] + AD18 f ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -5846,32 +11031,942 @@ Slack (MET) : 0.477ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 + required time 13.322 + arrival time -12.927 ------------------------------------------------------------------- - slack 0.477 + slack 0.395 -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.403ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.919 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.919 + ------------------------------------------------------------------- + slack 0.403 + +Slack (MET) : 0.403ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.919 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.919 + ------------------------------------------------------------------- + slack 0.403 + +Slack (MET) : 0.403ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.919 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.919 + ------------------------------------------------------------------- + slack 0.403 + +Slack (MET) : 0.403ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.919 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.919 + ------------------------------------------------------------------- + slack 0.403 + +Slack (MET) : 0.403ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.919 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.919 + ------------------------------------------------------------------- + slack 0.403 + +Slack (MET) : 0.403ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.919 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.919 + ------------------------------------------------------------------- + slack 0.403 + +Slack (MET) : 0.403ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.919 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.919 + ------------------------------------------------------------------- + slack 0.403 + +Slack (MET) : 0.403ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.919 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.919 + ------------------------------------------------------------------- + slack 0.403 + +Slack (MET) : 0.403ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.919 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.919 + ------------------------------------------------------------------- + slack 0.403 + +Slack (MET) : 0.403ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.919 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.919 + ------------------------------------------------------------------- + slack 0.403 + +Slack (MET) : 0.416ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] + Destination: ext_ram_data[6] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -5879,39 +11974,36 @@ Slack (MET) : 0.477ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 + SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.820 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O + net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38] + SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3 + SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 r u_matmul_axi_slave/ram_reg_i_46/O + net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] + SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5 + SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O + net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 + SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0 + SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O + net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I + AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I + AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 r ext_ram_data_IOBUF[6]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.906 ext_ram_data[6] + AE20 r ext_ram_data[6] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -5919,32 +12011,32 @@ Slack (MET) : 0.477ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 + required time 13.322 + arrival time -12.906 ------------------------------------------------------------------- - slack 0.477 + slack 0.416 -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.416ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] + Destination: ext_ram_data[6] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -5952,39 +12044,36 @@ Slack (MET) : 0.477ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 + SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.820 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O + net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38] + SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3 + SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 r u_matmul_axi_slave/ram_reg_i_46/O + net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] + SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5 + SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O + net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 + SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0 + SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O + net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I + AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I + AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 r ext_ram_data_IOBUF[6]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.906 ext_ram_data[6] + AE20 r ext_ram_data[6] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -5992,32 +12081,32 @@ Slack (MET) : 0.477ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 + required time 13.322 + arrival time -12.906 ------------------------------------------------------------------- - slack 0.477 + slack 0.416 -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.416ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] + Destination: ext_ram_data[6] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6025,39 +12114,36 @@ Slack (MET) : 0.477ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 + SLICE_X36Y83 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.820 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O + net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38] + SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3 + SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 r u_matmul_axi_slave/ram_reg_i_46/O + net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] + SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5 + SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O + net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 + SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0 + SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O + net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I + AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I + AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 r ext_ram_data_IOBUF[6]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.906 ext_ram_data[6] + AE20 r ext_ram_data[6] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -6065,32 +12151,32 @@ Slack (MET) : 0.477ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 + required time 13.322 + arrival time -12.906 ------------------------------------------------------------------- - slack 0.477 + slack 0.416 -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.416ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] + Destination: ext_ram_data[6] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6098,39 +12184,36 @@ Slack (MET) : 0.477ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 + SLICE_X36Y83 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.820 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O + net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38] + SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3 + SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 r u_matmul_axi_slave/ram_reg_i_46/O + net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] + SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5 + SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O + net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 + SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0 + SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O + net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I + AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I + AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 r ext_ram_data_IOBUF[6]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.906 ext_ram_data[6] + AE20 r ext_ram_data[6] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -6138,32 +12221,32 @@ Slack (MET) : 0.477ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 + required time 13.322 + arrival time -12.906 ------------------------------------------------------------------- - slack 0.477 + slack 0.416 -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.416ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] + Destination: ext_ram_data[6] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6171,39 +12254,36 @@ Slack (MET) : 0.477ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 + SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.820 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O + net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38] + SLICE_X23Y79 f u_matmul_axi_slave/ram_reg_i_46/I3 + SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 f u_matmul_axi_slave/ram_reg_i_46/O + net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] + SLICE_X19Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5 + SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O + net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 + SLICE_X12Y76 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0 + SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O + net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I + AE20 f ext_ram_data_IOBUF[6]_inst/OBUFT/I + AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 f ext_ram_data_IOBUF[6]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.906 ext_ram_data[6] + AE20 f ext_ram_data[6] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -6211,32 +12291,32 @@ Slack (MET) : 0.477ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 + required time 13.322 + arrival time -12.906 ------------------------------------------------------------------- - slack 0.477 + slack 0.416 -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.416ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] + Destination: ext_ram_data[6] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6244,39 +12324,36 @@ Slack (MET) : 0.477ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 + SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.820 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O + net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38] + SLICE_X23Y79 f u_matmul_axi_slave/ram_reg_i_46/I3 + SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 f u_matmul_axi_slave/ram_reg_i_46/O + net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] + SLICE_X19Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5 + SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O + net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 + SLICE_X12Y76 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0 + SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O + net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I + AE20 f ext_ram_data_IOBUF[6]_inst/OBUFT/I + AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 f ext_ram_data_IOBUF[6]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.906 ext_ram_data[6] + AE20 f ext_ram_data[6] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -6284,32 +12361,32 @@ Slack (MET) : 0.477ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 + required time 13.322 + arrival time -12.906 ------------------------------------------------------------------- - slack 0.477 + slack 0.416 -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.416ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] + Destination: ext_ram_data[6] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6317,39 +12394,36 @@ Slack (MET) : 0.477ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 + SLICE_X36Y83 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.820 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O + net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38] + SLICE_X23Y79 f u_matmul_axi_slave/ram_reg_i_46/I3 + SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 f u_matmul_axi_slave/ram_reg_i_46/O + net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] + SLICE_X19Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5 + SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O + net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 + SLICE_X12Y76 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0 + SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O + net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I + AE20 f ext_ram_data_IOBUF[6]_inst/OBUFT/I + AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 f ext_ram_data_IOBUF[6]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.906 ext_ram_data[6] + AE20 f ext_ram_data[6] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -6357,32 +12431,32 @@ Slack (MET) : 0.477ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 + required time 13.322 + arrival time -12.906 ------------------------------------------------------------------- - slack 0.477 + slack 0.416 -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.416ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] + Destination: ext_ram_data[6] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6390,39 +12464,36 @@ Slack (MET) : 0.477ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 + SLICE_X36Y83 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.820 f u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O + net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38] + SLICE_X23Y79 f u_matmul_axi_slave/ram_reg_i_46/I3 + SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 f u_matmul_axi_slave/ram_reg_i_46/O + net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] + SLICE_X19Y79 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5 + SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O + net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 + SLICE_X12Y76 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0 + SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O + net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I + AE20 f ext_ram_data_IOBUF[6]_inst/OBUFT/I + AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 f ext_ram_data_IOBUF[6]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.906 ext_ram_data[6] + AE20 f ext_ram_data[6] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -6430,32 +12501,32 @@ Slack (MET) : 0.477ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 + required time 13.322 + arrival time -12.906 ------------------------------------------------------------------- - slack 0.477 + slack 0.416 -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] + Destination: ext_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6463,39 +12534,39 @@ Slack (MET) : 0.477ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I + AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I + AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.900 ext_ram_data[31] + AC23 r ext_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -6503,32 +12574,32 @@ Slack (MET) : 0.477ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 + required time 13.322 + arrival time -12.900 ------------------------------------------------------------------- - slack 0.477 + slack 0.422 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6536,61 +12607,854 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I + AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I + AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.900 ext_ram_data[31] + AC23 r ext_ram_data[31] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.900 + ------------------------------------------------------------------- + slack 0.422 + +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[31] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I + AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I + AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.900 ext_ram_data[31] + AC23 r ext_ram_data[31] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.900 + ------------------------------------------------------------------- + slack 0.422 + +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[31] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I + AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I + AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.900 ext_ram_data[31] + AC23 r ext_ram_data[31] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.900 + ------------------------------------------------------------------- + slack 0.422 + +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[31] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I + AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I + AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.900 ext_ram_data[31] + AC23 r ext_ram_data[31] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.900 + ------------------------------------------------------------------- + slack 0.422 + +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[31] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I + AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I + AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.900 ext_ram_data[31] + AC23 r ext_ram_data[31] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.900 + ------------------------------------------------------------------- + slack 0.422 + +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[31] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I + AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I + AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.900 ext_ram_data[31] + AC23 r ext_ram_data[31] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.900 + ------------------------------------------------------------------- + slack 0.422 + +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[31] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I + AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I + AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.900 ext_ram_data[31] + AC23 r ext_ram_data[31] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.900 + ------------------------------------------------------------------- + slack 0.422 + +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[31] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I + AC23 f ext_ram_data_IOBUF[31]_inst/OBUFT/I + AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 f ext_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.900 ext_ram_data[31] + AC23 f ext_ram_data[31] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.900 + ------------------------------------------------------------------- + slack 0.422 + +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[31] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I + AC23 f ext_ram_data_IOBUF[31]_inst/OBUFT/I + AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 f ext_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.900 ext_ram_data[31] + AC23 f ext_ram_data[31] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.900 + ------------------------------------------------------------------- + slack 0.422 + +Slack (MET) : 0.443ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[6] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.287ns (logic 5.138ns (33.611%) route 10.149ns (66.389%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.551 2.641 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB0 + SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR0 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR0_O) + 0.152 2.793 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O + net (fo=1, routed) 1.421 4.214 u_matmul_axi_slave/ep_rd_c1[38] + SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3 + SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.562 r u_matmul_axi_slave/ram_reg_i_46/O + net (fo=1, routed) 0.461 5.023 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] + SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5 + SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.147 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O + net (fo=4, routed) 0.529 5.676 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 + SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0 + SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.800 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O + net (fo=2, routed) 3.517 9.317 ext_ram_data_IOBUF[6]_inst/I + AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I + AE20 OBUFT (Prop_obuft_I_O) 3.562 12.879 r ext_ram_data_IOBUF[6]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.879 ext_ram_data[6] + AE20 r ext_ram_data[6] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.879 + ------------------------------------------------------------------- + slack 0.443 + +Slack (MET) : 0.443ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[6] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.287ns (logic 5.138ns (33.611%) route 10.149ns (66.389%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.551 2.641 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB0 + SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR0 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR0_O) + 0.152 2.793 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O + net (fo=1, routed) 1.421 4.214 u_matmul_axi_slave/ep_rd_c1[38] + SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3 + SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.562 r u_matmul_axi_slave/ram_reg_i_46/O + net (fo=1, routed) 0.461 5.023 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] + SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5 + SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.147 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O + net (fo=4, routed) 0.529 5.676 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 + SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0 + SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.800 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O + net (fo=2, routed) 3.517 9.317 ext_ram_data_IOBUF[6]_inst/I + AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I + AE20 OBUFT (Prop_obuft_I_O) 3.562 12.879 r ext_ram_data_IOBUF[6]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.879 ext_ram_data[6] + AE20 r ext_ram_data[6] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.879 + ------------------------------------------------------------------- + slack 0.443 + +Slack (MET) : 0.475ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.847 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -6598,32 +13462,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.847 ------------------------------------------------------------------- - slack 0.555 + slack 0.475 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.475ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] + Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6631,61 +13495,57 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.847 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -6693,32 +13553,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.847 ------------------------------------------------------------------- - slack 0.555 + slack 0.475 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.475ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] + Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6726,61 +13586,57 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.847 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -6788,32 +13644,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.847 ------------------------------------------------------------------- - slack 0.555 + slack 0.475 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.475ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] + Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6821,61 +13677,57 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.847 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -6883,32 +13735,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.847 ------------------------------------------------------------------- - slack 0.555 + slack 0.475 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.475ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] + Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6916,61 +13768,57 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.847 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -6978,32 +13826,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.847 ------------------------------------------------------------------- - slack 0.555 + slack 0.475 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.475ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] + Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7011,61 +13859,57 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.847 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -7073,32 +13917,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.847 ------------------------------------------------------------------- - slack 0.555 + slack 0.475 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.475ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] + Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7106,61 +13950,57 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.847 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -7168,32 +14008,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.847 ------------------------------------------------------------------- - slack 0.555 + slack 0.475 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.475ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] + Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7201,61 +14041,57 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.847 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -7263,32 +14099,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.847 ------------------------------------------------------------------- - slack 0.555 + slack 0.475 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.475ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] + Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7296,61 +14132,57 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.847 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -7358,32 +14190,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.847 ------------------------------------------------------------------- - slack 0.555 + slack 0.475 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.475ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] + Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7391,61 +14223,57 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.847 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -7453,32 +14281,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.847 ------------------------------------------------------------------- - slack 0.555 + slack 0.475 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] +Slack (MET) : 0.483ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7486,61 +14314,39 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I + M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I + M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.839 base_ram_data[31] + M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -7548,32 +14354,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.839 ------------------------------------------------------------------- - slack 0.555 + slack 0.483 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] +Slack (MET) : 0.483ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7581,61 +14387,39 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I + M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I + M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.839 base_ram_data[31] + M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -7643,32 +14427,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.839 ------------------------------------------------------------------- - slack 0.555 + slack 0.483 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] +Slack (MET) : 0.483ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7676,61 +14460,39 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I + M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I + M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.839 base_ram_data[31] + M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -7738,32 +14500,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.839 ------------------------------------------------------------------- - slack 0.555 + slack 0.483 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] +Slack (MET) : 0.483ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7771,61 +14533,39 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I + M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I + M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.839 base_ram_data[31] + M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -7833,32 +14573,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.839 ------------------------------------------------------------------- - slack 0.555 + slack 0.483 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] +Slack (MET) : 0.483ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7866,61 +14606,39 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I + M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I + M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.839 base_ram_data[31] + M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -7928,32 +14646,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.839 ------------------------------------------------------------------- - slack 0.555 + slack 0.483 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] +Slack (MET) : 0.483ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7961,61 +14679,39 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I + M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I + M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.839 base_ram_data[31] + M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -8023,32 +14719,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.839 ------------------------------------------------------------------- - slack 0.555 + slack 0.483 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] +Slack (MET) : 0.483ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -8056,61 +14752,39 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I + M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I + M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.839 base_ram_data[31] + M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -8118,32 +14792,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.839 ------------------------------------------------------------------- - slack 0.555 + slack 0.483 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] +Slack (MET) : 0.483ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -8151,61 +14825,39 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I + M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I + M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.839 base_ram_data[31] + M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -8213,32 +14865,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.839 ------------------------------------------------------------------- - slack 0.555 + slack 0.483 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] +Slack (MET) : 0.483ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -8246,61 +14898,39 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I + M22 f base_ram_data_IOBUF[31]_inst/OBUFT/I + M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 f base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.839 base_ram_data[31] + M22 f base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -8308,32 +14938,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.839 ------------------------------------------------------------------- - slack 0.555 + slack 0.483 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] +Slack (MET) : 0.483ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -8341,61 +14971,39 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) + 3.868 -2.408 + SLICE_X33Y88 FDRE 0.000 -2.408 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 f u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 f u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I + M22 f base_ram_data_IOBUF[31]_inst/OBUFT/I + M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 f base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.839 base_ram_data[31] + M22 f base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -8403,13691 +15011,32 @@ Slack (MET) : 0.555ns (required time - arrival time) propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 + required time 13.322 + arrival time -12.839 ------------------------------------------------------------------- - slack 0.555 + slack 0.483 -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 4.581ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.489ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) + Destination: ext_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.588ns (logic 0.606ns (4.154%) route 13.982ns (95.846%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.151ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.132ns = ( 17.868 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22095,46 +15044,90 @@ Slack (MET) : 4.581ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 10.475 12.101 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X85Y50 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T + AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.833 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.542 17.868 - clock pessimism -0.507 17.361 - clock uncertainty -0.071 17.290 - SLICE_X85Y50 FDCE (Recov_fdce_C_CLR) -0.609 16.681 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 16.681 - arrival time -12.101 + required time 13.322 + arrival time -12.833 ------------------------------------------------------------------- - slack 4.581 + slack 0.489 -Slack (MET) : 5.171ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.489ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) + Destination: ext_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.003ns (logic 0.606ns (4.328%) route 13.397ns (95.672%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22142,46 +15135,90 @@ Slack (MET) : 5.171ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 9.890 11.515 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X77Y52 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T + AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.833 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.547 17.873 - clock pessimism -0.507 17.366 - clock uncertainty -0.071 17.295 - SLICE_X77Y52 FDCE (Recov_fdce_C_CLR) -0.609 16.686 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 16.686 - arrival time -11.515 + required time 13.322 + arrival time -12.833 ------------------------------------------------------------------- - slack 5.171 + slack 0.489 -Slack (MET) : 5.624ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.489ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) + Destination: ext_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.646ns (logic 0.606ns (4.441%) route 13.040ns (95.559%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22189,46 +15226,90 @@ Slack (MET) : 5.624ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 9.533 11.158 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X90Y57 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T + AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.833 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X90Y57 FDCE (Recov_fdce_C_CLR) -0.523 16.782 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 16.782 - arrival time -11.158 + required time 13.322 + arrival time -12.833 ------------------------------------------------------------------- - slack 5.624 + slack 0.489 -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.489ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) + Destination: ext_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22236,46 +15317,90 @@ Slack (MET) : 6.450ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T + AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.833 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.835 18.160 - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 + required time 13.322 + arrival time -12.833 ------------------------------------------------------------------- - slack 6.450 + slack 0.489 -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.489ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) + Destination: ext_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22283,46 +15408,90 @@ Slack (MET) : 6.450ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T + AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.833 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.835 18.160 - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 + required time 13.322 + arrival time -12.833 ------------------------------------------------------------------- - slack 6.450 + slack 0.489 -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.489ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) + Destination: ext_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22330,46 +15499,90 @@ Slack (MET) : 6.450ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T + AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.833 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.835 18.160 - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 + required time 13.322 + arrival time -12.833 ------------------------------------------------------------------- - slack 6.450 + slack 0.489 -Slack (MET) : 6.650ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.489ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) + Destination: ext_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22377,46 +15590,90 @@ Slack (MET) : 6.650ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T + AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.833 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 16.697 - arrival time -10.047 + required time 13.322 + arrival time -12.833 ------------------------------------------------------------------- - slack 6.650 + slack 0.489 -Slack (MET) : 6.650ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.489ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) + Destination: ext_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22424,46 +15681,90 @@ Slack (MET) : 6.650ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T + AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.833 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 16.697 - arrival time -10.047 + required time 13.322 + arrival time -12.833 ------------------------------------------------------------------- - slack 6.650 + slack 0.489 -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.489ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) + Destination: ext_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22471,46 +15772,90 @@ Slack (MET) : 6.654ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T + AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.833 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 13.322 + arrival time -12.833 ------------------------------------------------------------------- - slack 6.654 + slack 0.489 -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.489ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) + Destination: ext_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22518,46 +15863,90 @@ Slack (MET) : 6.654ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T + AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.833 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 13.322 + arrival time -12.833 ------------------------------------------------------------------- - slack 6.654 + slack 0.489 -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.508ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 15.143ns (logic 6.882ns (45.449%) route 8.261ns (54.551%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22565,46 +15954,90 @@ Slack (MET) : 6.654ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.595 9.272 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 12.815 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.815 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14] + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 13.322 + arrival time -12.815 ------------------------------------------------------------------- - slack 6.654 + slack 0.508 -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.508ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 15.143ns (logic 6.882ns (45.449%) route 8.261ns (54.551%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22612,9364 +16045,19871 @@ Slack (MET) : 6.654ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR + 3.947 -2.329 + SLICE_X7Y69 FDCE 0.000 -2.329 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.595 9.272 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 12.815 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.815 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 - ------------------------------------------------------------------- - slack 6.654 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.881ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5] - ------------------------------------------------------------------- - required time 16.983 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.881 - -Slack (MET) : 6.881ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg - ------------------------------------------------------------------- - required time 16.983 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.881 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7] - ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.967 - -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8] - ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.967 - -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9] - ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.967 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.136ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.561 - ------------------------------------------------------------------- - slack 7.136 - -Slack (MET) : 7.136ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.561 - ------------------------------------------------------------------- - slack 7.136 - -Slack (MET) : 7.143ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.414ns (logic 0.606ns (4.882%) route 11.808ns (95.118%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.301 9.926 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6] - ------------------------------------------------------------------- - required time 17.069 - arrival time -9.926 - ------------------------------------------------------------------- - slack 7.143 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.560 17.886 - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.560 17.886 - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.560 17.886 - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[2] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.560 17.886 - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[3] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.262ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[28]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%)) - Logic Levels: 1 (LUT1=1) + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.815 + ------------------------------------------------------------------- + slack 0.508 + +Slack (MET) : 0.737ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[28]/CLR + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2 + SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O + net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 + SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3 + SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O + net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4 + SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 propagated clock network latency - 3.553 17.879 - clock pessimism -0.507 17.372 - clock uncertainty -0.071 17.301 - SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[28] + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] ------------------------------------------------------------------- - required time 16.692 - arrival time -9.431 + required time 27.175 + arrival time -26.438 ------------------------------------------------------------------- - slack 7.262 + slack 0.737 -Slack (MET) : 7.262ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[29]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%)) - Logic Levels: 1 (LUT1=1) +Slack (MET) : 0.737ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[29]/CLR + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2 + SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O + net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 + SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3 + SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O + net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4 + SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 propagated clock network latency - 3.553 17.879 - clock pessimism -0.507 17.372 - clock uncertainty -0.071 17.301 - SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[29] + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] ------------------------------------------------------------------- - required time 16.692 - arrival time -9.431 + required time 27.175 + arrival time -26.438 ------------------------------------------------------------------- - slack 7.262 + slack 0.737 -Slack (MET) : 7.262ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[30]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%)) - Logic Levels: 1 (LUT1=1) +Slack (MET) : 0.737ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[30]/CLR + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2 + SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O + net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 + SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3 + SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O + net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4 + SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 propagated clock network latency - 3.553 17.879 - clock pessimism -0.507 17.372 - clock uncertainty -0.071 17.301 - SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[30] + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] ------------------------------------------------------------------- - required time 16.692 - arrival time -9.431 + required time 27.175 + arrival time -26.438 ------------------------------------------------------------------- - slack 7.262 + slack 0.737 -Slack (MET) : 7.262ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[31]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%)) - Logic Levels: 1 (LUT1=1) +Slack (MET) : 0.737ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[31]/CLR + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2 + SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O + net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 + SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3 + SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O + net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4 + SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 propagated clock network latency - 3.553 17.879 - clock pessimism -0.507 17.372 - clock uncertainty -0.071 17.301 - SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[31] + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] ------------------------------------------------------------------- - required time 16.692 - arrival time -9.431 + required time 27.175 + arrival time -26.438 ------------------------------------------------------------------- - slack 7.262 + slack 0.737 -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[24]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.737ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2 + SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O + net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 + SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3 + SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O + net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4 + SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] + ------------------------------------------------------------------- + required time 27.175 + arrival time -26.438 + ------------------------------------------------------------------- + slack 0.737 + +Slack (MET) : 0.737ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2 + SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O + net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 + SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3 + SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O + net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4 + SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] + ------------------------------------------------------------------- + required time 27.175 + arrival time -26.438 + ------------------------------------------------------------------- + slack 0.737 + +Slack (MET) : 0.737ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2 + SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O + net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 + SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3 + SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O + net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4 + SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] + ------------------------------------------------------------------- + required time 27.175 + arrival time -26.438 + ------------------------------------------------------------------- + slack 0.737 + +Slack (MET) : 0.737ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2 + SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O + net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 + SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3 + SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O + net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4 + SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] + ------------------------------------------------------------------- + required time 27.175 + arrival time -26.438 + ------------------------------------------------------------------- + slack 0.737 + +Slack (MET) : 0.737ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2 + SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O + net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 + SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3 + SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O + net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4 + SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] + ------------------------------------------------------------------- + required time 27.175 + arrival time -26.438 + ------------------------------------------------------------------- + slack 0.737 + +Slack (MET) : 0.737ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2 + SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O + net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 + SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3 + SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O + net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4 + SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] + ------------------------------------------------------------------- + required time 27.175 + arrival time -26.438 + ------------------------------------------------------------------- + slack 0.737 + +Slack (MET) : 0.754ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0 + SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O + net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 + SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3 + SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O + net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1 + SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O + net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.370 + ------------------------------------------------------------------- + slack 0.754 + +Slack (MET) : 0.754ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0 + SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O + net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 + SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3 + SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O + net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1 + SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O + net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.370 + ------------------------------------------------------------------- + slack 0.754 + +Slack (MET) : 0.754ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0 + SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O + net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 + SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3 + SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O + net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1 + SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O + net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.370 + ------------------------------------------------------------------- + slack 0.754 + +Slack (MET) : 0.754ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0 + SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O + net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 + SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3 + SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O + net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1 + SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O + net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.370 + ------------------------------------------------------------------- + slack 0.754 + +Slack (MET) : 0.754ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0 + SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O + net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 + SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3 + SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O + net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1 + SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O + net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.370 + ------------------------------------------------------------------- + slack 0.754 + +Slack (MET) : 0.754ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0 + SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O + net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 + SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3 + SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O + net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1 + SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O + net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.370 + ------------------------------------------------------------------- + slack 0.754 + +Slack (MET) : 0.754ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0 + SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O + net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 + SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3 + SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O + net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1 + SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O + net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.370 + ------------------------------------------------------------------- + slack 0.754 + +Slack (MET) : 0.754ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0 + SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O + net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 + SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3 + SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O + net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1 + SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O + net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.370 + ------------------------------------------------------------------- + slack 0.754 + +Slack (MET) : 0.754ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0 + SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O + net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 + SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3 + SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O + net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1 + SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O + net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.370 + ------------------------------------------------------------------- + slack 0.754 + +Slack (MET) : 0.754ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0 + SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O + net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 + SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3 + SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O + net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1 + SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O + net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.370 + ------------------------------------------------------------------- + slack 0.754 + +Slack (MET) : 0.793ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2 + SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O + net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 + SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3 + SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O + net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3 + SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] + ------------------------------------------------------------------- + required time 27.177 + arrival time -26.384 + ------------------------------------------------------------------- + slack 0.793 + +Slack (MET) : 0.793ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2 + SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O + net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 + SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3 + SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O + net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3 + SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] + ------------------------------------------------------------------- + required time 27.177 + arrival time -26.384 + ------------------------------------------------------------------- + slack 0.793 + +Slack (MET) : 0.793ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2 + SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O + net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 + SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3 + SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O + net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3 + SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] + ------------------------------------------------------------------- + required time 27.177 + arrival time -26.384 + ------------------------------------------------------------------- + slack 0.793 + +Slack (MET) : 0.793ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2 + SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O + net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 + SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3 + SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O + net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3 + SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] + ------------------------------------------------------------------- + required time 27.177 + arrival time -26.384 + ------------------------------------------------------------------- + slack 0.793 + +Slack (MET) : 0.793ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2 + SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O + net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 + SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3 + SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O + net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3 + SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] + ------------------------------------------------------------------- + required time 27.177 + arrival time -26.384 + ------------------------------------------------------------------- + slack 0.793 + +Slack (MET) : 0.793ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2 + SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O + net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 + SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3 + SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O + net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3 + SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] + ------------------------------------------------------------------- + required time 27.177 + arrival time -26.384 + ------------------------------------------------------------------- + slack 0.793 + +Slack (MET) : 0.793ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2 + SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O + net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 + SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3 + SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O + net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3 + SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] + ------------------------------------------------------------------- + required time 27.177 + arrival time -26.384 + ------------------------------------------------------------------- + slack 0.793 + +Slack (MET) : 0.793ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2 + SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O + net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 + SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3 + SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O + net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3 + SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] + ------------------------------------------------------------------- + required time 27.177 + arrival time -26.384 + ------------------------------------------------------------------- + slack 0.793 + +Slack (MET) : 0.793ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2 + SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O + net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 + SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3 + SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O + net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3 + SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] + ------------------------------------------------------------------- + required time 27.177 + arrival time -26.384 + ------------------------------------------------------------------- + slack 0.793 + +Slack (MET) : 0.793ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2 + SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O + net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 + SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3 + SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O + net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3 + SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] + ------------------------------------------------------------------- + required time 27.177 + arrival time -26.384 + ------------------------------------------------------------------- + slack 0.793 + +Slack (MET) : 0.803ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2 + SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O + net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 + SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1 + SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O + net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.322 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2 + SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O + net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 + SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1 + SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O + net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.322 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2 + SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O + net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 + SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1 + SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O + net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.322 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2 + SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O + net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 + SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1 + SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O + net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.322 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2 + SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O + net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 + SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1 + SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O + net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.322 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2 + SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O + net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 + SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1 + SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O + net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.322 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2 + SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O + net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 + SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1 + SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O + net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.322 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2 + SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O + net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 + SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1 + SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O + net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.322 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2 + SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O + net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 + SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1 + SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O + net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.322 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2 + SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O + net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 + SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1 + SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O + net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.322 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.804ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 + SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0 + SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0 + SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 + SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.172 + arrival time -26.369 + ------------------------------------------------------------------- + slack 0.804 + +Slack (MET) : 0.804ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 + SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0 + SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0 + SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 + SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.172 + arrival time -26.369 + ------------------------------------------------------------------- + slack 0.804 + +Slack (MET) : 0.804ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 + SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0 + SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0 + SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 + SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.172 + arrival time -26.369 + ------------------------------------------------------------------- + slack 0.804 + +Slack (MET) : 0.804ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 + SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0 + SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0 + SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 + SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.172 + arrival time -26.369 + ------------------------------------------------------------------- + slack 0.804 + +Slack (MET) : 0.804ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 + SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0 + SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0 + SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 + SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.172 + arrival time -26.369 + ------------------------------------------------------------------- + slack 0.804 + +Slack (MET) : 0.804ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 + SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0 + SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0 + SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 + SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.172 + arrival time -26.369 + ------------------------------------------------------------------- + slack 0.804 + +Slack (MET) : 0.804ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 + SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0 + SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0 + SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 + SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.172 + arrival time -26.369 + ------------------------------------------------------------------- + slack 0.804 + +Slack (MET) : 0.804ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 + SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0 + SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0 + SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 + SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.172 + arrival time -26.369 + ------------------------------------------------------------------- + slack 0.804 + +Slack (MET) : 0.804ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 + SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0 + SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0 + SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 + SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.172 + arrival time -26.369 + ------------------------------------------------------------------- + slack 0.804 + +Slack (MET) : 0.804ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 + SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0 + SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0 + SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 + SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.172 + arrival time -26.369 + ------------------------------------------------------------------- + slack 0.804 + +Slack (MET) : 0.863ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2 + SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O + net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 + SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2 + SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O + net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O + net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.311 + ------------------------------------------------------------------- + slack 0.863 + +Slack (MET) : 0.863ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2 + SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O + net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 + SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2 + SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O + net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O + net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.311 + ------------------------------------------------------------------- + slack 0.863 + +Slack (MET) : 0.863ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2 + SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O + net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 + SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2 + SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O + net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O + net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.311 + ------------------------------------------------------------------- + slack 0.863 + +Slack (MET) : 0.863ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2 + SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O + net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 + SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2 + SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O + net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O + net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.311 + ------------------------------------------------------------------- + slack 0.863 + +Slack (MET) : 0.863ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2 + SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O + net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 + SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2 + SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O + net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O + net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.311 + ------------------------------------------------------------------- + slack 0.863 + +Slack (MET) : 0.863ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2 + SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O + net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 + SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2 + SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O + net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O + net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.311 + ------------------------------------------------------------------- + slack 0.863 + +Slack (MET) : 0.863ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2 + SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O + net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 + SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2 + SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O + net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O + net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.311 + ------------------------------------------------------------------- + slack 0.863 + +Slack (MET) : 0.863ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2 + SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O + net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 + SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2 + SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O + net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O + net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.311 + ------------------------------------------------------------------- + slack 0.863 + +Slack (MET) : 0.863ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2 + SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O + net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 + SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2 + SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O + net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O + net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.311 + ------------------------------------------------------------------- + slack 0.863 + +Slack (MET) : 0.863ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2 + SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O + net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 + SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2 + SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O + net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 + SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O + net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.311 + ------------------------------------------------------------------- + slack 0.863 + +Slack (MET) : 0.865ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 + SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 + SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O + net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 + SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 + SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O + net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 + SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 + SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O + net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.261 + ------------------------------------------------------------------- + slack 0.865 + +Slack (MET) : 0.865ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 + SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 + SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O + net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 + SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 + SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O + net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 + SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 + SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O + net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.261 + ------------------------------------------------------------------- + slack 0.865 + +Slack (MET) : 0.865ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 + SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 + SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O + net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 + SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 + SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O + net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 + SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 + SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O + net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.261 + ------------------------------------------------------------------- + slack 0.865 + +Slack (MET) : 0.865ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 + SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 + SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O + net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 + SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 + SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O + net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 + SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 + SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O + net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.261 + ------------------------------------------------------------------- + slack 0.865 + +Slack (MET) : 0.865ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 + SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 + SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O + net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 + SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 + SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O + net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 + SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 + SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O + net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.261 + ------------------------------------------------------------------- + slack 0.865 + +Slack (MET) : 0.865ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 + SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 + SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O + net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 + SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 + SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O + net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 + SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 + SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O + net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.261 + ------------------------------------------------------------------- + slack 0.865 + +Slack (MET) : 0.865ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 + SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 + SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O + net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 + SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 + SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O + net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 + SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 + SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O + net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.261 + ------------------------------------------------------------------- + slack 0.865 + +Slack (MET) : 0.865ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 + SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 + SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O + net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 + SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 + SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O + net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 + SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 + SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O + net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.261 + ------------------------------------------------------------------- + slack 0.865 + +Slack (MET) : 0.865ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 + SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 + SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O + net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 + SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 + SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O + net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 + SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 + SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O + net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.261 + ------------------------------------------------------------------- + slack 0.865 + +Slack (MET) : 0.865ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 + SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 + SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O + net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 + SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 + SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O + net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 + SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 + SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O + net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.397 27.722 + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.261 + ------------------------------------------------------------------- + slack 0.865 + +Slack (MET) : 0.867ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5 + SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 + SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + ------------------------------------------------------------------- + required time 27.122 + arrival time -26.255 + ------------------------------------------------------------------- + slack 0.867 + +Slack (MET) : 0.867ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5 + SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 + SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + ------------------------------------------------------------------- + required time 27.122 + arrival time -26.255 + ------------------------------------------------------------------- + slack 0.867 + +Slack (MET) : 0.867ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5 + SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 + SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + ------------------------------------------------------------------- + required time 27.122 + arrival time -26.255 + ------------------------------------------------------------------- + slack 0.867 + +Slack (MET) : 0.867ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5 + SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 + SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + ------------------------------------------------------------------- + required time 27.122 + arrival time -26.255 + ------------------------------------------------------------------- + slack 0.867 + +Slack (MET) : 0.867ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5 + SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 + SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + ------------------------------------------------------------------- + required time 27.122 + arrival time -26.255 + ------------------------------------------------------------------- + slack 0.867 + +Slack (MET) : 0.867ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5 + SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 + SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + ------------------------------------------------------------------- + required time 27.122 + arrival time -26.255 + ------------------------------------------------------------------- + slack 0.867 + +Slack (MET) : 0.867ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5 + SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 + SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + ------------------------------------------------------------------- + required time 27.122 + arrival time -26.255 + ------------------------------------------------------------------- + slack 0.867 + +Slack (MET) : 0.867ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5 + SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 + SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + ------------------------------------------------------------------- + required time 27.122 + arrival time -26.255 + ------------------------------------------------------------------- + slack 0.867 + +Slack (MET) : 0.867ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5 + SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 + SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + ------------------------------------------------------------------- + required time 27.122 + arrival time -26.255 + ------------------------------------------------------------------- + slack 0.867 + +Slack (MET) : 0.867ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5 + SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 + SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.395 27.720 + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + ------------------------------------------------------------------- + required time 27.122 + arrival time -26.255 + ------------------------------------------------------------------- + slack 0.867 + +Slack (MET) : 0.894ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1 + SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2 + SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + ------------------------------------------------------------------- + required time 27.127 + arrival time -26.233 + ------------------------------------------------------------------- + slack 0.894 + +Slack (MET) : 0.894ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1 + SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2 + SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + ------------------------------------------------------------------- + required time 27.127 + arrival time -26.233 + ------------------------------------------------------------------- + slack 0.894 + +Slack (MET) : 0.894ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1 + SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2 + SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + ------------------------------------------------------------------- + required time 27.127 + arrival time -26.233 + ------------------------------------------------------------------- + slack 0.894 + +Slack (MET) : 0.894ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1 + SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2 + SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + ------------------------------------------------------------------- + required time 27.127 + arrival time -26.233 + ------------------------------------------------------------------- + slack 0.894 + +Slack (MET) : 0.894ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1 + SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2 + SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + ------------------------------------------------------------------- + required time 27.127 + arrival time -26.233 + ------------------------------------------------------------------- + slack 0.894 + +Slack (MET) : 0.894ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1 + SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2 + SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + ------------------------------------------------------------------- + required time 27.127 + arrival time -26.233 + ------------------------------------------------------------------- + slack 0.894 + +Slack (MET) : 0.894ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1 + SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2 + SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + ------------------------------------------------------------------- + required time 27.127 + arrival time -26.233 + ------------------------------------------------------------------- + slack 0.894 + +Slack (MET) : 0.894ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1 + SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2 + SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + ------------------------------------------------------------------- + required time 27.127 + arrival time -26.233 + ------------------------------------------------------------------- + slack 0.894 + +Slack (MET) : 0.894ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1 + SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2 + SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + ------------------------------------------------------------------- + required time 27.127 + arrival time -26.233 + ------------------------------------------------------------------- + slack 0.894 + +Slack (MET) : 0.894ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1 + SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2 + SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.398 27.723 + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + ------------------------------------------------------------------- + required time 27.127 + arrival time -26.233 + ------------------------------------------------------------------- + slack 0.894 + +Slack (MET) : 0.921ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0 + SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1 + SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2 + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.396 27.721 + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.204 + ------------------------------------------------------------------- + slack 0.921 + +Slack (MET) : 0.921ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0 + SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1 + SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2 + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.396 27.721 + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.204 + ------------------------------------------------------------------- + slack 0.921 + +Slack (MET) : 0.921ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0 + SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1 + SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2 + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.396 27.721 + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.204 + ------------------------------------------------------------------- + slack 0.921 + +Slack (MET) : 0.921ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0 + SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1 + SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2 + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.396 27.721 + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.204 + ------------------------------------------------------------------- + slack 0.921 + +Slack (MET) : 0.921ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0 + SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1 + SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2 + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.396 27.721 + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.204 + ------------------------------------------------------------------- + slack 0.921 + +Slack (MET) : 0.921ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0 + SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1 + SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2 + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.396 27.721 + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.204 + ------------------------------------------------------------------- + slack 0.921 + +Slack (MET) : 0.921ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0 + SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1 + SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2 + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.396 27.721 + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.204 + ------------------------------------------------------------------- + slack 0.921 + +Slack (MET) : 0.921ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0 + SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1 + SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2 + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.396 27.721 + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.204 + ------------------------------------------------------------------- + slack 0.921 + +Slack (MET) : 0.921ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0 + SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1 + SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2 + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.396 27.721 + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.204 + ------------------------------------------------------------------- + slack 0.921 + +Slack (MET) : 0.921ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.625 -2.651 + SLICE_X129Y140 FDRE 0.000 -2.651 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 r u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 r u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 f u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0 + SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1 + SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2 + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + clock source latency -5.674 24.326 + propagated clock network latency + 3.396 27.721 + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.204 + ------------------------------------------------------------------- + slack 0.921 + +Slack (MET) : 3.826ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.817ns (logic 0.642ns (7.282%) route 8.175ns (92.718%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[24]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.745 6.147 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X96Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[24] + 3.566 10.892 + clock pessimism -0.507 10.385 + clock uncertainty -0.093 10.292 + SLICE_X96Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.973 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 + required time 9.973 + arrival time -6.147 ------------------------------------------------------------------- - slack 7.267 + slack 3.826 -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[25]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 3.860ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.747ns (logic 0.642ns (7.340%) route 8.105ns (92.660%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.061ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.102ns = ( 10.898 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[25]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.675 6.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X104Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[25] + 3.572 10.898 + clock pessimism -0.507 10.391 + clock uncertainty -0.093 10.298 + SLICE_X104Y85 FDCE (Recov_fdce_C_CLR) -0.361 9.937 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 + required time 9.937 + arrival time -6.077 ------------------------------------------------------------------- - slack 7.267 + slack 3.860 -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[26]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 3.902ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.747ns (logic 0.642ns (7.340%) route 8.105ns (92.660%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.061ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.102ns = ( 10.898 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[26]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.675 6.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X104Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[26] + 3.572 10.898 + clock pessimism -0.507 10.391 + clock uncertainty -0.093 10.298 + SLICE_X104Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 + required time 9.979 + arrival time -6.077 ------------------------------------------------------------------- - slack 7.267 + slack 3.902 -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[27]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.068ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[27]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[27] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 + required time 9.883 + arrival time -5.815 ------------------------------------------------------------------- - slack 7.267 + slack 4.068 -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[28]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.068ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[28]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[28] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 + required time 9.883 + arrival time -5.815 ------------------------------------------------------------------- - slack 7.267 + slack 4.068 -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[29]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.068ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[29]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[29] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 + required time 9.883 + arrival time -5.815 ------------------------------------------------------------------- - slack 7.267 + slack 4.068 -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[30]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[30]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[30] + 3.563 10.889 + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 + required time 9.884 + arrival time -5.769 ------------------------------------------------------------------- - slack 7.267 + slack 4.115 -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[31]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[31]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[31] + 3.563 10.889 + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 + required time 9.884 + arrival time -5.769 ------------------------------------------------------------------- - slack 7.267 + slack 4.115 -Slack (MET) : 7.288ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[3]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.565 17.027 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[3] + 3.563 10.889 + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3] ------------------------------------------------------------------- - required time 17.027 - arrival time -9.740 + required time 9.884 + arrival time -5.769 ------------------------------------------------------------------- - slack 7.288 + slack 4.115 -Slack (MET) : 7.330ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[0]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[0] + 3.563 10.889 + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4] ------------------------------------------------------------------- - required time 17.069 - arrival time -9.740 + required time 9.884 + arrival time -5.769 ------------------------------------------------------------------- - slack 7.330 + slack 4.115 -Slack (MET) : 7.330ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[2]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[2] + 3.563 10.889 + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5] ------------------------------------------------------------------- - required time 17.069 - arrival time -9.740 + required time 9.884 + arrival time -5.769 ------------------------------------------------------------------- - slack 7.330 + slack 4.115 -Slack (MET) : 7.330ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[4]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[4] + 3.563 10.889 + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6] ------------------------------------------------------------------- - required time 17.069 - arrival time -9.740 + required time 9.884 + arrival time -5.769 ------------------------------------------------------------------- - slack 7.330 + slack 4.115 -Slack (MET) : 7.330ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.154ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[5]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X94Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[5] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X94Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6] ------------------------------------------------------------------- - required time 17.069 - arrival time -9.740 + required time 9.969 + arrival time -5.815 ------------------------------------------------------------------- - slack 7.330 + slack 4.154 -Slack (MET) : 7.345ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.154ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.206ns (logic 0.606ns (4.965%) route 11.600ns (95.035%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.230ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.751ns = ( 18.249 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.093 9.718 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X3Y3 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X94Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.924 18.249 - clock pessimism -0.507 17.743 - clock uncertainty -0.071 17.672 - SLICE_X3Y3 FDCE (Recov_fdce_C_CLR) -0.609 17.063 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X94Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8] ------------------------------------------------------------------- - required time 17.063 - arrival time -9.718 + required time 9.969 + arrival time -5.815 ------------------------------------------------------------------- - slack 7.345 + slack 4.154 -Slack (MET) : 7.388ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/bf1_count_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.159ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.160ns (logic 0.606ns (4.983%) route 11.554ns (95.017%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.227ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.754ns = ( 18.246 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.047 9.673 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X5Y8 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/bf1_count_reg[0]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X100Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.921 18.246 - clock pessimism -0.507 17.740 - clock uncertainty -0.071 17.669 - SLICE_X5Y8 FDCE (Recov_fdce_C_CLR) -0.609 17.060 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/bf1_count_reg[0] + 3.563 10.889 + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X100Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.928 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26] ------------------------------------------------------------------- - required time 17.060 - arrival time -9.673 + required time 9.928 + arrival time -5.769 ------------------------------------------------------------------- - slack 7.388 + slack 4.159 -Slack (MET) : 7.401ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[24]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.201ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.139ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[24]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X100Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.554 17.880 - clock pessimism -0.507 17.373 - clock uncertainty -0.071 17.302 - SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[24] + 3.563 10.889 + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X100Y86 FDCE (Recov_fdce_C_CLR) -0.319 9.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25] ------------------------------------------------------------------- - required time 16.693 - arrival time -9.293 + required time 9.970 + arrival time -5.769 ------------------------------------------------------------------- - slack 7.401 + slack 4.201 -Slack (MET) : 7.401ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[25]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.223ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.139ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[25]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.554 17.880 - clock pessimism -0.507 17.373 - clock uncertainty -0.071 17.302 - SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[25] + 3.565 10.891 + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24] ------------------------------------------------------------------- - required time 16.693 - arrival time -9.293 + required time 9.886 + arrival time -5.662 ------------------------------------------------------------------- - slack 7.401 + slack 4.223 -Slack (MET) : 7.401ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[26]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.223ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.139ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[26]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.554 17.880 - clock pessimism -0.507 17.373 - clock uncertainty -0.071 17.302 - SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[26] + 3.565 10.891 + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27] ------------------------------------------------------------------- - required time 16.693 - arrival time -9.293 + required time 9.886 + arrival time -5.662 ------------------------------------------------------------------- - slack 7.401 + slack 4.223 -Slack (MET) : 7.401ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[27]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.223ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.139ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[27]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.554 17.880 - clock pessimism -0.507 17.373 - clock uncertainty -0.071 17.302 - SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[27] + 3.565 10.891 + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4] ------------------------------------------------------------------- - required time 16.693 - arrival time -9.293 + required time 9.886 + arrival time -5.662 ------------------------------------------------------------------- - slack 7.401 + slack 4.223 -Slack (MET) : 7.407ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[20]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.223ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.137ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[20]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.556 17.882 - clock pessimism -0.507 17.375 - clock uncertainty -0.071 17.304 - SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[20] + 3.565 10.891 + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7] ------------------------------------------------------------------- - required time 16.695 - arrival time -9.289 + required time 9.886 + arrival time -5.662 ------------------------------------------------------------------- - slack 7.407 + slack 4.223 -Slack (MET) : 7.407ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[21]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.224ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.137ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[21]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.556 17.882 - clock pessimism -0.507 17.375 - clock uncertainty -0.071 17.304 - SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[21] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y98 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22] ------------------------------------------------------------------- - required time 16.695 - arrival time -9.289 + required time 9.883 + arrival time -5.659 ------------------------------------------------------------------- - slack 7.407 + slack 4.224 -Slack (MET) : 7.407ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[22]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.224ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.137ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[22]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.556 17.882 - clock pessimism -0.507 17.375 - clock uncertainty -0.071 17.304 - SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[22] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y98 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6] ------------------------------------------------------------------- - required time 16.695 - arrival time -9.289 + required time 9.883 + arrival time -5.659 ------------------------------------------------------------------- - slack 7.407 + slack 4.224 -Slack (MET) : 7.407ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[23]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.224ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.137ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[23]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.556 17.882 - clock pessimism -0.507 17.375 - clock uncertainty -0.071 17.304 - SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[23] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y98 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8] ------------------------------------------------------------------- - required time 16.695 - arrival time -9.289 + required time 9.883 + arrival time -5.659 ------------------------------------------------------------------- - slack 7.407 + slack 4.224 -Slack (MET) : 7.431ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.275ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.206ns (logic 0.606ns (4.965%) route 11.600ns (95.035%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.230ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.751ns = ( 18.249 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.093 9.718 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X2Y3 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.924 18.249 - clock pessimism -0.507 17.743 - clock uncertainty -0.071 17.672 - SLICE_X2Y3 FDCE (Recov_fdce_C_CLR) -0.523 17.149 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4] + 3.561 10.887 + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X99Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13] ------------------------------------------------------------------- - required time 17.149 - arrival time -9.718 + required time 9.882 + arrival time -5.607 ------------------------------------------------------------------- - slack 7.431 + slack 4.275 -Slack (MET) : 7.510ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/mu_do_en_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.275ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.038ns (logic 0.606ns (5.034%) route 11.432ns (94.966%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.925 9.551 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X5Y3 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/mu_do_en_reg/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.922 18.247 - clock pessimism -0.507 17.741 - clock uncertainty -0.071 17.670 - SLICE_X5Y3 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/mu_do_en_reg + 3.561 10.887 + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X99Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2] ------------------------------------------------------------------- - required time 17.061 - arrival time -9.551 + required time 9.882 + arrival time -5.607 ------------------------------------------------------------------- - slack 7.510 + slack 4.275 -Slack (MET) : 7.574ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[16]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.275ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[16]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[16] + 3.561 10.887 + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X99Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.122 + required time 9.882 + arrival time -5.607 ------------------------------------------------------------------- - slack 7.574 + slack 4.275 -Slack (MET) : 7.574ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[17]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.305ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.172ns (logic 0.642ns (7.856%) route 7.530ns (92.144%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.025ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 10.723 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[17]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.101 5.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y101 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[17] + 3.398 10.723 + clock pessimism -0.418 10.305 + clock uncertainty -0.093 10.212 + SLICE_X95Y101 FDCE (Recov_fdce_C_CLR) -0.405 9.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.122 + required time 9.807 + arrival time -5.503 ------------------------------------------------------------------- - slack 7.574 + slack 4.305 -Slack (MET) : 7.574ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[18]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.309ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[18]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[18] + 3.565 10.891 + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.122 + required time 9.972 + arrival time -5.662 ------------------------------------------------------------------- - slack 7.574 + slack 4.309 -Slack (MET) : 7.574ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[19]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.309ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[19]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[19] + 3.565 10.891 + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.122 + required time 9.972 + arrival time -5.662 ------------------------------------------------------------------- - slack 7.574 + slack 4.309 -Slack (MET) : 7.609ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.309ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2] + 3.565 10.891 + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5] ------------------------------------------------------------------- - required time 17.064 - arrival time -9.455 + required time 9.972 + arrival time -5.662 ------------------------------------------------------------------- - slack 7.609 + slack 4.309 -Slack (MET) : 7.609ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.309ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3] + 3.565 10.891 + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7] ------------------------------------------------------------------- - required time 17.064 - arrival time -9.455 + required time 9.972 + arrival time -5.662 ------------------------------------------------------------------- - slack 7.609 + slack 4.309 -Slack (MET) : 7.609ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.310ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X94Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X94Y98 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6] ------------------------------------------------------------------- - required time 17.064 - arrival time -9.455 + required time 9.969 + arrival time -5.659 ------------------------------------------------------------------- - slack 7.609 + slack 4.310 -Slack (MET) : 7.609ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.319ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9] + 3.561 10.887 + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.361 9.926 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19] ------------------------------------------------------------------- - required time 17.064 - arrival time -9.455 + required time 9.926 + arrival time -5.607 ------------------------------------------------------------------- - slack 7.609 + slack 4.319 -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.319ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[5]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[5] + 3.561 10.887 + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.361 9.926 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2] ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 + required time 9.926 + arrival time -5.607 ------------------------------------------------------------------- - slack 7.637 + slack 4.319 -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.361ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[6]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[6] + 3.561 10.887 + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.319 9.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12] ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 + required time 9.968 + arrival time -5.607 ------------------------------------------------------------------- - slack 7.637 + slack 4.361 -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.361ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[7]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[7] + 3.561 10.887 + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.319 9.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29] ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 + required time 9.968 + arrival time -5.607 ------------------------------------------------------------------- - slack 7.637 + slack 4.361 -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.382ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.173ns (logic 0.642ns (7.855%) route 7.531ns (92.145%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[8]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.101 5.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[8] + 3.564 10.890 + clock pessimism -0.507 10.383 + clock uncertainty -0.093 10.290 + SLICE_X103Y84 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25] ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 + required time 9.885 + arrival time -5.503 ------------------------------------------------------------------- - slack 7.637 + slack 4.382 -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.382ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.173ns (logic 0.642ns (7.855%) route 7.531ns (92.145%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[9]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.101 5.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[9] + 3.564 10.890 + clock pessimism -0.507 10.383 + clock uncertainty -0.093 10.290 + SLICE_X103Y84 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6] ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 + required time 9.885 + arrival time -5.503 ------------------------------------------------------------------- - slack 7.637 + slack 4.382 -Slack (MET) : 7.638ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.406ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.958ns (logic 0.606ns (5.068%) route 11.352ns (94.932%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.845 9.470 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X2Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X2Y1 FDCE (Recov_fdce_C_CLR) -0.565 17.108 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25] ------------------------------------------------------------------- - required time 17.108 - arrival time -9.470 + required time 9.881 + arrival time -5.475 ------------------------------------------------------------------- - slack 7.638 + slack 4.406 -Slack (MET) : 7.638ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.406ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.958ns (logic 0.606ns (5.068%) route 11.352ns (94.932%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.845 9.470 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X2Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[3]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X2Y1 FDCE (Recov_fdce_C_CLR) -0.565 17.108 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[3] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28] ------------------------------------------------------------------- - required time 17.108 - arrival time -9.470 + required time 9.881 + arrival time -5.475 ------------------------------------------------------------------- - slack 7.638 + slack 4.406 -Slack (MET) : 7.641ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.406ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.911ns (logic 0.606ns (5.088%) route 11.305ns (94.912%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.798 9.423 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X1Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[4]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[4] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2] ------------------------------------------------------------------- - required time 17.064 - arrival time -9.423 + required time 9.881 + arrival time -5.475 ------------------------------------------------------------------- - slack 7.641 + slack 4.406 -Slack (MET) : 7.668ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.406ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.881ns (logic 0.606ns (5.101%) route 11.275ns (94.899%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.768 9.393 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X5Y6 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[0]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.922 18.247 - clock pessimism -0.507 17.741 - clock uncertainty -0.071 17.670 - SLICE_X5Y6 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[0] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3] ------------------------------------------------------------------- - required time 17.061 - arrival time -9.393 + required time 9.881 + arrival time -5.475 ------------------------------------------------------------------- - slack 7.668 + slack 4.406 -Slack (MET) : 7.668ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.420ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.881ns (logic 0.606ns (5.101%) route 11.275ns (94.899%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.768 9.393 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X5Y6 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[1]/CLR + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.922 18.247 - clock pessimism -0.507 17.741 - clock uncertainty -0.071 17.670 - SLICE_X5Y6 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[1] + 3.564 10.890 + clock pessimism -0.507 10.383 + clock uncertainty -0.093 10.290 + SLICE_X101Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12] ------------------------------------------------------------------- - required time 17.061 - arrival time -9.393 + required time 9.885 + arrival time -5.465 ------------------------------------------------------------------- - slack 7.668 + slack 4.420 -Slack (MET) : 7.668ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 4.420ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.881ns (logic 0.606ns (5.101%) route 11.275ns (94.899%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.768 9.393 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X5Y6 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.922 18.247 - clock pessimism -0.507 17.741 - clock uncertainty -0.071 17.670 - SLICE_X5Y6 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[2] - ------------------------------------------------------------------- - required time 17.061 - arrival time -9.393 - ------------------------------------------------------------------- - slack 7.668 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + 3.564 10.890 + clock pessimism -0.507 10.383 + clock uncertainty -0.093 10.290 + SLICE_X101Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20] ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 + required time 9.885 + arrival time -5.465 ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- + slack 4.420 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns +Slack (MET) : 4.420ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + 3.564 10.890 + clock pessimism -0.507 10.383 + clock uncertainty -0.093 10.290 + SLICE_X101Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3] ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 + required time 9.885 + arrival time -5.465 ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns + slack 4.420 - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns +Slack (MET) : 4.430ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2] ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 + required time 9.881 + arrival time -5.450 ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- + slack 4.430 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns +Slack (MET) : 4.430ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31] ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 + required time 9.881 + arrival time -5.450 ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- + slack 4.430 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns +Slack (MET) : 4.430ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7] ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 + required time 9.881 + arrival time -5.450 ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- + slack 4.430 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns +Slack (MET) : 4.430ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8] ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 + required time 9.881 + arrival time -5.450 ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- + slack 4.430 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns +Slack (MET) : 4.450ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X98Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.925 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3] ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 + required time 9.925 + arrival time -5.475 ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- + slack 4.450 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns +Slack (MET) : 4.450ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][4]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][4]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X98Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.925 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][4] ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 + required time 9.925 + arrival time -5.475 ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- + slack 4.450 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns +Slack (MET) : 4.474ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][9]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X96Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][9]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X96Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.925 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][9] ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 + required time 9.925 + arrival time -5.450 ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- + slack 4.474 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns +Slack (MET) : 4.479ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][10]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.066ns (logic 0.642ns (7.959%) route 7.424ns (92.041%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.044ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.995 5.397 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X89Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][10]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] + 3.555 10.881 + clock pessimism -0.507 10.374 + clock uncertainty -0.093 10.281 + SLICE_X89Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][10] ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 + required time 9.876 + arrival time -5.397 ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns + slack 4.479 - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns +Slack (MET) : 4.479ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][13]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.066ns (logic 0.642ns (7.959%) route 7.424ns (92.041%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.044ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.995 5.397 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X89Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][13]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] + 3.555 10.881 + clock pessimism -0.507 10.374 + clock uncertainty -0.093 10.281 + SLICE_X89Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][13] ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 + required time 9.876 + arrival time -5.397 ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- + slack 4.479 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns +Slack (MET) : 4.479ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][5]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.066ns (logic 0.642ns (7.959%) route 7.424ns (92.041%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.044ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.995 5.397 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X89Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][5]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 3.555 10.881 + clock pessimism -0.507 10.374 + clock uncertainty -0.093 10.281 + SLICE_X89Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][5] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 + required time 9.876 + arrival time -5.397 ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- + slack 4.479 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns +Slack (MET) : 4.492ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][27]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][27]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X98Y86 FDCE (Recov_fdce_C_CLR) -0.319 9.967 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][27] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 + required time 9.967 + arrival time -5.475 ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- + slack 4.492 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns +Slack (MET) : 4.492ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][28]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][28]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X98Y86 FDCE (Recov_fdce_C_CLR) -0.319 9.967 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][28] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 + required time 9.967 + arrival time -5.475 ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- + slack 4.492 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns +Slack (MET) : 4.506ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][12]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X100Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][12]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] + 3.564 10.890 + clock pessimism -0.507 10.383 + clock uncertainty -0.093 10.290 + SLICE_X100Y87 FDCE (Recov_fdce_C_CLR) -0.319 9.971 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][12] ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 + required time 9.971 + arrival time -5.465 ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- + slack 4.506 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns +Slack (MET) : 4.506ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][4]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X100Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][4]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] + 3.564 10.890 + clock pessimism -0.507 10.383 + clock uncertainty -0.093 10.290 + SLICE_X100Y87 FDCE (Recov_fdce_C_CLR) -0.319 9.971 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][4] ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 + required time 9.971 + arrival time -5.465 ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- + slack 4.506 - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns +Slack (MET) : 4.508ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][12]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.044ns (logic 0.642ns (7.981%) route 7.402ns (92.019%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.973 5.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][12]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y97 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][12] ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 + required time 9.883 + arrival time -5.375 ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.508 + +Slack (MET) : 4.508ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][4]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.044ns (logic 0.642ns (7.981%) route 7.402ns (92.019%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.973 5.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][4]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y97 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][4] ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 + required time 9.883 + arrival time -5.375 ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.508 + +Slack (MET) : 4.512ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][31]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.127ns (logic 0.642ns (7.900%) route 7.485ns (92.100%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.055 5.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X100Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][31]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X100Y84 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][31] ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 + required time 9.969 + arrival time -5.457 ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.512 + +Slack (MET) : 4.512ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][4]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.127ns (logic 0.642ns (7.900%) route 7.485ns (92.100%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.055 5.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X100Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][4]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X100Y84 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][4] ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 + required time 9.969 + arrival time -5.457 ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.512 + +Slack (MET) : 4.512ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.127ns (logic 0.642ns (7.900%) route 7.485ns (92.100%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.055 5.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X100Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][6]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X100Y84 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][6] ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 + required time 9.969 + arrival time -5.457 ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.512 + +Slack (MET) : 4.516ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][18]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X96Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][18]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X96Y86 FDCE (Recov_fdce_C_CLR) -0.319 9.967 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][18] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 + required time 9.967 + arrival time -5.450 ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.516 + +Slack (MET) : 4.545ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][18]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.003ns (logic 0.642ns (8.022%) route 7.361ns (91.978%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.117ns = ( 10.883 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.931 5.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][18]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 3.557 10.883 + clock pessimism -0.507 10.376 + clock uncertainty -0.093 10.283 + SLICE_X95Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.878 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][18] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 + required time 9.878 + arrival time -5.333 ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.545 + +Slack (MET) : 4.545ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][19]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.003ns (logic 0.642ns (8.022%) route 7.361ns (91.978%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.117ns = ( 10.883 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.931 5.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][19]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 3.557 10.883 + clock pessimism -0.507 10.376 + clock uncertainty -0.093 10.283 + SLICE_X95Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.878 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][19] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 + required time 9.878 + arrival time -5.333 ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.545 + +Slack (MET) : 4.551ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][10]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.994ns (logic 0.642ns (8.031%) route 7.352ns (91.969%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.044ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.922 5.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X89Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][10]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 3.555 10.881 + clock pessimism -0.507 10.374 + clock uncertainty -0.093 10.281 + SLICE_X89Y97 FDCE (Recov_fdce_C_CLR) -0.405 9.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][10] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 + required time 9.876 + arrival time -5.325 ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.551 + +Slack (MET) : 4.551ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][5]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.994ns (logic 0.642ns (8.031%) route 7.352ns (91.969%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.044ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.922 5.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X89Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][5]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 3.555 10.881 + clock pessimism -0.507 10.374 + clock uncertainty -0.093 10.281 + SLICE_X89Y97 FDCE (Recov_fdce_C_CLR) -0.405 9.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][5] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 + required time 9.876 + arrival time -5.325 ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.551 + +Slack (MET) : 4.565ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][14]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.066ns (logic 0.642ns (7.959%) route 7.424ns (92.041%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.044ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.995 5.397 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X88Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][14]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + 3.555 10.881 + clock pessimism -0.507 10.374 + clock uncertainty -0.093 10.281 + SLICE_X88Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.962 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][14] ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 + required time 9.962 + arrival time -5.397 ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.565 + +Slack (MET) : 4.565ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][2]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.066ns (logic 0.642ns (7.959%) route 7.424ns (92.041%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.044ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.995 5.397 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X88Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][2]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.555 10.881 + clock pessimism -0.507 10.374 + clock uncertainty -0.093 10.281 + SLICE_X88Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.962 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][2] ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 + required time 9.962 + arrival time -5.397 ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.565 + +Slack (MET) : 4.566ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][31]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.027ns (logic 0.642ns (7.998%) route 7.385ns (92.002%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.048ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.115ns = ( 10.885 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.955 5.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][31]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.559 10.885 + clock pessimism -0.507 10.378 + clock uncertainty -0.093 10.285 + SLICE_X98Y84 FDCE (Recov_fdce_C_CLR) -0.361 9.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][31] ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 + required time 9.924 + arrival time -5.358 ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.566 + +Slack (MET) : 4.566ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][3]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.027ns (logic 0.642ns (7.998%) route 7.385ns (92.002%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.048ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.115ns = ( 10.885 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.955 5.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][3]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.559 10.885 + clock pessimism -0.507 10.378 + clock uncertainty -0.093 10.285 + SLICE_X98Y84 FDCE (Recov_fdce_C_CLR) -0.361 9.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][3] ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 + required time 9.924 + arrival time -5.358 ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.566 + +Slack (MET) : 4.566ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.027ns (logic 0.642ns (7.998%) route 7.385ns (92.002%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.048ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.115ns = ( 10.885 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.955 5.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][6]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.559 10.885 + clock pessimism -0.507 10.378 + clock uncertainty -0.093 10.285 + SLICE_X98Y84 FDCE (Recov_fdce_C_CLR) -0.361 9.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][6] ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 + required time 9.924 + arrival time -5.358 ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.566 + +Slack (MET) : 4.594ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][20]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.047ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X91Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][20]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.558 10.884 + clock pessimism -0.507 10.377 + clock uncertainty -0.093 10.284 + SLICE_X91Y94 FDCE (Recov_fdce_C_CLR) -0.405 9.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][20] ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 + required time 9.879 + arrival time -5.285 ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.594 + +Slack (MET) : 4.594ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][21]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.047ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X91Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][21]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + 3.558 10.884 + clock pessimism -0.507 10.377 + clock uncertainty -0.093 10.284 + SLICE_X91Y94 FDCE (Recov_fdce_C_CLR) -0.405 9.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][21] ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 + required time 9.879 + arrival time -5.285 ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.594 + +Slack (MET) : 4.594ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][23]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.047ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X91Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][23]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] + 3.558 10.884 + clock pessimism -0.507 10.377 + clock uncertainty -0.093 10.284 + SLICE_X91Y94 FDCE (Recov_fdce_C_CLR) -0.405 9.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][23] ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 + required time 9.879 + arrival time -5.285 ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.594 + +Slack (MET) : 4.594ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][7]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.047ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X91Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][7]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] + 3.558 10.884 + clock pessimism -0.507 10.377 + clock uncertainty -0.093 10.284 + SLICE_X91Y94 FDCE (Recov_fdce_C_CLR) -0.405 9.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][7] ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 + required time 9.879 + arrival time -5.285 ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.594 + +Slack (MET) : 4.594ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][12]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.044ns (logic 0.642ns (7.981%) route 7.402ns (92.019%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.973 5.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X94Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][12]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X94Y97 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][12] ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 + required time 9.969 + arrival time -5.375 ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.594 + +Slack (MET) : 4.594ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][15]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.044ns (logic 0.642ns (7.981%) route 7.402ns (92.019%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.973 5.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X94Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][15]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X94Y97 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][15] ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 + required time 9.969 + arrival time -5.375 ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.594 + +Slack (MET) : 4.594ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][22]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.044ns (logic 0.642ns (7.981%) route 7.402ns (92.019%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.973 5.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X94Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][22]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X94Y97 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][22] ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 + required time 9.969 + arrival time -5.375 ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.594 + +Slack (MET) : 4.594ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.044ns (logic 0.642ns (7.981%) route 7.402ns (92.019%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.973 5.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X94Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][6]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] + 3.562 10.888 + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X94Y97 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][6] ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 + required time 9.969 + arrival time -5.375 ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.594 + +Slack (MET) : 4.608ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][25]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.027ns (logic 0.642ns (7.998%) route 7.385ns (92.002%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.048ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.115ns = ( 10.885 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.955 5.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][25]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] + 3.559 10.885 + clock pessimism -0.507 10.378 + clock uncertainty -0.093 10.285 + SLICE_X98Y84 FDCE (Recov_fdce_C_CLR) -0.319 9.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][25] ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 + required time 9.966 + arrival time -5.358 ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.608 + +Slack (MET) : 4.608ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][28]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.027ns (logic 0.642ns (7.998%) route 7.385ns (92.002%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.048ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.115ns = ( 10.885 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.955 5.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][28]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] + 3.559 10.885 + clock pessimism -0.507 10.378 + clock uncertainty -0.093 10.285 + SLICE_X98Y84 FDCE (Recov_fdce_C_CLR) -0.319 9.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][28] ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 + required time 9.966 + arrival time -5.358 ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.608 + +Slack (MET) : 4.608ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][2]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.027ns (logic 0.642ns (7.998%) route 7.385ns (92.002%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.048ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.115ns = ( 10.885 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.955 5.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][2]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.559 10.885 + clock pessimism -0.507 10.378 + clock uncertainty -0.093 10.285 + SLICE_X98Y84 FDCE (Recov_fdce_C_CLR) -0.319 9.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][2] ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 + required time 9.966 + arrival time -5.358 ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.608 + +Slack (MET) : 4.637ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][10]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.994ns (logic 0.642ns (8.031%) route 7.352ns (91.969%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.044ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.922 5.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X88Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][10]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.555 10.881 + clock pessimism -0.507 10.374 + clock uncertainty -0.093 10.281 + SLICE_X88Y97 FDCE (Recov_fdce_C_CLR) -0.319 9.962 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][10] ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 + required time 9.962 + arrival time -5.325 ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.637 + +Slack (MET) : 4.637ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][5]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.994ns (logic 0.642ns (8.031%) route 7.352ns (91.969%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.044ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.119ns = ( 10.881 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.922 5.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X88Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][5]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.555 10.881 + clock pessimism -0.507 10.374 + clock uncertainty -0.093 10.281 + SLICE_X88Y97 FDCE (Recov_fdce_C_CLR) -0.319 9.962 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][5] ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 + required time 9.962 + arrival time -5.325 ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.637 + +Slack (MET) : 4.651ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][27]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.890ns (logic 0.642ns (8.137%) route 7.248ns (91.863%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.039ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.124ns = ( 10.876 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.818 5.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X89Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][27]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.550 10.876 + clock pessimism -0.507 10.369 + clock uncertainty -0.093 10.276 + SLICE_X89Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.871 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][27] ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 + required time 9.871 + arrival time -5.220 ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.651 + +Slack (MET) : 4.651ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][28]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.890ns (logic 0.642ns (8.137%) route 7.248ns (91.863%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.039ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.124ns = ( 10.876 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.818 5.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X89Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][28]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.550 10.876 + clock pessimism -0.507 10.369 + clock uncertainty -0.093 10.276 + SLICE_X89Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.871 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][28] ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 + required time 9.871 + arrival time -5.220 ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + slack 4.651 + +Slack (MET) : 4.663ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][18]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.883ns (logic 0.642ns (8.144%) route 7.241ns (91.856%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.045ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.118ns = ( 10.882 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.812 5.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][18]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + 3.556 10.882 + clock pessimism -0.507 10.375 + clock uncertainty -0.093 10.282 + SLICE_X95Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.877 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][18] ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 + required time 9.877 + arrival time -5.214 ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.663 + +Slack (MET) : 4.672ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][18]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.878ns (logic 0.642ns (8.149%) route 7.236ns (91.851%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.806 5.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X97Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][18]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X97Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][18] ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 + required time 9.881 + arrival time -5.209 ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.672 + +Slack (MET) : 4.672ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][9]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.878ns (logic 0.642ns (8.149%) route 7.236ns (91.851%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.806 5.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X97Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][9]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] + 3.560 10.886 + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X97Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][9] ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 + required time 9.881 + arrival time -5.209 ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.672 + +Slack (MET) : 4.673ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][12]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.884ns (logic 0.642ns (8.143%) route 7.242ns (91.857%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.812 5.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][12]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] + 3.566 10.892 + clock pessimism -0.507 10.385 + clock uncertainty -0.093 10.292 + SLICE_X101Y89 FDCE (Recov_fdce_C_CLR) -0.405 9.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][12] ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 + required time 9.887 + arrival time -5.214 ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.673 + +Slack (MET) : 4.673ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][13]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.884ns (logic 0.642ns (8.143%) route 7.242ns (91.857%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.812 5.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][13]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] + 3.566 10.892 + clock pessimism -0.507 10.385 + clock uncertainty -0.093 10.292 + SLICE_X101Y89 FDCE (Recov_fdce_C_CLR) -0.405 9.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][13] ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 + required time 9.887 + arrival time -5.214 ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.673 + +Slack (MET) : 4.673ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][19]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.884ns (logic 0.642ns (8.143%) route 7.242ns (91.857%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.812 5.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][19]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] + 3.566 10.892 + clock pessimism -0.507 10.385 + clock uncertainty -0.093 10.292 + SLICE_X101Y89 FDCE (Recov_fdce_C_CLR) -0.405 9.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][19] ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 + required time 9.887 + arrival time -5.214 ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.673 + +Slack (MET) : 4.673ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][20]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.884ns (logic 0.642ns (8.143%) route 7.242ns (91.857%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.812 5.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][20]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] + 3.566 10.892 + clock pessimism -0.507 10.385 + clock uncertainty -0.093 10.292 + SLICE_X101Y89 FDCE (Recov_fdce_C_CLR) -0.405 9.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][20] ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 + required time 9.887 + arrival time -5.214 ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.673 + +Slack (MET) : 4.680ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][20]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.047ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X90Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][20]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] + 3.558 10.884 + clock pessimism -0.507 10.377 + clock uncertainty -0.093 10.284 + SLICE_X90Y94 FDCE (Recov_fdce_C_CLR) -0.319 9.965 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][20] ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 + required time 9.965 + arrival time -5.285 ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.680 + +Slack (MET) : 4.680ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][21]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.047ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X90Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][21]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] + 3.558 10.884 + clock pessimism -0.507 10.377 + clock uncertainty -0.093 10.284 + SLICE_X90Y94 FDCE (Recov_fdce_C_CLR) -0.319 9.965 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][21] ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 + required time 9.965 + arrival time -5.285 ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.680 + +Slack (MET) : 4.680ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][24]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.954ns (logic 0.642ns (8.071%) route 7.312ns (91.929%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.047ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.116ns = ( 10.884 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.883 5.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X90Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][24]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] + 3.558 10.884 + clock pessimism -0.507 10.377 + clock uncertainty -0.093 10.284 + SLICE_X90Y94 FDCE (Recov_fdce_C_CLR) -0.319 9.965 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][24] ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 + required time 9.965 + arrival time -5.285 ------------------------------------------------------------------- - slack 11.519 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + slack 4.680 + +Slack (MET) : 4.680ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][14]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 7.852ns (logic 0.642ns (8.176%) route 7.210ns (91.824%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.031ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.132ns = ( 10.868 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D + 3.606 -2.670 + SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 4.781 5.183 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X86Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][14]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 + (clock mlkem_clk rise edge) + 13.000 13.000 r + clock source latency -5.674 7.326 propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] + 3.542 10.868 + clock pessimism -0.507 10.361 + clock uncertainty -0.093 10.268 + SLICE_X86Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.863 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[6][14] ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 + required time 9.863 + arrival time -5.183 ------------------------------------------------------------------- - slack 11.519 + slack 4.680 diff --git a/fpga/vivado_reports_nodsp/timing_summary_full.rpt b/fpga/vivado_reports_nodsp/timing_summary_full.rpt index ef11c9c..8e258e4 100644 --- a/fpga/vivado_reports_nodsp/timing_summary_full.rpt +++ b/fpga/vivado_reports_nodsp/timing_summary_full.rpt @@ -1,13 +1,13 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:10 2026 +| Date : Sat Jul 11 09:34:15 2026 | Host : fedora running 64-bit unknown -| Command : report_timing_summary -delay_type max -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/vivado_reports_nodsp/timing_summary_full.rpt +| Command : report_timing_summary -delay_type max -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_summary_full.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report @@ -208,7 +208,7 @@ video_vsync WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 0.167 0.000 0 115177 7.000 0.000 0 42610 + 0.070 0.000 0 88843 5.250 0.000 0 33736 All user specified timing constraints are met. @@ -219,13 +219,13 @@ All user specified timing constraints are met. | ------------- ------------------------------------------------------------------------------------------------ -Clock Waveform(ns) Period(ns) Frequency(MHz) ------ ------------ ---------- -------------- -clk {0.000 10.000} 20.000 50.000 - clkfbout_clk_pll {0.000 10.000} 20.000 50.000 - cpu_clk {0.000 15.161} 30.323 32.979 - mlkem_clk_clk_pll {0.000 20.000} 40.000 25.000 - sys_clk {0.000 10.000} 20.000 50.000 +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 10.000} 20.000 50.000 + clkfbout_clk_pll {0.000 10.000} 20.000 50.000 + cpu_clk {0.000 15.000} 30.000 33.333 + mlkem_clk {0.000 6.500} 13.000 76.923 + sys_clk {0.000 10.000} 20.000 50.000 ------------------------------------------------------------------------------------------------ @@ -233,13 +233,13 @@ clk {0.000 10.000} 20.000 50.000 | ----------------- ------------------------------------------------------------------------------------------------ -Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------ ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -clk 7.000 0.000 0 1 - clkfbout_clk_pll 17.845 0.000 0 3 - cpu_clk 2.716 0.000 0 17197 13.911 0.000 0 6486 - mlkem_clk_clk_pll 10.807 0.000 0 48474 18.750 0.000 0 26131 - sys_clk 0.167 0.000 0 22818 8.750 0.000 0 9989 +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 7.000 0.000 0 1 + clkfbout_clk_pll 17.845 0.000 0 3 + cpu_clk 0.737 0.000 0 17197 13.750 0.000 0 6486 + mlkem_clk 0.070 0.000 0 31646 5.250 0.000 0 17274 + sys_clk 0.125 0.000 0 22307 8.750 0.000 0 9972 ------------------------------------------------------------------------------------------------ @@ -247,10 +247,8 @@ clk | ----------------- ------------------------------------------------------------------------------------------------ -From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ----------- -------- ------- ------- --------------------- ------------------- -sys_clk mlkem_clk_clk_pll 14.363 0.000 0 108 -mlkem_clk_clk_pll sys_clk 16.175 0.000 0 59 +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ @@ -260,11 +258,9 @@ mlkem_clk_clk_pll sys_clk 16.175 0.000 Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- -**async_default** cpu_clk cpu_clk 25.793 0.000 0 67 -**async_default** mlkem_clk_clk_pll mlkem_clk_clk_pll 23.497 0.000 0 25694 -**async_default** sys_clk mlkem_clk_clk_pll 9.156 0.000 0 4 -**async_default** mlkem_clk_clk_pll sys_clk 11.249 0.000 0 2 -**async_default** sys_clk sys_clk 4.581 0.000 0 886 +**async_default** cpu_clk cpu_clk 26.018 0.000 0 67 +**async_default** mlkem_clk mlkem_clk 3.826 0.000 0 16740 +**async_default** sys_clk sys_clk 6.335 0.000 0 886 ------------------------------------------------------------------------------------------------ @@ -275,7 +271,9 @@ Path Group From Clock To Clock WNS(ns) TNS(ns Path Group From Clock To Clock ---------- ---------- -------- (none) sys_clk cpu_clk +(none) sys_clk mlkem_clk (none) cpu_clk sys_clk +(none) mlkem_clk sys_clk ------------------------------------------------------------------------------------------------ @@ -353,2382 +351,31 @@ Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 From Clock: cpu_clk To Clock: cpu_clk -Setup : 0 Failing Endpoints, Worst Slack 2.716ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 0.737ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 13.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.966 28.460 u_cpu/exe_stage/cpu_clk - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/C - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.975 28.469 u_cpu/exe_stage/cpu_clk - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/C - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.885 28.379 u_cpu/exe_stage/cpu_clk - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/C - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.959ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.468ns (logic 7.073ns (25.750%) route 20.395ns (74.250%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O - net (fo=20, routed) 0.780 22.220 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 - SLICE_X42Y31 LUT6 (Prop_lut6_I0_O) 0.124 22.344 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O - net (fo=27, routed) 1.068 23.412 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 - SLICE_X45Y35 LUT4 (Prop_lut4_I2_O) 0.150 23.562 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O - net (fo=1, routed) 1.078 24.640 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 - SLICE_X39Y34 LUT6 (Prop_lut6_I1_O) 0.326 24.966 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O - net (fo=1, routed) 0.000 24.966 u_cpu/exe_stage/ds_to_es_bus[118] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.975 28.469 u_cpu/exe_stage/cpu_clk - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/C - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.029 27.926 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] - ------------------------------------------------------------------- - required time 27.926 - arrival time -24.966 - ------------------------------------------------------------------- - slack 2.959 - -Slack (MET) : 3.081ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.303ns (logic 7.073ns (25.905%) route 20.230ns (74.095%)) - Logic Levels: 32 (CARRY4=5 LUT3=2 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.059ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.945ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 1.096 21.904 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y31 LUT6 (Prop_lut6_I5_O) 0.124 22.028 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_19/O - net (fo=4, routed) 0.942 22.969 u_cpu/id_stage/ds_to_es_bus_r[188]_i_19_n_0 - SLICE_X43Y28 LUT3 (Prop_lut3_I2_O) 0.150 23.119 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_11/O - net (fo=1, routed) 0.652 23.771 u_cpu/id_stage/ds_to_es_bus_r[181]_i_11_n_0 - SLICE_X43Y28 LUT6 (Prop_lut6_I5_O) 0.326 24.097 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O - net (fo=1, routed) 0.581 24.678 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 - SLICE_X46Y28 LUT6 (Prop_lut6_I3_O) 0.124 24.802 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O - net (fo=1, routed) 0.000 24.802 u_cpu/exe_stage/ds_to_es_bus[131] - SLICE_X46Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_cpu/exe_stage/cpu_clk - SLICE_X46Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/C - clock pessimism -0.498 27.880 - clock uncertainty -0.074 27.806 - SLICE_X46Y28 FDRE (Setup_fdre_C_D) 0.077 27.883 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] - ------------------------------------------------------------------- - required time 27.883 - arrival time -24.802 - ------------------------------------------------------------------- - slack 3.081 - -Slack (MET) : 3.101ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.282ns (logic 6.845ns (25.090%) route 20.437ns (74.910%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O - net (fo=20, routed) 0.619 22.058 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 - SLICE_X41Y30 LUT6 (Prop_lut6_I0_O) 0.124 22.182 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O - net (fo=15, routed) 1.068 23.250 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 - SLICE_X43Y32 LUT4 (Prop_lut4_I2_O) 0.124 23.374 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_2/O - net (fo=1, routed) 1.282 24.656 u_cpu/id_stage/ds_to_es_bus_r[176]_i_2_n_0 - SLICE_X46Y24 LUT6 (Prop_lut6_I1_O) 0.124 24.780 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O - net (fo=1, routed) 0.000 24.780 u_cpu/exe_stage/ds_to_es_bus[126] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.081 27.882 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] - ------------------------------------------------------------------- - required time 27.882 - arrival time -24.780 - ------------------------------------------------------------------- - slack 3.101 - -Slack (MET) : 3.107ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.229ns (logic 6.845ns (25.138%) route 20.384ns (74.862%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.057ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.947ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.277 23.041 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X51Y27 LUT4 (Prop_lut4_I2_O) 0.124 23.165 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_12/O - net (fo=1, routed) 0.649 23.814 u_cpu/id_stage/ds_to_es_bus_r[186]_i_12_n_0 - SLICE_X47Y27 LUT5 (Prop_lut5_I0_O) 0.124 23.938 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_5/O - net (fo=1, routed) 0.666 24.604 u_cpu/id_stage/ds_to_es_bus_r[186]_i_5_n_0 - SLICE_X45Y27 LUT6 (Prop_lut6_I4_O) 0.124 24.728 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O - net (fo=1, routed) 0.000 24.728 u_cpu/exe_stage/ds_to_es_bus[136] - SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_cpu/exe_stage/cpu_clk - SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/C - clock pessimism -0.498 27.878 - clock uncertainty -0.074 27.804 - SLICE_X45Y27 FDRE (Setup_fdre_C_D) 0.031 27.835 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] - ------------------------------------------------------------------- - required time 27.835 - arrival time -24.728 - ------------------------------------------------------------------- - slack 3.107 - -Slack (MET) : 3.111ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.278ns (logic 6.845ns (25.094%) route 20.433ns (74.906%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.064ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.940ns = ( 28.383 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.127 22.946 u_cpu/id_stage/fs_to_ds_bus_r_reg[46]_0 - SLICE_X48Y33 LUT4 (Prop_lut4_I0_O) 0.124 23.070 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O - net (fo=1, routed) 0.656 23.726 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 - SLICE_X46Y30 LUT6 (Prop_lut6_I1_O) 0.124 23.850 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O - net (fo=1, routed) 0.803 24.652 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 - SLICE_X44Y33 LUT6 (Prop_lut6_I4_O) 0.124 24.776 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O - net (fo=1, routed) 0.000 24.776 u_cpu/exe_stage/ds_to_es_bus[117] - SLICE_X44Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.889 28.383 u_cpu/exe_stage/cpu_clk - SLICE_X44Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/C - clock pessimism -0.498 27.885 - clock uncertainty -0.074 27.811 - SLICE_X44Y33 FDRE (Setup_fdre_C_D) 0.077 27.888 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] - ------------------------------------------------------------------- - required time 27.888 - arrival time -24.776 - ------------------------------------------------------------------- - slack 3.111 - -Slack (MET) : 3.117ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.301ns (logic 7.095ns (25.988%) route 20.206ns (74.012%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O - net (fo=20, routed) 0.780 22.220 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 - SLICE_X42Y31 LUT6 (Prop_lut6_I0_O) 0.124 22.344 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O - net (fo=27, routed) 0.883 23.227 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 - SLICE_X44Y32 LUT2 (Prop_lut2_I1_O) 0.150 23.377 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O - net (fo=1, routed) 1.075 24.452 u_cpu/id_stage/ds_to_es_bus_r_reg[171] - SLICE_X41Y26 LUT6 (Prop_lut6_I2_O) 0.348 24.800 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O - net (fo=1, routed) 0.000 24.800 u_cpu/exe_stage/ds_to_es_bus[121] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.966 28.460 u_cpu/exe_stage/cpu_clk - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/C - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.029 27.917 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] - ------------------------------------------------------------------- - required time 27.917 - arrival time -24.800 - ------------------------------------------------------------------- - slack 3.117 - -Slack (MET) : 3.132ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.293ns (logic 7.073ns (25.915%) route 20.220ns (74.085%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 0.818 22.446 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X40Y24 LUT5 (Prop_lut5_I0_O) 0.326 22.772 r u_cpu/u_csr/ds_to_es_bus_r[187]_i_11/O - net (fo=1, routed) 0.976 23.747 u_cpu/id_stage/ds_to_es_bus_r_reg[187]_0 - SLICE_X40Y30 LUT4 (Prop_lut4_I2_O) 0.124 23.871 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O - net (fo=1, routed) 0.796 24.668 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 - SLICE_X41Y31 LUT6 (Prop_lut6_I4_O) 0.124 24.792 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O - net (fo=1, routed) 0.000 24.792 u_cpu/exe_stage/ds_to_es_bus[137] - SLICE_X41Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.971 28.465 u_cpu/exe_stage/cpu_clk - SLICE_X41Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/C - clock pessimism -0.498 27.967 - clock uncertainty -0.074 27.893 - SLICE_X41Y31 FDRE (Setup_fdre_C_D) 0.031 27.924 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] - ------------------------------------------------------------------- - required time 27.924 - arrival time -24.792 - ------------------------------------------------------------------- - slack 3.132 - -Slack (MET) : 3.146ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.188ns (logic 6.949ns (25.559%) route 20.239ns (74.441%)) - Logic Levels: 31 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.847 20.893 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y30 LUT5 (Prop_lut5_I2_O) 0.124 21.017 f u_cpu/id_stage/ds_to_es_bus_r[183]_i_15/O - net (fo=8, routed) 1.169 22.186 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_1 - SLICE_X44Y30 LUT2 (Prop_lut2_I1_O) 0.148 22.334 f u_cpu/id_stage/ds_to_es_bus_r[183]_i_12/O - net (fo=6, routed) 0.893 23.226 u_cpu/id_stage/ds_to_es_bus_r[183]_i_12_n_0 - SLICE_X41Y29 LUT6 (Prop_lut6_I3_O) 0.328 23.554 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_3/O - net (fo=1, routed) 1.008 24.562 u_cpu/id_stage/ds_to_es_bus_r[180]_i_3_n_0 - SLICE_X43Y26 LUT6 (Prop_lut6_I2_O) 0.124 24.686 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O - net (fo=1, routed) 0.000 24.686 u_cpu/exe_stage/ds_to_es_bus[130] - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X43Y26 FDRE (Setup_fdre_C_D) 0.032 27.833 u_cpu/exe_stage/ds_to_es_bus_r_reg[180] - ------------------------------------------------------------------- - required time 27.833 - arrival time -24.686 - ------------------------------------------------------------------- - slack 3.146 - -Slack (MET) : 3.154ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.182ns (logic 6.845ns (25.182%) route 20.337ns (74.818%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.057ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.947ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.745 21.553 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I3_O) 0.124 21.677 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O - net (fo=32, routed) 1.325 23.002 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 - SLICE_X46Y27 LUT4 (Prop_lut4_I0_O) 0.124 23.126 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_10/O - net (fo=1, routed) 0.502 23.627 u_cpu/id_stage/ds_to_es_bus_r[185]_i_10_n_0 - SLICE_X46Y27 LUT6 (Prop_lut6_I5_O) 0.124 23.751 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_4/O - net (fo=1, routed) 0.805 24.556 u_cpu/id_stage/ds_to_es_bus_r[185]_i_4_n_0 - SLICE_X45Y27 LUT6 (Prop_lut6_I3_O) 0.124 24.680 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O - net (fo=1, routed) 0.000 24.680 u_cpu/exe_stage/ds_to_es_bus[135] - SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_cpu/exe_stage/cpu_clk - SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/C - clock pessimism -0.498 27.878 - clock uncertainty -0.074 27.804 - SLICE_X45Y27 FDRE (Setup_fdre_C_D) 0.031 27.835 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] - ------------------------------------------------------------------- - required time 27.835 - arrival time -24.680 - ------------------------------------------------------------------- - slack 3.154 - -Slack (MET) : 3.179ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.737ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.162ns (logic 6.845ns (25.201%) route 20.317ns (74.799%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.064ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.940ns = ( 28.383 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -2742,120 +389,903 @@ Slack (MET) : 3.179ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.745 21.553 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I3_O) 0.124 21.677 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O - net (fo=32, routed) 1.184 22.860 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 - SLICE_X46Y31 LUT4 (Prop_lut4_I0_O) 0.124 22.984 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_13/O - net (fo=1, routed) 0.785 23.769 u_cpu/id_stage/ds_to_es_bus_r[189]_i_13_n_0 - SLICE_X47Y33 LUT6 (Prop_lut6_I5_O) 0.124 23.893 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_4/O - net (fo=1, routed) 0.643 24.536 u_cpu/id_stage/ds_to_es_bus_r[189]_i_4_n_0 - SLICE_X47Y33 LUT6 (Prop_lut6_I3_O) 0.124 24.660 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O - net (fo=1, routed) 0.000 24.660 u_cpu/exe_stage/ds_to_es_bus[139] - SLICE_X47Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O + net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 + SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O + net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 + SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.889 28.383 u_cpu/exe_stage/cpu_clk - SLICE_X47Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/C - clock pessimism -0.498 27.885 - clock uncertainty -0.074 27.811 - SLICE_X47Y33 FDRE (Setup_fdre_C_D) 0.029 27.840 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] ------------------------------------------------------------------- - required time 27.840 - arrival time -24.660 + required time 27.175 + arrival time -26.438 ------------------------------------------------------------------- - slack 3.179 + slack 0.737 -Slack (MET) : 3.179ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.754ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O + net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 + SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O + net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 + SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O + net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.370 + ------------------------------------------------------------------- + slack 0.754 + +Slack (MET) : 0.793ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O + net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 + SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O + net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 + SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] + ------------------------------------------------------------------- + required time 27.177 + arrival time -26.384 + ------------------------------------------------------------------- + slack 0.793 + +Slack (MET) : 0.803ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O + net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 + SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O + net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.322 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.804ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 + SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.172 + arrival time -26.369 + ------------------------------------------------------------------- + slack 0.804 + +Slack (MET) : 0.863ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 + SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O + net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 + SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O + net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O + net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.311 + ------------------------------------------------------------------- + slack 0.863 + +Slack (MET) : 0.865ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 + SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O + net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 + SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O + net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 + SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O + net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] + ------------------------------------------------------------------- + required time 27.126 + arrival time -26.261 + ------------------------------------------------------------------- + slack 0.865 + +Slack (MET) : 0.867ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.160ns (logic 7.073ns (26.042%) route 20.087ns (73.958%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -2869,120 +1299,123 @@ Slack (MET) : 3.179ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 1.194 22.822 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X50Y28 LUT6 (Prop_lut6_I0_O) 0.326 23.148 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O - net (fo=1, routed) 0.700 23.848 u_cpu/id_stage/ds_to_es_bus_r_reg[190] - SLICE_X47Y30 LUT6 (Prop_lut6_I2_O) 0.124 23.972 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O - net (fo=1, routed) 0.562 24.534 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 - SLICE_X45Y29 LUT5 (Prop_lut5_I1_O) 0.124 24.658 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O - net (fo=1, routed) 0.000 24.658 u_cpu/exe_stage/ds_to_es_bus[140] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.885 28.379 u_cpu/exe_stage/cpu_clk - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/C - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.031 27.838 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk + SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- - required time 27.838 - arrival time -24.658 + required time 27.122 + arrival time -26.255 ------------------------------------------------------------------- - slack 3.179 + slack 0.867 -Slack (MET) : 3.222ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.894ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.251ns (logic 6.845ns (25.118%) route 20.406ns (74.882%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -2996,120 +1429,123 @@ Slack (MET) : 3.222ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 0.885 22.649 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X39Y35 LUT4 (Prop_lut4_I2_O) 0.124 22.773 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_9/O - net (fo=1, routed) 1.128 23.901 u_cpu/id_stage/ds_to_es_bus_r[162]_i_9_n_0 - SLICE_X39Y33 LUT6 (Prop_lut6_I2_O) 0.124 24.025 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_4/O - net (fo=1, routed) 0.600 24.625 u_cpu/id_stage/ds_to_es_bus_r[162]_i_4_n_0 - SLICE_X40Y32 LUT6 (Prop_lut6_I2_O) 0.124 24.749 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_1/O - net (fo=1, routed) 0.000 24.749 u_cpu/exe_stage/ds_to_es_bus[112] - SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk - SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/C - clock pessimism -0.498 27.969 - clock uncertainty -0.074 27.895 - SLICE_X40Y32 FDRE (Setup_fdre_C_D) 0.077 27.972 u_cpu/exe_stage/ds_to_es_bus_r_reg[162] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] ------------------------------------------------------------------- - required time 27.972 - arrival time -24.749 + required time 27.127 + arrival time -26.233 ------------------------------------------------------------------- - slack 3.222 + slack 0.894 -Slack (MET) : 3.225ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.921ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.158ns (logic 6.845ns (25.204%) route 20.313ns (74.796%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.058ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.377 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -3123,1945 +1559,123 @@ Slack (MET) : 3.225ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.499 21.307 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT5 (Prop_lut5_I4_O) 0.124 21.431 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O - net (fo=12, routed) 1.248 22.679 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 - SLICE_X48Y34 LUT4 (Prop_lut4_I2_O) 0.124 22.803 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_8/O - net (fo=1, routed) 0.983 23.787 u_cpu/id_stage/ds_to_es_bus_r[163]_i_8_n_0 - SLICE_X42Y34 LUT6 (Prop_lut6_I0_O) 0.124 23.911 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_4/O - net (fo=1, routed) 0.622 24.533 u_cpu/id_stage/ds_to_es_bus_r[163]_i_4_n_0 - SLICE_X42Y29 LUT6 (Prop_lut6_I3_O) 0.124 24.657 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_1/O - net (fo=1, routed) 0.000 24.657 u_cpu/exe_stage/ds_to_es_bus[113] - SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.883 28.377 u_cpu/exe_stage/cpu_clk - SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/C - clock pessimism -0.498 27.879 - clock uncertainty -0.074 27.805 - SLICE_X42Y29 FDRE (Setup_fdre_C_D) 0.077 27.882 u_cpu/exe_stage/ds_to_es_bus_r_reg[163] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/C + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] ------------------------------------------------------------------- - required time 27.882 - arrival time -24.657 + required time 27.125 + arrival time -26.204 ------------------------------------------------------------------- - slack 3.225 + slack 0.921 -Slack (MET) : 3.228ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.103ns (logic 7.041ns (25.978%) route 20.062ns (74.021%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.499 21.307 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT5 (Prop_lut5_I4_O) 0.124 21.431 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O - net (fo=12, routed) 0.831 22.262 u_cpu/u_csr/ds_to_es_bus_r[166]_i_4_0 - SLICE_X45Y31 LUT2 (Prop_lut2_I1_O) 0.118 22.380 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_8/O - net (fo=1, routed) 0.965 23.345 u_cpu/u_csr/ds_to_es_bus_r[165]_i_8_n_0 - SLICE_X42Y28 LUT6 (Prop_lut6_I0_O) 0.326 23.671 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O - net (fo=1, routed) 0.806 24.478 u_cpu/id_stage/ds_to_es_bus_r_reg[165] - SLICE_X43Y26 LUT6 (Prop_lut6_I3_O) 0.124 24.602 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O - net (fo=1, routed) 0.000 24.602 u_cpu/exe_stage/ds_to_es_bus[115] - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X43Y26 FDRE (Setup_fdre_C_D) 0.029 27.830 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] - ------------------------------------------------------------------- - required time 27.830 - arrival time -24.602 - ------------------------------------------------------------------- - slack 3.228 - -Slack (MET) : 3.306ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.027ns (logic 6.845ns (25.326%) route 20.182ns (74.674%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.269 23.016 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y27 LUT4 (Prop_lut4_I0_O) 0.124 23.140 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_11/O - net (fo=1, routed) 0.487 23.627 u_cpu/id_stage/ds_to_es_bus_r[174]_i_11_n_0 - SLICE_X45Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.751 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_4/O - net (fo=1, routed) 0.651 24.402 u_cpu/id_stage/ds_to_es_bus_r[174]_i_4_n_0 - SLICE_X43Y26 LUT6 (Prop_lut6_I3_O) 0.124 24.526 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O - net (fo=1, routed) 0.000 24.526 u_cpu/exe_stage/ds_to_es_bus[124] - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X43Y26 FDRE (Setup_fdre_C_D) 0.031 27.832 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] - ------------------------------------------------------------------- - required time 27.832 - arrival time -24.526 - ------------------------------------------------------------------- - slack 3.306 - -Slack (MET) : 3.315ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.066ns (logic 6.845ns (25.290%) route 20.221ns (74.710%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.056ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.948ns = ( 28.375 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.494 21.302 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y28 LUT6 (Prop_lut6_I5_O) 0.124 21.426 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_12/O - net (fo=11, routed) 1.101 22.527 u_cpu/id_stage/ds_to_es_bus_r[178]_i_12_n_0 - SLICE_X46Y22 LUT5 (Prop_lut5_I2_O) 0.124 22.651 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_10/O - net (fo=1, routed) 0.985 23.636 u_cpu/id_stage/ds_to_es_bus_r[178]_i_10_n_0 - SLICE_X46Y26 LUT6 (Prop_lut6_I2_O) 0.124 23.760 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O - net (fo=1, routed) 0.680 24.440 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 - SLICE_X46Y26 LUT6 (Prop_lut6_I3_O) 0.124 24.564 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O - net (fo=1, routed) 0.000 24.564 u_cpu/exe_stage/ds_to_es_bus[128] - SLICE_X46Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.881 28.375 u_cpu/exe_stage/cpu_clk - SLICE_X46Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/C - clock pessimism -0.498 27.877 - clock uncertainty -0.074 27.803 - SLICE_X46Y26 FDRE (Setup_fdre_C_D) 0.077 27.880 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] - ------------------------------------------------------------------- - required time 27.880 - arrival time -24.564 - ------------------------------------------------------------------- - slack 3.315 - -Slack (MET) : 3.348ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.129ns (logic 6.845ns (25.231%) route 20.284ns (74.769%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X44Y31 LUT4 (Prop_lut4_I0_O) 0.124 23.189 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_7/O - net (fo=1, routed) 0.553 23.742 u_cpu/id_stage/ds_to_es_bus_r[166]_i_7_n_0 - SLICE_X40Y31 LUT5 (Prop_lut5_I0_O) 0.124 23.866 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_3/O - net (fo=1, routed) 0.638 24.504 u_cpu/id_stage/ds_to_es_bus_r[166]_i_3_n_0 - SLICE_X40Y32 LUT6 (Prop_lut6_I2_O) 0.124 24.628 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_1/O - net (fo=1, routed) 0.000 24.628 u_cpu/exe_stage/ds_to_es_bus[116] - SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk - SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/C - clock pessimism -0.498 27.969 - clock uncertainty -0.074 27.895 - SLICE_X40Y32 FDRE (Setup_fdre_C_D) 0.081 27.976 u_cpu/exe_stage/ds_to_es_bus_r_reg[166] - ------------------------------------------------------------------- - required time 27.976 - arrival time -24.628 - ------------------------------------------------------------------- - slack 3.348 - -Slack (MET) : 3.380ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.001ns (logic 6.845ns (25.351%) route 20.156ns (74.649%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O - net (fo=20, routed) 0.619 22.058 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 - SLICE_X41Y30 LUT6 (Prop_lut6_I0_O) 0.124 22.182 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O - net (fo=15, routed) 1.094 23.277 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 - SLICE_X47Y33 LUT6 (Prop_lut6_I5_O) 0.124 23.401 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_2/O - net (fo=1, routed) 0.974 24.375 u_cpu/id_stage/ds_to_es_bus_r[179]_i_2_n_0 - SLICE_X46Y24 LUT5 (Prop_lut5_I1_O) 0.124 24.499 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_1/O - net (fo=1, routed) 0.000 24.499 u_cpu/exe_stage/ds_to_es_bus[129] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.079 27.880 u_cpu/exe_stage/ds_to_es_bus_r_reg[179] - ------------------------------------------------------------------- - required time 27.880 - arrival time -24.499 - ------------------------------------------------------------------- - slack 3.380 - -Slack (MET) : 3.393ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][10]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][10]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][10]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][10] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.239 - ------------------------------------------------------------------- - slack 3.393 - -Slack (MET) : 3.393ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][18]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][18]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][18]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][18] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.239 - ------------------------------------------------------------------- - slack 3.393 - -Slack (MET) : 3.393ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][23]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][23]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][23]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][23] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.239 - ------------------------------------------------------------------- - slack 3.393 - -Slack (MET) : 3.393ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][27]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][27]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][27]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][27] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.239 - ------------------------------------------------------------------- - slack 3.393 - -Slack (MET) : 3.408ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.974ns (logic 7.073ns (26.222%) route 19.901ns (73.778%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.057ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.947ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 1.025 22.652 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X45Y28 LUT5 (Prop_lut5_I0_O) 0.326 22.978 r u_cpu/u_csr/ds_to_es_bus_r[182]_i_8/O - net (fo=1, routed) 0.653 23.631 u_cpu/id_stage/ds_to_es_bus_r_reg[182] - SLICE_X44Y28 LUT6 (Prop_lut6_I1_O) 0.124 23.755 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_2/O - net (fo=1, routed) 0.593 24.348 u_cpu/id_stage/ds_to_es_bus_r[182]_i_2_n_0 - SLICE_X44Y27 LUT6 (Prop_lut6_I1_O) 0.124 24.472 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_1/O - net (fo=1, routed) 0.000 24.472 u_cpu/exe_stage/ds_to_es_bus[132] - SLICE_X44Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_cpu/exe_stage/cpu_clk - SLICE_X44Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/C - clock pessimism -0.498 27.878 - clock uncertainty -0.074 27.804 - SLICE_X44Y27 FDRE (Setup_fdre_C_D) 0.077 27.881 u_cpu/exe_stage/ds_to_es_bus_r_reg[182] - ------------------------------------------------------------------- - required time 27.881 - arrival time -24.472 - ------------------------------------------------------------------- - slack 3.408 - -Slack (MET) : 3.421ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][29]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][29]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][29]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][29] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.210 - ------------------------------------------------------------------- - slack 3.421 - -Slack (MET) : 3.421ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][2]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][2]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][2]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][2] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.210 - ------------------------------------------------------------------- - slack 3.421 - -Slack (MET) : 3.421ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][4]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][4]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][4]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][4] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.210 - ------------------------------------------------------------------- - slack 3.421 - -Slack (MET) : 3.421ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][7]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][7]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][7]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][7] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.210 - ------------------------------------------------------------------- - slack 3.421 - -Slack (MET) : 3.432ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.954ns (logic 7.073ns (26.241%) route 19.881ns (73.759%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.061ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.943ns = ( 28.380 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 1.175 22.803 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X47Y31 LUT4 (Prop_lut4_I3_O) 0.326 23.129 r u_cpu/u_csr/ds_to_es_bus_r[188]_i_12/O - net (fo=1, routed) 0.667 23.796 u_cpu/id_stage/ds_to_es_bus_r_reg[188] - SLICE_X47Y31 LUT6 (Prop_lut6_I1_O) 0.124 23.920 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_5/O - net (fo=1, routed) 0.409 24.329 u_cpu/id_stage/ds_to_es_bus_r[188]_i_5_n_0 - SLICE_X48Y31 LUT6 (Prop_lut6_I4_O) 0.124 24.453 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_1/O - net (fo=1, routed) 0.000 24.453 u_cpu/exe_stage/ds_to_es_bus[138] - SLICE_X48Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.886 28.380 u_cpu/exe_stage/cpu_clk - SLICE_X48Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/C - clock pessimism -0.498 27.882 - clock uncertainty -0.074 27.808 - SLICE_X48Y31 FDRE (Setup_fdre_C_D) 0.077 27.885 u_cpu/exe_stage/ds_to_es_bus_r_reg[188] - ------------------------------------------------------------------- - required time 27.885 - arrival time -24.453 - ------------------------------------------------------------------- - slack 3.432 - -Slack (MET) : 3.450ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.943ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.937ns (logic 7.073ns (26.257%) route 19.864ns (73.743%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.058ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.377 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.831ns (logic 8.005ns (27.765%) route 20.826ns (72.235%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=9 LUT6=12 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -5075,120 +1689,123 @@ Slack (MET) : 3.450ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 0.952 22.579 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X42Y24 LUT5 (Prop_lut5_I1_O) 0.326 22.905 r u_cpu/u_csr/ds_to_es_bus_r[192]_i_9/O - net (fo=1, routed) 0.483 23.388 u_cpu/id_stage/ds_to_es_bus_r_reg[192] - SLICE_X42Y27 LUT4 (Prop_lut4_I3_O) 0.124 23.512 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_3/O - net (fo=1, routed) 0.800 24.312 u_cpu/id_stage/ds_to_es_bus_r[192]_i_3_n_0 - SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 24.436 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_1/O - net (fo=1, routed) 0.000 24.436 u_cpu/exe_stage/ds_to_es_bus[142] - SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.866 24.418 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 + SLICE_X115Y152 LUT5 (Prop_lut5_I0_O) 0.326 24.744 r u_cpu/u_csr/ds_to_es_bus_r[192]_i_9/O + net (fo=1, routed) 0.415 25.158 u_cpu/id_stage/ds_to_es_bus_r_reg[192] + SLICE_X111Y152 LUT4 (Prop_lut4_I3_O) 0.124 25.282 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_3/O + net (fo=1, routed) 0.775 26.057 u_cpu/id_stage/ds_to_es_bus_r[192]_i_3_n_0 + SLICE_X110Y159 LUT6 (Prop_lut6_I2_O) 0.124 26.181 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_1/O + net (fo=1, routed) 0.000 26.181 u_cpu/exe_stage/ds_to_es_bus[142] + SLICE_X110Y159 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.883 28.377 u_cpu/exe_stage/cpu_clk - SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/C - clock pessimism -0.498 27.879 - clock uncertainty -0.074 27.805 - SLICE_X42Y29 FDRE (Setup_fdre_C_D) 0.081 27.886 u_cpu/exe_stage/ds_to_es_bus_r_reg[192] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk + SLICE_X110Y159 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X110Y159 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[192] ------------------------------------------------------------------- - required time 27.886 - arrival time -24.436 + required time 27.124 + arrival time -26.181 ------------------------------------------------------------------- - slack 3.450 + slack 0.943 -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.964ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.862ns (logic 7.809ns (27.057%) route 21.053ns (72.943%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.138ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.275ns = ( 27.725 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -5202,1056 +1819,123 @@ Slack (MET) : 3.466ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][13]/CE + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 1.058 24.188 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_4 + SLICE_X103Y151 LUT4 (Prop_lut4_I2_O) 0.124 24.312 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_7/O + net (fo=1, routed) 0.590 24.902 u_cpu/id_stage/ds_to_es_bus_r[163]_i_7_n_0 + SLICE_X102Y150 LUT5 (Prop_lut5_I4_O) 0.124 25.026 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_3/O + net (fo=1, routed) 1.061 26.087 u_cpu/id_stage/ds_to_es_bus_r[163]_i_3_n_0 + SLICE_X112Y150 LUT6 (Prop_lut6_I2_O) 0.124 26.211 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_1/O + net (fo=1, routed) 0.000 26.211 u_cpu/exe_stage/ds_to_es_bus[113] + SLICE_X112Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][13]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][13] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.554 27.725 u_cpu/exe_stage/cpu_clk + SLICE_X112Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/C + clock pessimism -0.514 27.212 + clock uncertainty -0.113 27.098 + SLICE_X112Y150 FDRE (Setup_fdre_C_D) 0.077 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[163] ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 + required time 27.175 + arrival time -26.211 ------------------------------------------------------------------- - slack 3.466 + slack 0.964 -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][15]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][15] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][17]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][17]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][17]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][17] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][21]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][21]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][21]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][21] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][3]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][3]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][3]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][3] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][4]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][4]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][4]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][4] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][6]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][6]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][6]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][6] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][7]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][7]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][7]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][7] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.472ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.860ns (logic 6.845ns (25.484%) route 20.015ns (74.516%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.494 21.302 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y28 LUT6 (Prop_lut6_I5_O) 0.124 21.426 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_12/O - net (fo=11, routed) 1.266 22.692 u_cpu/id_stage/ds_to_es_bus_r[178]_i_12_n_0 - SLICE_X45Y19 LUT5 (Prop_lut5_I4_O) 0.124 22.816 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_7/O - net (fo=1, routed) 0.650 23.467 u_cpu/id_stage/ds_to_es_bus_r[169]_i_7_n_0 - SLICE_X45Y24 LUT5 (Prop_lut5_I2_O) 0.124 23.591 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_3/O - net (fo=1, routed) 0.643 24.234 u_cpu/id_stage/ds_to_es_bus_r[169]_i_3_n_0 - SLICE_X45Y24 LUT6 (Prop_lut6_I2_O) 0.124 24.358 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_1/O - net (fo=1, routed) 0.000 24.358 u_cpu/exe_stage/ds_to_es_bus[119] - SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X45Y24 FDRE (Setup_fdre_C_D) 0.029 27.830 u_cpu/exe_stage/ds_to_es_bus_r_reg[169] - ------------------------------------------------------------------- - required time 27.830 - arrival time -24.358 - ------------------------------------------------------------------- - slack 3.472 - -Slack (MET) : 3.473ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.965ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.860ns (logic 6.845ns (25.484%) route 20.015ns (74.516%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.812ns (logic 8.005ns (27.784%) route 20.807ns (72.216%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6265,120 +1949,123 @@ Slack (MET) : 3.473ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.494 21.302 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y28 LUT6 (Prop_lut6_I5_O) 0.124 21.426 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_12/O - net (fo=11, routed) 1.155 22.581 u_cpu/id_stage/ds_to_es_bus_r[178]_i_12_n_0 - SLICE_X42Y20 LUT5 (Prop_lut5_I4_O) 0.124 22.705 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O - net (fo=1, routed) 0.760 23.465 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 - SLICE_X42Y24 LUT5 (Prop_lut5_I0_O) 0.124 23.589 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O - net (fo=1, routed) 0.646 24.235 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 - SLICE_X45Y24 LUT6 (Prop_lut6_I3_O) 0.124 24.359 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O - net (fo=1, routed) 0.000 24.359 u_cpu/exe_stage/ds_to_es_bus[125] - SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O + net (fo=19, routed) 0.702 24.253 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 + SLICE_X114Y154 LUT4 (Prop_lut4_I0_O) 0.326 24.579 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_7/O + net (fo=1, routed) 0.772 25.352 u_cpu/id_stage/ds_to_es_bus_r[175]_i_7_n_0 + SLICE_X112Y154 LUT4 (Prop_lut4_I2_O) 0.124 25.476 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_3/O + net (fo=1, routed) 0.561 26.037 u_cpu/id_stage/ds_to_es_bus_r[175]_i_3_n_0 + SLICE_X111Y153 LUT6 (Prop_lut6_I2_O) 0.124 26.161 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O + net (fo=1, routed) 0.000 26.161 u_cpu/exe_stage/ds_to_es_bus[125] + SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X45Y24 FDRE (Setup_fdre_C_D) 0.031 27.832 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X111Y153 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- - required time 27.832 - arrival time -24.359 + required time 27.126 + arrival time -26.161 ------------------------------------------------------------------- - slack 3.473 + slack 0.965 -Slack (MET) : 3.482ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][26]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 1.001ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.650ns (logic 5.748ns (21.569%) route 20.902ns (78.431%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.089ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.915ns = ( 28.408 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.774ns (logic 7.809ns (27.139%) route 20.965ns (72.861%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6392,92 +2079,4695 @@ Slack (MET) : 3.482ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.872 24.148 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y41 FDRE r u_cpu/btb/btb_pc_reg[13][26]/CE + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.935 25.244 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X117Y151 LUT6 (Prop_lut6_I0_O) 0.124 25.368 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_2/O + net (fo=1, routed) 0.631 26.000 u_cpu/id_stage/ds_to_es_bus_r[178]_i_2_n_0 + SLICE_X110Y156 LUT6 (Prop_lut6_I1_O) 0.124 26.124 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O + net (fo=1, routed) 0.000 26.124 u_cpu/exe_stage/ds_to_es_bus[128] + SLICE_X110Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.914 28.408 u_cpu/btb/cpu_clk - SLICE_X114Y41 FDRE r u_cpu/btb/btb_pc_reg[13][26]/C - clock pessimism -0.498 27.910 - clock uncertainty -0.074 27.836 - SLICE_X114Y41 FDRE (Setup_fdre_C_CE) -0.205 27.631 u_cpu/btb/btb_pc_reg[13][26] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X110Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X110Y156 FDRE (Setup_fdre_C_D) 0.029 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- - required time 27.631 - arrival time -24.148 + required time 27.124 + arrival time -26.124 ------------------------------------------------------------------- - slack 3.482 + slack 1.001 + +Slack (MET) : 1.021ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.754ns (logic 7.809ns (27.158%) route 20.945ns (72.842%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X112Y150 LUT4 (Prop_lut4_I2_O) 0.124 25.241 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_2/O + net (fo=1, routed) 0.738 25.979 u_cpu/id_stage/ds_to_es_bus_r[170]_i_2_n_0 + SLICE_X111Y153 LUT6 (Prop_lut6_I1_O) 0.124 26.103 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O + net (fo=1, routed) 0.000 26.103 u_cpu/exe_stage/ds_to_es_bus[120] + SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X111Y153 FDRE (Setup_fdre_C_D) 0.029 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] + ------------------------------------------------------------------- + required time 27.124 + arrival time -26.103 + ------------------------------------------------------------------- + slack 1.021 + +Slack (MET) : 1.037ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.784ns (logic 8.012ns (27.834%) route 20.772ns (72.165%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.761 24.317 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X112Y155 LUT5 (Prop_lut5_I0_O) 0.332 24.649 r u_cpu/u_csr/ds_to_es_bus_r[182]_i_8/O + net (fo=1, routed) 0.667 25.316 u_cpu/id_stage/ds_to_es_bus_r_reg[182] + SLICE_X112Y154 LUT6 (Prop_lut6_I1_O) 0.124 25.440 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_2/O + net (fo=1, routed) 0.569 26.010 u_cpu/id_stage/ds_to_es_bus_r[182]_i_2_n_0 + SLICE_X108Y157 LUT6 (Prop_lut6_I1_O) 0.124 26.134 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_1/O + net (fo=1, routed) 0.000 26.134 u_cpu/exe_stage/ds_to_es_bus[132] + SLICE_X108Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk + SLICE_X108Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/C + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X108Y157 FDRE (Setup_fdre_C_D) 0.077 27.171 u_cpu/exe_stage/ds_to_es_bus_r_reg[182] + ------------------------------------------------------------------- + required time 27.171 + arrival time -26.134 + ------------------------------------------------------------------- + slack 1.037 + +Slack (MET) : 1.065ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.709ns (logic 7.809ns (27.200%) route 20.900ns (72.800%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.884 25.193 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X117Y153 LUT6 (Prop_lut6_I3_O) 0.124 25.317 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_3/O + net (fo=1, routed) 0.617 25.935 u_cpu/id_stage/ds_to_es_bus_r[187]_i_3_n_0 + SLICE_X111Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.059 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O + net (fo=1, routed) 0.000 26.059 u_cpu/exe_stage/ds_to_es_bus[137] + SLICE_X111Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk + SLICE_X111Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/C + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X111Y158 FDRE (Setup_fdre_C_D) 0.029 27.123 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] + ------------------------------------------------------------------- + required time 27.123 + arrival time -26.059 + ------------------------------------------------------------------- + slack 1.065 + +Slack (MET) : 1.081ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.695ns (logic 8.005ns (27.897%) route 20.690ns (72.103%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.124 23.557 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O + net (fo=12, routed) 0.657 24.214 u_cpu/u_csr/ds_to_es_bus_r[166]_i_4_0 + SLICE_X112Y151 LUT2 (Prop_lut2_I1_O) 0.116 24.330 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_8/O + net (fo=1, routed) 0.808 25.138 u_cpu/u_csr/ds_to_es_bus_r[165]_i_8_n_0 + SLICE_X111Y151 LUT6 (Prop_lut6_I0_O) 0.328 25.466 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O + net (fo=1, routed) 0.455 25.920 u_cpu/id_stage/ds_to_es_bus_r_reg[165] + SLICE_X109Y151 LUT6 (Prop_lut6_I3_O) 0.124 26.044 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O + net (fo=1, routed) 0.000 26.044 u_cpu/exe_stage/ds_to_es_bus[115] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.044 + ------------------------------------------------------------------- + slack 1.081 + +Slack (MET) : 1.086ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.690ns (logic 8.012ns (27.926%) route 20.678ns (72.074%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 0.950 24.506 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X115Y152 LUT5 (Prop_lut5_I1_O) 0.332 24.838 r u_cpu/u_csr/ds_to_es_bus_r[180]_i_8/O + net (fo=1, routed) 0.451 25.289 u_cpu/id_stage/ds_to_es_bus_r_reg[180] + SLICE_X113Y152 LUT6 (Prop_lut6_I1_O) 0.124 25.413 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_2/O + net (fo=1, routed) 0.502 25.916 u_cpu/id_stage/ds_to_es_bus_r[180]_i_2_n_0 + SLICE_X110Y158 LUT6 (Prop_lut6_I1_O) 0.124 26.040 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O + net (fo=1, routed) 0.000 26.040 u_cpu/exe_stage/ds_to_es_bus[130] + SLICE_X110Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk + SLICE_X110Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X110Y158 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[180] + ------------------------------------------------------------------- + required time 27.125 + arrival time -26.040 + ------------------------------------------------------------------- + slack 1.086 + +Slack (MET) : 1.129ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.694ns (logic 8.012ns (27.922%) route 20.682ns (72.078%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O + net (fo=32, routed) 0.922 24.333 u_cpu/u_csr/ds_to_es_bus_r_reg[166]_0 + SLICE_X111Y151 LUT2 (Prop_lut2_I1_O) 0.119 24.452 r u_cpu/u_csr/ds_to_es_bus_r[167]_i_9/O + net (fo=1, routed) 0.505 24.957 u_cpu/id_stage/ds_to_es_bus_r_reg[167] + SLICE_X110Y151 LUT6 (Prop_lut6_I5_O) 0.332 25.289 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_3/O + net (fo=1, routed) 0.631 25.920 u_cpu/id_stage/ds_to_es_bus_r[167]_i_3_n_0 + SLICE_X108Y152 LUT6 (Prop_lut6_I2_O) 0.124 26.044 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O + net (fo=1, routed) 0.000 26.044 u_cpu/exe_stage/ds_to_es_bus[117] + SLICE_X108Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X108Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X108Y152 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.044 + ------------------------------------------------------------------- + slack 1.129 + +Slack (MET) : 1.139ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.640ns (logic 7.809ns (27.266%) route 20.831ns (72.734%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.139ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.276ns = ( 27.724 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.369 23.528 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X100Y152 LUT6 (Prop_lut6_I1_O) 0.124 23.652 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O + net (fo=29, routed) 1.525 25.177 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 + SLICE_X115Y156 LUT5 (Prop_lut5_I3_O) 0.124 25.301 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O + net (fo=1, routed) 0.564 25.865 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 + SLICE_X113Y156 LUT6 (Prop_lut6_I3_O) 0.124 25.989 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O + net (fo=1, routed) 0.000 25.989 u_cpu/exe_stage/ds_to_es_bus[127] + SLICE_X113Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.553 27.724 u_cpu/exe_stage/cpu_clk + SLICE_X113Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/C + clock pessimism -0.514 27.211 + clock uncertainty -0.113 27.097 + SLICE_X113Y156 FDRE (Setup_fdre_C_D) 0.031 27.128 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] + ------------------------------------------------------------------- + required time 27.128 + arrival time -25.989 + ------------------------------------------------------------------- + slack 1.139 + +Slack (MET) : 1.143ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.683ns (logic 7.809ns (27.225%) route 20.874ns (72.775%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.799 25.021 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X113Y151 LUT6 (Prop_lut6_I5_O) 0.124 25.145 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_3/O + net (fo=1, routed) 0.763 25.908 u_cpu/id_stage/ds_to_es_bus_r[188]_i_3_n_0 + SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.032 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_1/O + net (fo=1, routed) 0.000 26.032 u_cpu/exe_stage/ds_to_es_bus[138] + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[188] + ------------------------------------------------------------------- + required time 27.175 + arrival time -26.032 + ------------------------------------------------------------------- + slack 1.143 + +Slack (MET) : 1.148ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.629ns (logic 7.809ns (27.276%) route 20.820ns (72.723%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.941 25.251 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X116Y155 LUT4 (Prop_lut4_I0_O) 0.124 25.375 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_3/O + net (fo=1, routed) 0.480 25.854 u_cpu/id_stage/ds_to_es_bus_r[184]_i_3_n_0 + SLICE_X110Y156 LUT6 (Prop_lut6_I2_O) 0.124 25.978 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O + net (fo=1, routed) 0.000 25.978 u_cpu/exe_stage/ds_to_es_bus[134] + SLICE_X110Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X110Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X110Y156 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] + ------------------------------------------------------------------- + required time 27.126 + arrival time -25.978 + ------------------------------------------------------------------- + slack 1.148 + +Slack (MET) : 1.171ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.653ns (logic 7.809ns (27.254%) route 20.844ns (72.746%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 1.015 25.238 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X115Y150 LUT6 (Prop_lut6_I3_O) 0.124 25.362 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_2/O + net (fo=1, routed) 0.516 25.878 u_cpu/id_stage/ds_to_es_bus_r[179]_i_2_n_0 + SLICE_X112Y157 LUT5 (Prop_lut5_I1_O) 0.124 26.002 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_1/O + net (fo=1, routed) 0.000 26.002 u_cpu/exe_stage/ds_to_es_bus[129] + SLICE_X112Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X112Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X112Y157 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[179] + ------------------------------------------------------------------- + required time 27.173 + arrival time -26.002 + ------------------------------------------------------------------- + slack 1.171 + +Slack (MET) : 1.184ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.639ns (logic 7.809ns (27.267%) route 20.830ns (72.733%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.606 24.829 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X112Y150 LUT4 (Prop_lut4_I0_O) 0.124 24.953 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_2/O + net (fo=1, routed) 0.911 25.864 u_cpu/id_stage/ds_to_es_bus_r[174]_i_2_n_0 + SLICE_X108Y154 LUT6 (Prop_lut6_I1_O) 0.124 25.988 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O + net (fo=1, routed) 0.000 25.988 u_cpu/exe_stage/ds_to_es_bus[124] + SLICE_X108Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X108Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X108Y154 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] + ------------------------------------------------------------------- + required time 27.172 + arrival time -25.988 + ------------------------------------------------------------------- + slack 1.184 + +Slack (MET) : 1.184ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[6][0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.591ns (logic 7.135ns (24.956%) route 21.456ns (75.044%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.796 24.197 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X119Y184 LUT6 (Prop_lut6_I0_O) 0.124 24.321 r u_cpu/id_stage/btb_counter[6][1]_i_4/O + net (fo=2, routed) 0.623 24.944 u_cpu/btb/btb_counter_reg[6][1]_0 + SLICE_X120Y184 LUT3 (Prop_lut3_I1_O) 0.149 25.093 r u_cpu/btb/btb_counter[6][0]_i_2/O + net (fo=1, routed) 0.492 25.585 u_cpu/btb/btb_counter[6][0]_i_2_n_0 + SLICE_X121Y184 LUT6 (Prop_lut6_I0_O) 0.355 25.940 r u_cpu/btb/btb_counter[6][0]_i_1/O + net (fo=1, routed) 0.000 25.940 u_cpu/btb/btb_counter[6][0]_i_1_n_0 + SLICE_X121Y184 FDRE r u_cpu/btb/btb_counter_reg[6][0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/btb/cpu_clk + SLICE_X121Y184 FDRE r u_cpu/btb/btb_counter_reg[6][0]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X121Y184 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/btb/btb_counter_reg[6][0] + ------------------------------------------------------------------- + required time 27.124 + arrival time -25.940 + ------------------------------------------------------------------- + slack 1.184 + +Slack (MET) : 1.189ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.586ns (logic 7.809ns (27.317%) route 20.777ns (72.683%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O + net (fo=32, routed) 0.901 24.031 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_4 + SLICE_X100Y150 LUT6 (Prop_lut6_I0_O) 0.124 24.155 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_8/O + net (fo=1, routed) 1.039 25.194 u_cpu/id_stage/ds_to_es_bus_r[162]_i_8_n_0 + SLICE_X104Y150 LUT6 (Prop_lut6_I1_O) 0.124 25.318 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_4/O + net (fo=1, routed) 0.493 25.812 u_cpu/id_stage/ds_to_es_bus_r[162]_i_4_n_0 + SLICE_X105Y150 LUT6 (Prop_lut6_I2_O) 0.124 25.936 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_1/O + net (fo=1, routed) 0.000 25.936 u_cpu/exe_stage/ds_to_es_bus[112] + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.029 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[162] + ------------------------------------------------------------------- + required time 27.124 + arrival time -25.936 + ------------------------------------------------------------------- + slack 1.189 + +Slack (MET) : 1.194ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.581ns (logic 7.809ns (27.322%) route 20.772ns (72.678%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.729 25.039 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X115Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.163 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_2/O + net (fo=1, routed) 0.644 25.807 u_cpu/id_stage/ds_to_es_bus_r[191]_i_2_n_0 + SLICE_X109Y160 LUT6 (Prop_lut6_I1_O) 0.124 25.931 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_1/O + net (fo=1, routed) 0.000 25.931 u_cpu/exe_stage/ds_to_es_bus[141] + SLICE_X109Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk + SLICE_X109Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X109Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[191] + ------------------------------------------------------------------- + required time 27.124 + arrival time -25.931 + ------------------------------------------------------------------- + slack 1.194 + +Slack (MET) : 1.202ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.624ns (logic 7.809ns (27.281%) route 20.815ns (72.719%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.886 25.109 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 + SLICE_X112Y152 LUT6 (Prop_lut6_I5_O) 0.124 25.233 r u_cpu/id_stage/ds_to_es_bus_r[183]_i_2/O + net (fo=1, routed) 0.617 25.849 u_cpu/id_stage/ds_to_es_bus_r[183]_i_2_n_0 + SLICE_X108Y157 LUT6 (Prop_lut6_I1_O) 0.124 25.973 r u_cpu/id_stage/ds_to_es_bus_r[183]_i_1/O + net (fo=1, routed) 0.000 25.973 u_cpu/exe_stage/ds_to_es_bus[133] + SLICE_X108Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk + SLICE_X108Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/C + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X108Y157 FDRE (Setup_fdre_C_D) 0.081 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[183] + ------------------------------------------------------------------- + required time 27.175 + arrival time -25.973 + ------------------------------------------------------------------- + slack 1.202 + +Slack (MET) : 1.264ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[31][0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.507ns (logic 7.107ns (24.931%) route 21.400ns (75.069%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.285ns = ( 27.715 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.681 24.083 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X122Y181 LUT6 (Prop_lut6_I5_O) 0.124 24.207 r u_cpu/id_stage/btb_counter[31][1]_i_7/O + net (fo=2, routed) 0.737 24.944 u_cpu/btb/btb_counter_reg[31][1]_0 + SLICE_X122Y180 LUT3 (Prop_lut3_I1_O) 0.150 25.094 r u_cpu/btb/btb_counter[31][0]_i_2/O + net (fo=1, routed) 0.436 25.530 u_cpu/btb/btb_counter[31][0]_i_2_n_0 + SLICE_X122Y180 LUT6 (Prop_lut6_I0_O) 0.326 25.856 r u_cpu/btb/btb_counter[31][0]_i_1/O + net (fo=1, routed) 0.000 25.856 u_cpu/btb/btb_counter[31][0]_i_1_n_0 + SLICE_X122Y180 FDRE r u_cpu/btb/btb_counter_reg[31][0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.544 27.715 u_cpu/btb/cpu_clk + SLICE_X122Y180 FDRE r u_cpu/btb/btb_counter_reg[31][0]/C + clock pessimism -0.514 27.202 + clock uncertainty -0.113 27.088 + SLICE_X122Y180 FDRE (Setup_fdre_C_D) 0.032 27.120 u_cpu/btb/btb_counter_reg[31][0] + ------------------------------------------------------------------- + required time 27.120 + arrival time -25.856 + ------------------------------------------------------------------- + slack 1.264 + +Slack (MET) : 1.268ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.505ns (logic 7.809ns (27.395%) route 20.696ns (72.605%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.493 23.007 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X102Y155 LUT6 (Prop_lut6_I0_O) 0.124 23.131 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O + net (fo=26, routed) 1.314 24.445 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 + SLICE_X117Y155 LUT5 (Prop_lut5_I0_O) 0.124 24.569 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_7/O + net (fo=1, routed) 0.584 25.153 u_cpu/id_stage/ds_to_es_bus_r[169]_i_7_n_0 + SLICE_X110Y155 LUT5 (Prop_lut5_I2_O) 0.124 25.277 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_3/O + net (fo=1, routed) 0.454 25.731 u_cpu/id_stage/ds_to_es_bus_r[169]_i_3_n_0 + SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.124 25.855 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_1/O + net (fo=1, routed) 0.000 25.855 u_cpu/exe_stage/ds_to_es_bus[119] + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk + SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/C + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.029 27.123 u_cpu/exe_stage/ds_to_es_bus_r_reg[169] + ------------------------------------------------------------------- + required time 27.123 + arrival time -25.855 + ------------------------------------------------------------------- + slack 1.268 + +Slack (MET) : 1.281ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.496ns (logic 7.809ns (27.404%) route 20.687ns (72.596%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.139ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.276ns = ( 27.724 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.632 23.146 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y153 LUT6 (Prop_lut6_I3_O) 0.124 23.270 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O + net (fo=32, routed) 0.937 24.207 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 + SLICE_X109Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.331 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_12/O + net (fo=1, routed) 0.363 24.694 u_cpu/id_stage/ds_to_es_bus_r[176]_i_12_n_0 + SLICE_X109Y155 LUT5 (Prop_lut5_I4_O) 0.124 24.818 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_5/O + net (fo=1, routed) 0.903 25.721 u_cpu/id_stage/ds_to_es_bus_r[176]_i_5_n_0 + SLICE_X113Y156 LUT6 (Prop_lut6_I4_O) 0.124 25.845 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O + net (fo=1, routed) 0.000 25.845 u_cpu/exe_stage/ds_to_es_bus[126] + SLICE_X113Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.553 27.724 u_cpu/exe_stage/cpu_clk + SLICE_X113Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/C + clock pessimism -0.514 27.211 + clock uncertainty -0.113 27.097 + SLICE_X113Y156 FDRE (Setup_fdre_C_D) 0.029 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] + ------------------------------------------------------------------- + required time 27.126 + arrival time -25.845 + ------------------------------------------------------------------- + slack 1.281 + +Slack (MET) : 1.307ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.470ns (logic 8.005ns (28.117%) route 20.465ns (71.883%)) + Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.662 23.176 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.300 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_16/O + net (fo=32, routed) 1.089 24.389 u_cpu/u_csr/ds_to_es_bus_r_reg[169] + SLICE_X111Y152 LUT2 (Prop_lut2_I1_O) 0.118 24.507 r u_cpu/u_csr/ds_to_es_bus_r[166]_i_11/O + net (fo=1, routed) 0.578 25.085 u_cpu/u_csr/ds_to_es_bus_r[166]_i_11_n_0 + SLICE_X111Y151 LUT6 (Prop_lut6_I5_O) 0.326 25.411 r u_cpu/u_csr/ds_to_es_bus_r[166]_i_4/O + net (fo=1, routed) 0.285 25.696 u_cpu/id_stage/ds_to_es_bus_r_reg[166] + SLICE_X109Y151 LUT6 (Prop_lut6_I3_O) 0.124 25.820 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_1/O + net (fo=1, routed) 0.000 25.820 u_cpu/exe_stage/ds_to_es_bus[116] + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk + SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/C + clock pessimism -0.514 27.210 + clock uncertainty -0.113 27.096 + SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[166] + ------------------------------------------------------------------- + required time 27.127 + arrival time -25.820 + ------------------------------------------------------------------- + slack 1.307 + +Slack (MET) : 1.392ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[5][0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.383ns (logic 7.115ns (25.068%) route 21.268ns (74.932%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.786 24.187 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X123Y184 LUT6 (Prop_lut6_I0_O) 0.124 24.311 r u_cpu/id_stage/btb_counter[5][1]_i_4/O + net (fo=2, routed) 0.649 24.960 u_cpu/btb/btb_counter_reg[5][1]_0 + SLICE_X122Y184 LUT3 (Prop_lut3_I1_O) 0.152 25.112 r u_cpu/btb/btb_counter[5][0]_i_2/O + net (fo=1, routed) 0.288 25.400 u_cpu/btb/btb_counter[5][0]_i_2_n_0 + SLICE_X122Y184 LUT6 (Prop_lut6_I0_O) 0.332 25.732 r u_cpu/btb/btb_counter[5][0]_i_1/O + net (fo=1, routed) 0.000 25.732 u_cpu/btb/btb_counter[5][0]_i_1_n_0 + SLICE_X122Y184 FDRE r u_cpu/btb/btb_counter_reg[5][0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/btb/cpu_clk + SLICE_X122Y184 FDRE r u_cpu/btb/btb_counter_reg[5][0]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X122Y184 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/btb/btb_counter_reg[5][0] + ------------------------------------------------------------------- + required time 27.124 + arrival time -25.732 + ------------------------------------------------------------------- + slack 1.392 + +Slack (MET) : 1.450ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.327ns (logic 7.809ns (27.568%) route 20.518ns (72.432%)) + Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O + net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] + SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O + net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 + SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O + net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] + SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O + net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 + SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O + net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] + SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O + net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 + SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] + net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 + SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] + net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] + SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O + net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 + SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.662 23.176 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.300 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_16/O + net (fo=32, routed) 1.223 24.523 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_3 + SLICE_X108Y153 LUT4 (Prop_lut4_I0_O) 0.124 24.647 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_12/O + net (fo=1, routed) 0.498 25.145 u_cpu/id_stage/ds_to_es_bus_r[173]_i_12_n_0 + SLICE_X109Y153 LUT6 (Prop_lut6_I1_O) 0.124 25.269 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_4/O + net (fo=1, routed) 0.283 25.552 u_cpu/id_stage/ds_to_es_bus_r[173]_i_4_n_0 + SLICE_X111Y153 LUT6 (Prop_lut6_I4_O) 0.124 25.676 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_1/O + net (fo=1, routed) 0.000 25.676 u_cpu/exe_stage/ds_to_es_bus[123] + SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk + SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X111Y153 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[173] + ------------------------------------------------------------------- + required time 27.126 + arrival time -25.676 + ------------------------------------------------------------------- + slack 1.450 + +Slack (MET) : 1.497ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[28][1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.272ns (logic 7.111ns (25.152%) route 21.161ns (74.848%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.285ns = ( 27.715 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.669 24.070 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X121Y181 LUT6 (Prop_lut6_I0_O) 0.124 24.194 r u_cpu/id_stage/btb_counter[28][1]_i_8/O + net (fo=2, routed) 0.661 24.855 u_cpu/btb/btb_counter_reg[28][1]_0 + SLICE_X122Y180 LUT3 (Prop_lut3_I1_O) 0.153 25.008 r u_cpu/btb/btb_counter[28][1]_i_2/O + net (fo=1, routed) 0.287 25.295 u_cpu/btb/btb_counter[28][1]_i_2_n_0 + SLICE_X121Y180 LUT6 (Prop_lut6_I0_O) 0.327 25.622 r u_cpu/btb/btb_counter[28][1]_i_1/O + net (fo=1, routed) 0.000 25.622 u_cpu/btb/btb_counter[28][1]_i_1_n_0 + SLICE_X121Y180 FDRE r u_cpu/btb/btb_counter_reg[28][1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.544 27.715 u_cpu/btb/cpu_clk + SLICE_X121Y180 FDRE r u_cpu/btb/btb_counter_reg[28][1]/C + clock pessimism -0.514 27.202 + clock uncertainty -0.113 27.088 + SLICE_X121Y180 FDRE (Setup_fdre_C_D) 0.031 27.119 u_cpu/btb/btb_counter_reg[28][1] + ------------------------------------------------------------------- + required time 27.119 + arrival time -25.622 + ------------------------------------------------------------------- + slack 1.497 + +Slack (MET) : 1.516ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[4][1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.306ns (logic 7.129ns (25.185%) route 21.177ns (74.815%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.144ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.744 24.146 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X120Y182 LUT6 (Prop_lut6_I0_O) 0.124 24.270 r u_cpu/id_stage/btb_counter[4][1]_i_4/O + net (fo=2, routed) 0.602 24.872 u_cpu/btb/btb_counter_reg[4][1]_0 + SLICE_X120Y183 LUT3 (Prop_lut3_I1_O) 0.150 25.022 r u_cpu/btb/btb_counter[4][1]_i_2/O + net (fo=1, routed) 0.286 25.308 u_cpu/btb/btb_counter[4][1]_i_2_n_0 + SLICE_X120Y183 LUT6 (Prop_lut6_I0_O) 0.348 25.656 r u_cpu/btb/btb_counter[4][1]_i_1/O + net (fo=1, routed) 0.000 25.656 u_cpu/btb/btb_counter[4][1]_i_1_n_0 + SLICE_X120Y183 FDRE r u_cpu/btb/btb_counter_reg[4][1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.548 27.719 u_cpu/btb/cpu_clk + SLICE_X120Y183 FDRE r u_cpu/btb/btb_counter_reg[4][1]/C + clock pessimism -0.514 27.206 + clock uncertainty -0.113 27.092 + SLICE_X120Y183 FDRE (Setup_fdre_C_D) 0.079 27.171 u_cpu/btb/btb_counter_reg[4][1] + ------------------------------------------------------------------- + required time 27.171 + arrival time -25.656 + ------------------------------------------------------------------- + slack 1.516 + +Slack (MET) : 1.521ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[6][1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.255ns (logic 7.082ns (25.065%) route 21.173ns (74.935%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.796 24.197 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X119Y184 LUT6 (Prop_lut6_I0_O) 0.124 24.321 r u_cpu/id_stage/btb_counter[6][1]_i_4/O + net (fo=2, routed) 0.567 24.888 u_cpu/btb/btb_counter_reg[6][1]_0 + SLICE_X121Y184 LUT3 (Prop_lut3_I1_O) 0.119 25.007 r u_cpu/btb/btb_counter[6][1]_i_2/O + net (fo=1, routed) 0.266 25.272 u_cpu/btb/btb_counter[6][1]_i_2_n_0 + SLICE_X121Y184 LUT6 (Prop_lut6_I0_O) 0.332 25.604 r u_cpu/btb/btb_counter[6][1]_i_1/O + net (fo=1, routed) 0.000 25.604 u_cpu/btb/btb_counter[6][1]_i_1_n_0 + SLICE_X121Y184 FDRE r u_cpu/btb/btb_counter_reg[6][1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/btb/cpu_clk + SLICE_X121Y184 FDRE r u_cpu/btb/btb_counter_reg[6][1]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X121Y184 FDRE (Setup_fdre_C_D) 0.032 27.125 u_cpu/btb/btb_counter_reg[6][1] + ------------------------------------------------------------------- + required time 27.125 + arrival time -25.604 + ------------------------------------------------------------------- + slack 1.521 + +Slack (MET) : 1.534ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[24][1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.286ns (logic 6.879ns (24.320%) route 21.407ns (75.680%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.144ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.800 24.201 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X120Y183 LUT6 (Prop_lut6_I0_O) 0.124 24.325 r u_cpu/id_stage/btb_counter[24][1]_i_4/O + net (fo=2, routed) 0.610 24.935 u_cpu/btb/btb_counter_reg[24][1]_0 + SLICE_X120Y183 LUT3 (Prop_lut3_I1_O) 0.124 25.059 r u_cpu/btb/btb_counter[24][1]_i_2/O + net (fo=1, routed) 0.452 25.511 u_cpu/btb/btb_counter[24][1]_i_2_n_0 + SLICE_X120Y183 LUT6 (Prop_lut6_I0_O) 0.124 25.635 r u_cpu/btb/btb_counter[24][1]_i_1/O + net (fo=1, routed) 0.000 25.635 u_cpu/btb/btb_counter[24][1]_i_1_n_0 + SLICE_X120Y183 FDRE r u_cpu/btb/btb_counter_reg[24][1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.548 27.719 u_cpu/btb/cpu_clk + SLICE_X120Y183 FDRE r u_cpu/btb/btb_counter_reg[24][1]/C + clock pessimism -0.514 27.206 + clock uncertainty -0.113 27.092 + SLICE_X120Y183 FDRE (Setup_fdre_C_D) 0.077 27.169 u_cpu/btb/btb_counter_reg[24][1] + ------------------------------------------------------------------- + required time 27.169 + arrival time -25.635 + ------------------------------------------------------------------- + slack 1.534 + +Slack (MET) : 1.554ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[19][1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.273ns (logic 6.879ns (24.331%) route 21.394ns (75.669%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.781 24.182 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X123Y184 LUT6 (Prop_lut6_I0_O) 0.124 24.306 r u_cpu/id_stage/btb_counter[19][1]_i_4/O + net (fo=2, routed) 0.482 24.788 u_cpu/btb/btb_counter_reg[19][1]_0 + SLICE_X123Y184 LUT3 (Prop_lut3_I1_O) 0.124 24.912 r u_cpu/btb/btb_counter[19][1]_i_2/O + net (fo=1, routed) 0.586 25.498 u_cpu/btb/btb_counter[19][1]_i_2_n_0 + SLICE_X124Y186 LUT6 (Prop_lut6_I0_O) 0.124 25.622 r u_cpu/btb/btb_counter[19][1]_i_1/O + net (fo=1, routed) 0.000 25.622 u_cpu/btb/btb_counter[19][1]_i_1_n_0 + SLICE_X124Y186 FDRE r u_cpu/btb/btb_counter_reg[19][1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/btb/cpu_clk + SLICE_X124Y186 FDRE r u_cpu/btb/btb_counter_reg[19][1]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X124Y186 FDRE (Setup_fdre_C_D) 0.081 27.176 u_cpu/btb/btb_counter_reg[19][1] + ------------------------------------------------------------------- + required time 27.176 + arrival time -25.622 + ------------------------------------------------------------------- + slack 1.554 + +Slack (MET) : 1.569ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[30][1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.200ns (logic 6.879ns (24.393%) route 21.321ns (75.607%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.147ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns = ( 27.716 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.723 24.124 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X122Y181 LUT6 (Prop_lut6_I0_O) 0.124 24.248 r u_cpu/id_stage/btb_counter[30][1]_i_6/O + net (fo=2, routed) 0.621 24.869 u_cpu/btb/btb_counter_reg[30][1]_0 + SLICE_X123Y181 LUT3 (Prop_lut3_I1_O) 0.124 24.993 r u_cpu/btb/btb_counter[30][1]_i_2/O + net (fo=1, routed) 0.433 25.426 u_cpu/btb/btb_counter[30][1]_i_2_n_0 + SLICE_X123Y181 LUT6 (Prop_lut6_I0_O) 0.124 25.550 r u_cpu/btb/btb_counter[30][1]_i_1/O + net (fo=1, routed) 0.000 25.550 u_cpu/btb/btb_counter[30][1]_i_1_n_0 + SLICE_X123Y181 FDRE r u_cpu/btb/btb_counter_reg[30][1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.545 27.716 u_cpu/btb/cpu_clk + SLICE_X123Y181 FDRE r u_cpu/btb/btb_counter_reg[30][1]/C + clock pessimism -0.514 27.203 + clock uncertainty -0.113 27.089 + SLICE_X123Y181 FDRE (Setup_fdre_C_D) 0.029 27.118 u_cpu/btb/btb_counter_reg[30][1] + ------------------------------------------------------------------- + required time 27.118 + arrival time -25.550 + ------------------------------------------------------------------- + slack 1.569 + +Slack (MET) : 1.573ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[31][1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.194ns (logic 7.082ns (25.118%) route 21.112ns (74.882%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.285ns = ( 27.715 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.681 24.083 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X122Y181 LUT6 (Prop_lut6_I5_O) 0.124 24.207 r u_cpu/id_stage/btb_counter[31][1]_i_7/O + net (fo=2, routed) 0.417 24.624 u_cpu/btb/btb_counter_reg[31][1]_0 + SLICE_X123Y181 LUT3 (Prop_lut3_I1_O) 0.119 24.743 r u_cpu/btb/btb_counter[31][1]_i_2/O + net (fo=1, routed) 0.469 25.212 u_cpu/btb/btb_counter[31][1]_i_2_n_0 + SLICE_X123Y180 LUT6 (Prop_lut6_I0_O) 0.332 25.544 r u_cpu/btb/btb_counter[31][1]_i_1/O + net (fo=1, routed) 0.000 25.544 u_cpu/btb/btb_counter[31][1]_i_1_n_0 + SLICE_X123Y180 FDRE r u_cpu/btb/btb_counter_reg[31][1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.544 27.715 u_cpu/btb/cpu_clk + SLICE_X123Y180 FDRE r u_cpu/btb/btb_counter_reg[31][1]/C + clock pessimism -0.514 27.202 + clock uncertainty -0.113 27.088 + SLICE_X123Y180 FDRE (Setup_fdre_C_D) 0.029 27.117 u_cpu/btb/btb_counter_reg[31][1] + ------------------------------------------------------------------- + required time 27.117 + arrival time -25.544 + ------------------------------------------------------------------- + slack 1.573 + +Slack (MET) : 1.574ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[1][0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.197ns (logic 6.879ns (24.396%) route 21.318ns (75.604%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.147ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns = ( 27.716 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.723 24.125 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X122Y182 LUT6 (Prop_lut6_I0_O) 0.124 24.249 r u_cpu/id_stage/btb_counter[1][1]_i_4/O + net (fo=2, routed) 0.767 25.016 u_cpu/btb/btb_counter_reg[1][1]_0 + SLICE_X122Y181 LUT3 (Prop_lut3_I1_O) 0.124 25.140 r u_cpu/btb/btb_counter[1][0]_i_2/O + net (fo=1, routed) 0.282 25.423 u_cpu/btb/btb_counter[1][0]_i_2_n_0 + SLICE_X121Y181 LUT6 (Prop_lut6_I0_O) 0.124 25.547 r u_cpu/btb/btb_counter[1][0]_i_1/O + net (fo=1, routed) 0.000 25.547 u_cpu/btb/btb_counter[1][0]_i_1_n_0 + SLICE_X121Y181 FDRE r u_cpu/btb/btb_counter_reg[1][0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.545 27.716 u_cpu/btb/cpu_clk + SLICE_X121Y181 FDRE r u_cpu/btb/btb_counter_reg[1][0]/C + clock pessimism -0.514 27.203 + clock uncertainty -0.113 27.089 + SLICE_X121Y181 FDRE (Setup_fdre_C_D) 0.031 27.120 u_cpu/btb/btb_counter_reg[1][0] + ------------------------------------------------------------------- + required time 27.120 + arrival time -25.547 + ------------------------------------------------------------------- + slack 1.574 + +Slack (MET) : 1.574ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[19][0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.249ns (logic 6.879ns (24.351%) route 21.370ns (75.649%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.781 24.182 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X123Y184 LUT6 (Prop_lut6_I0_O) 0.124 24.306 r u_cpu/id_stage/btb_counter[19][1]_i_4/O + net (fo=2, routed) 0.574 24.880 u_cpu/btb/btb_counter_reg[19][1]_0 + SLICE_X123Y186 LUT3 (Prop_lut3_I1_O) 0.124 25.004 r u_cpu/btb/btb_counter[19][0]_i_2/O + net (fo=1, routed) 0.471 25.474 u_cpu/btb/btb_counter[19][0]_i_2_n_0 + SLICE_X124Y186 LUT6 (Prop_lut6_I0_O) 0.124 25.598 r u_cpu/btb/btb_counter[19][0]_i_1/O + net (fo=1, routed) 0.000 25.598 u_cpu/btb/btb_counter[19][0]_i_1_n_0 + SLICE_X124Y186 FDRE r u_cpu/btb/btb_counter_reg[19][0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.551 27.722 u_cpu/btb/cpu_clk + SLICE_X124Y186 FDRE r u_cpu/btb/btb_counter_reg[19][0]/C + clock pessimism -0.514 27.209 + clock uncertainty -0.113 27.095 + SLICE_X124Y186 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/btb/btb_counter_reg[19][0] + ------------------------------------------------------------------- + required time 27.172 + arrival time -25.598 + ------------------------------------------------------------------- + slack 1.574 + +Slack (MET) : 1.574ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[26][0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.199ns (logic 6.879ns (24.395%) route 21.320ns (75.605%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.727 24.128 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X122Y182 LUT6 (Prop_lut6_I0_O) 0.124 24.252 r u_cpu/id_stage/btb_counter[26][1]_i_4/O + net (fo=2, routed) 0.604 24.856 u_cpu/btb/btb_counter_reg[26][1]_0 + SLICE_X122Y184 LUT3 (Prop_lut3_I1_O) 0.124 24.980 r u_cpu/btb/btb_counter[26][0]_i_2/O + net (fo=1, routed) 0.444 25.424 u_cpu/btb/btb_counter[26][0]_i_2_n_0 + SLICE_X122Y184 LUT6 (Prop_lut6_I0_O) 0.124 25.548 r u_cpu/btb/btb_counter[26][0]_i_1/O + net (fo=1, routed) 0.000 25.548 u_cpu/btb/btb_counter[26][0]_i_1_n_0 + SLICE_X122Y184 FDRE r u_cpu/btb/btb_counter_reg[26][0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/btb/cpu_clk + SLICE_X122Y184 FDRE r u_cpu/btb/btb_counter_reg[26][0]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X122Y184 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/btb/btb_counter_reg[26][0] + ------------------------------------------------------------------- + required time 27.122 + arrival time -25.548 + ------------------------------------------------------------------- + slack 1.574 + +Slack (MET) : 1.584ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[14][1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.190ns (logic 6.879ns (24.402%) route 21.311ns (75.598%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.661 24.063 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X124Y185 LUT6 (Prop_lut6_I5_O) 0.124 24.187 r u_cpu/id_stage/btb_counter[14][1]_i_4/O + net (fo=2, routed) 0.672 24.859 u_cpu/btb/btb_counter_reg[14][1]_0 + SLICE_X123Y185 LUT3 (Prop_lut3_I1_O) 0.124 24.983 r u_cpu/btb/btb_counter[14][1]_i_2/O + net (fo=1, routed) 0.433 25.416 u_cpu/btb/btb_counter[14][1]_i_2_n_0 + SLICE_X123Y185 LUT6 (Prop_lut6_I0_O) 0.124 25.540 r u_cpu/btb/btb_counter[14][1]_i_1/O + net (fo=1, routed) 0.000 25.540 u_cpu/btb/btb_counter[14][1]_i_1_n_0 + SLICE_X123Y185 FDRE r u_cpu/btb/btb_counter_reg[14][1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.550 27.721 u_cpu/btb/cpu_clk + SLICE_X123Y185 FDRE r u_cpu/btb/btb_counter_reg[14][1]/C + clock pessimism -0.514 27.208 + clock uncertainty -0.113 27.094 + SLICE_X123Y185 FDRE (Setup_fdre_C_D) 0.029 27.123 u_cpu/btb/btb_counter_reg[14][1] + ------------------------------------------------------------------- + required time 27.123 + arrival time -25.540 + ------------------------------------------------------------------- + slack 1.584 + +Slack (MET) : 1.587ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[26][1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.186ns (logic 7.107ns (25.215%) route 21.079ns (74.785%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.282ns = ( 27.718 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.727 24.128 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X122Y182 LUT6 (Prop_lut6_I0_O) 0.124 24.252 r u_cpu/id_stage/btb_counter[26][1]_i_4/O + net (fo=2, routed) 0.645 24.897 u_cpu/btb/btb_counter_reg[26][1]_0 + SLICE_X122Y182 LUT3 (Prop_lut3_I1_O) 0.150 25.047 r u_cpu/btb/btb_counter[26][1]_i_2/O + net (fo=1, routed) 0.162 25.209 u_cpu/btb/btb_counter[26][1]_i_2_n_0 + SLICE_X122Y182 LUT6 (Prop_lut6_I0_O) 0.326 25.535 r u_cpu/btb/btb_counter[26][1]_i_1/O + net (fo=1, routed) 0.000 25.535 u_cpu/btb/btb_counter[26][1]_i_1_n_0 + SLICE_X122Y182 FDRE r u_cpu/btb/btb_counter_reg[26][1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.718 u_cpu/btb/cpu_clk + SLICE_X122Y182 FDRE r u_cpu/btb/btb_counter_reg[26][1]/C + clock pessimism -0.514 27.205 + clock uncertainty -0.113 27.091 + SLICE_X122Y182 FDRE (Setup_fdre_C_D) 0.031 27.122 u_cpu/btb/btb_counter_reg[26][1] + ------------------------------------------------------------------- + required time 27.122 + arrival time -25.535 + ------------------------------------------------------------------- + slack 1.587 + +Slack (MET) : 1.599ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[5][1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.176ns (logic 7.107ns (25.223%) route 21.069ns (74.777%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.786 24.187 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X123Y184 LUT6 (Prop_lut6_I0_O) 0.124 24.311 r u_cpu/id_stage/btb_counter[5][1]_i_4/O + net (fo=2, routed) 0.584 24.895 u_cpu/btb/btb_counter_reg[5][1]_0 + SLICE_X123Y184 LUT3 (Prop_lut3_I1_O) 0.150 25.045 r u_cpu/btb/btb_counter[5][1]_i_2/O + net (fo=1, routed) 0.154 25.200 u_cpu/btb/btb_counter[5][1]_i_2_n_0 + SLICE_X123Y184 LUT6 (Prop_lut6_I0_O) 0.326 25.526 r u_cpu/btb/btb_counter[5][1]_i_1/O + net (fo=1, routed) 0.000 25.526 u_cpu/btb/btb_counter[5][1]_i_1_n_0 + SLICE_X123Y184 FDRE r u_cpu/btb/btb_counter_reg[5][1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/btb/cpu_clk + SLICE_X123Y184 FDRE r u_cpu/btb/btb_counter_reg[5][1]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X123Y184 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/btb/btb_counter_reg[5][1] + ------------------------------------------------------------------- + required time 27.124 + arrival time -25.526 + ------------------------------------------------------------------- + slack 1.599 + +Slack (MET) : 1.603ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[28][0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.167ns (logic 6.879ns (24.422%) route 21.288ns (75.578%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.285ns = ( 27.715 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.669 24.070 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X121Y181 LUT6 (Prop_lut6_I0_O) 0.124 24.194 r u_cpu/id_stage/btb_counter[28][1]_i_8/O + net (fo=2, routed) 0.632 24.827 u_cpu/btb/btb_counter_reg[28][1]_0 + SLICE_X121Y182 LUT3 (Prop_lut3_I1_O) 0.124 24.951 r u_cpu/btb/btb_counter[28][0]_i_2/O + net (fo=1, routed) 0.442 25.393 u_cpu/btb/btb_counter[28][0]_i_2_n_0 + SLICE_X121Y180 LUT6 (Prop_lut6_I0_O) 0.124 25.517 r u_cpu/btb/btb_counter[28][0]_i_1/O + net (fo=1, routed) 0.000 25.517 u_cpu/btb/btb_counter[28][0]_i_1_n_0 + SLICE_X121Y180 FDRE r u_cpu/btb/btb_counter_reg[28][0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.544 27.715 u_cpu/btb/cpu_clk + SLICE_X121Y180 FDRE r u_cpu/btb/btb_counter_reg[28][0]/C + clock pessimism -0.514 27.202 + clock uncertainty -0.113 27.088 + SLICE_X121Y180 FDRE (Setup_fdre_C_D) 0.031 27.119 u_cpu/btb/btb_counter_reg[28][0] + ------------------------------------------------------------------- + required time 27.119 + arrival time -25.517 + ------------------------------------------------------------------- + slack 1.603 + +Slack (MET) : 1.636ns (required time - arrival time) + Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/btb_counter_reg[17][1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.137ns (logic 6.879ns (24.449%) route 21.258ns (75.551%)) + Logic Levels: 32 (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT5=5 LUT6=17 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.651ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q + net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] + SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O + net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 + SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] + net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 + SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O + net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 + SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O + net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 + SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O + net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 + SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O + net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 + SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O + net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 + SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O + net (fo=6, routed) 1.411 10.887 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] + SLICE_X106Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.011 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10/O + net (fo=1, routed) 0.000 11.011 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_10_n_0 + SLICE_X106Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.561 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] + net (fo=1, routed) 0.000 11.561 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 + SLICE_X106Y124 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 11.789 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] + net (fo=5, routed) 0.954 12.744 u_cpu/dcache/tagv_ram_way[0].u/CO[0] + SLICE_X107Y129 LUT6 (Prop_lut6_I0_O) 0.313 13.057 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O + net (fo=4, routed) 0.642 13.699 u_cpu/addr_trans/tlb_entry/p_22_in + SLICE_X106Y134 LUT3 (Prop_lut3_I2_O) 0.124 13.823 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.171 13.994 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X106Y134 LUT6 (Prop_lut6_I3_O) 0.124 14.118 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.631 14.749 u_cpu/mem_stage/data_data_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 14.873 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.370 15.242 u_cpu/mem_stage/ms_allowin + SLICE_X104Y142 LUT6 (Prop_lut6_I2_O) 0.124 15.366 f u_cpu/mem_stage/es_to_ms_bus_r[175]_i_2/O + net (fo=6, routed) 0.463 15.829 u_cpu/exe_stage/p_13_in + SLICE_X104Y141 LUT5 (Prop_lut5_I0_O) 0.116 15.945 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.677 16.622 u_cpu/exe_stage/dcacop_op_en + SLICE_X106Y133 LUT6 (Prop_lut6_I5_O) 0.328 16.950 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.421 17.371 u_cpu/exe_stage/main_idle2lookup + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 17.495 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.444 17.939 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X105Y133 LUT5 (Prop_lut5_I4_O) 0.124 18.063 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.633 18.696 u_cpu/exe_stage/data_addr_ok + SLICE_X105Y141 LUT6 (Prop_lut6_I2_O) 0.124 18.820 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.446 19.266 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X106Y142 LUT6 (Prop_lut6_I2_O) 0.124 19.390 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 1.470 20.859 u_cpu/id_stage/btb_operate_en + SLICE_X120Y159 LUT2 (Prop_lut2_I1_O) 0.148 21.007 f u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13/O + net (fo=31, routed) 0.941 21.948 u_cpu/id_stage/btb_target_reg_0_31_0_1_i_13_n_0 + SLICE_X126Y166 LUT6 (Prop_lut6_I0_O) 0.328 22.276 r u_cpu/id_stage/btb_counter[29][1]_i_7/O + net (fo=1, routed) 1.001 23.278 u_cpu/id_stage/btb_counter[29][1]_i_7_n_0 + SLICE_X124Y178 LUT4 (Prop_lut4_I1_O) 0.124 23.402 r u_cpu/id_stage/btb_counter[29][1]_i_5/O + net (fo=49, routed) 0.636 24.037 u_cpu/id_stage/btb_counter[29][1]_i_5_n_0 + SLICE_X123Y183 LUT6 (Prop_lut6_I0_O) 0.124 24.161 r u_cpu/id_stage/btb_counter[17][1]_i_4/O + net (fo=2, routed) 0.644 24.805 u_cpu/btb/btb_counter_reg[17][1]_0 + SLICE_X121Y184 LUT3 (Prop_lut3_I1_O) 0.124 24.929 r u_cpu/btb/btb_counter[17][1]_i_2/O + net (fo=1, routed) 0.433 25.362 u_cpu/btb/btb_counter[17][1]_i_2_n_0 + SLICE_X121Y184 LUT6 (Prop_lut6_I0_O) 0.124 25.486 r u_cpu/btb/btb_counter[17][1]_i_1/O + net (fo=1, routed) 0.000 25.486 u_cpu/btb/btb_counter[17][1]_i_1_n_0 + SLICE_X121Y184 FDRE r u_cpu/btb/btb_counter_reg[17][1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.720 u_cpu/btb/cpu_clk + SLICE_X121Y184 FDRE r u_cpu/btb/btb_counter_reg[17][1]/C + clock pessimism -0.514 27.207 + clock uncertainty -0.113 27.093 + SLICE_X121Y184 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/btb/btb_counter_reg[17][1] + ------------------------------------------------------------------- + required time 27.122 + arrival time -25.486 + ------------------------------------------------------------------- + slack 1.636 @@ -6486,199 +6776,199 @@ Slack (MET) : 3.482ns (required time - arrival time) Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: cpu_clk -Waveform(ns): { 0.000 15.161 } -Period(ns): 30.323 +Waveform(ns): { 0.000 15.000 } +Period(ns): 30.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I -Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.323 29.074 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 -Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[1]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y5 u_cpu/btb/btb_untaken_entry_r_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y6 u_cpu/btb/btb_untaken_entry_r_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y8 u_cpu/btb/btb_untaken_entry_r_reg[11]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y4 u_cpu/btb/btb_untaken_entry_r_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X50Y5 u_cpu/btb/btb_untaken_entry_r_reg[13]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X49Y9 u_cpu/btb/btb_untaken_entry_r_reg[14]/C -Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA_D1/CLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y47 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y47 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y46 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y46 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y48 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y48 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y49 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y49 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y50 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y50 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y51 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y51 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y48 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y48 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y49 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y49 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y52 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y52 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y51 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y51 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y52 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y52 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y51 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y51 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X7Y50 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X7Y50 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X7Y51 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X7Y51 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X6Y48 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X6Y48 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X6Y49 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X6Y49 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a BUFG/I n/a 2.155 30.000 27.845 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I +Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.000 28.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X140Y147 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[10][9]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X143Y140 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][0]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X143Y140 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][10]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X142Y141 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][11]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X142Y141 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][12]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X145Y142 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][13]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X143Y143 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][14]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X142Y141 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][15]/C +Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.000 130.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X124Y169 u_cpu/btb/btb_target_reg_0_31_22_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X124Y169 u_cpu/btb/btb_target_reg_0_31_22_23/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- -From Clock: mlkem_clk_clk_pll - To Clock: mlkem_clk_clk_pll +From Clock: mlkem_clk + To Clock: mlkem_clk -Setup : 0 Failing Endpoints, Worst Slack 10.807ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 0.070ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 5.250ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.070ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -6688,61 +6978,59 @@ Slack (MET) : 10.807ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O + net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732] + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/C + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732] ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 + required time 10.626 + arrival time -10.555 ------------------------------------------------------------------- - slack 10.807 + slack 0.070 -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.088ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -6752,61 +7040,89 @@ Slack (MET) : 10.904ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] + net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] + SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O + net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O + net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O + net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 + required time 10.168 + arrival time -10.080 ------------------------------------------------------------------- - slack 10.904 + slack 0.088 -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.091ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -6816,61 +7132,83 @@ Slack (MET) : 10.918ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) + 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] + net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] + SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O + net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O + net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O + net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 + required time 10.168 + arrival time -10.077 ------------------------------------------------------------------- - slack 10.918 + slack 0.091 -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.128ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -6880,61 +7218,59 @@ Slack (MET) : 11.034ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948] + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948] ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 + required time 10.701 + arrival time -10.573 ------------------------------------------------------------------- - slack 11.034 + slack 0.128 -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.129ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -6944,61 +7280,86 @@ Slack (MET) : 11.059ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] + net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O + net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 + SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O + net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O + net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 + required time 10.168 + arrival time -10.038 ------------------------------------------------------------------- - slack 11.059 + slack 0.129 -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.135ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7008,61 +7369,59 @@ Slack (MET) : 11.066ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O + net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731] + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/C + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731] ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 + required time 10.626 + arrival time -10.491 ------------------------------------------------------------------- - slack 11.066 + slack 0.135 -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.151ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7072,61 +7431,93 @@ Slack (MET) : 11.162ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O + net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 + required time 10.252 + arrival time -10.101 ------------------------------------------------------------------- - slack 11.162 + slack 0.151 -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.155ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7136,61 +7527,89 @@ Slack (MET) : 11.217ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] + net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] + SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O + net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 + SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O + net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O + net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/C - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 + required time 10.168 + arrival time -10.013 ------------------------------------------------------------------- - slack 11.217 + slack 0.155 -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.157ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7200,61 +7619,86 @@ Slack (MET) : 11.246ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] + net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O + net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 + SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O + net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O + net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/C - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 + required time 10.168 + arrival time -10.011 ------------------------------------------------------------------- - slack 11.246 + slack 0.157 -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.159ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7264,61 +7708,59 @@ Slack (MET) : 11.322ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O + net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943] + SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943] ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 + required time 10.750 + arrival time -10.591 ------------------------------------------------------------------- - slack 11.322 + slack 0.159 -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.175ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7328,61 +7770,61 @@ Slack (MET) : 11.414ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O + net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0 + SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O + net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975] + SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.987 11.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/C + clock pessimism -0.498 10.660 + clock uncertainty -0.093 10.567 + SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975] ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 + required time 10.631 + arrival time -10.455 ------------------------------------------------------------------- - slack 11.414 + slack 0.175 -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.214ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7392,61 +7834,61 @@ Slack (MET) : 11.421ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O + net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0 + SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O + net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888] + SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.061 11.232 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/C + clock pessimism -0.498 10.734 + clock uncertainty -0.093 10.641 + SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888] ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 + required time 10.754 + arrival time -10.573 ------------------------------------------------------------------- - slack 11.421 + slack 0.181 -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.181ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7456,61 +7898,93 @@ Slack (MET) : 11.503ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O + net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/C - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 + required time 10.252 + arrival time -10.071 ------------------------------------------------------------------- - slack 11.503 + slack 0.181 -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.185ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7520,61 +7994,59 @@ Slack (MET) : 11.505ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O + net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812] + SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.544 37.716 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/C - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.056 11.227 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/C + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 + required time 10.700 + arrival time -10.515 ------------------------------------------------------------------- - slack 11.505 + slack 0.185 -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.188ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.992ns (logic 0.732ns (5.634%) route 12.260ns (94.366%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7584,61 +8056,59 @@ Slack (MET) : 11.519ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.513 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/O + net (fo=1, routed) 0.000 10.513 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[946] + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946] ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 + required time 10.701 + arrival time -10.513 ------------------------------------------------------------------- - slack 11.519 + slack 0.188 -Slack (MET) : 11.557ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.208ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.299ns (logic 0.704ns (2.488%) route 27.595ns (97.512%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.969ns (logic 0.732ns (5.644%) route 12.237ns (94.356%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.207ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.775ns = ( 11.225 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7648,61 +8118,59 @@ Slack (MET) : 11.557ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.357 25.485 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.609 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[952]_i_1/O - net (fo=1, routed) 0.000 25.609 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_474 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.237 10.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X159Y32 MUXF7 (Prop_muxf7_S_O) 0.276 10.490 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[921]_i_1/O + net (fo=1, routed) 0.000 10.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[921] + SLICE_X159Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.054 11.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X159Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921]/C + clock pessimism -0.498 10.727 + clock uncertainty -0.093 10.634 + SLICE_X159Y32 FDCE (Setup_fdce_C_D) 0.064 10.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921] ------------------------------------------------------------------- - required time 37.166 - arrival time -25.609 + required time 10.698 + arrival time -10.490 ------------------------------------------------------------------- - slack 11.557 + slack 0.208 -Slack (MET) : 11.686ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.216ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[6] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.168ns (logic 0.704ns (2.499%) route 27.464ns (97.501%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.100ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.283ns = ( 37.717 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.516ns (logic 4.831ns (38.597%) route 7.685ns (61.403%)) + Logic Levels: 16 (CARRY4=5 LUT2=2 LUT5=2 LUT6=3 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7712,61 +8180,95 @@ Slack (MET) : 11.686ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.227 25.355 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.479 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[955]_i_1/O - net (fo=1, routed) 0.000 25.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_477 - SLICE_X43Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955]/D + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.651 6.519 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y85 LUT2 (Prop_lut2_I0_O) 0.150 6.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_182/O + net (fo=1, routed) 0.617 7.286 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub1[0] + SLICE_X139Y86 CARRY4 (Prop_carry4_CYINIT_CO[3]) + 0.788 8.074 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100/CO[3] + net (fo=1, routed) 0.000 8.074 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100_n_0 + SLICE_X139Y87 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 8.408 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_87/O[1] + net (fo=1, routed) 1.013 9.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[5] + SLICE_X140Y88 LUT6 (Prop_lut6_I0_O) 0.303 9.723 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_27/O + net (fo=1, routed) 0.313 10.036 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[6] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[6] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.545 37.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955]/C - clock pessimism -0.507 37.210 - clock uncertainty -0.077 37.134 - SLICE_X43Y132 FDCE (Setup_fdce_C_D) 0.031 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[6]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.165 - arrival time -25.479 + required time 10.252 + arrival time -10.036 ------------------------------------------------------------------- - slack 11.686 + slack 0.216 -Slack (MET) : 11.688ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.221ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.252ns (logic 0.704ns (2.492%) route 27.548ns (97.508%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.013ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.196ns = ( 37.804 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 13.008ns (logic 0.748ns (5.750%) route 12.260ns (94.250%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7776,61 +8278,59 @@ Slack (MET) : 11.688ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.311 25.438 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X41Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1020]_i_1/O - net (fo=1, routed) 0.000 25.562 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1186 - SLICE_X41Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.292 10.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[936]_i_1/O + net (fo=1, routed) 0.000 10.529 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[936] + SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.632 37.804 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X41Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020]/C - clock pessimism -0.507 37.297 - clock uncertainty -0.077 37.221 - SLICE_X41Y133 FDCE (Setup_fdce_C_D) 0.029 37.250 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936] ------------------------------------------------------------------- - required time 37.250 - arrival time -25.562 + required time 10.750 + arrival time -10.529 ------------------------------------------------------------------- - slack 11.688 + slack 0.221 -Slack (MET) : 11.690ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.223ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.161ns (logic 0.704ns (2.500%) route 27.457ns (97.500%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.960ns (logic 0.752ns (5.803%) route 12.208ns (94.197%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.212ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.770ns = ( 11.230 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7840,61 +8340,59 @@ Slack (MET) : 11.690ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.220 25.347 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X47Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1016]_i_1/O - net (fo=1, routed) 0.000 25.471 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1182 - SLICE_X47Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.208 10.184 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[817]_i_1/O + net (fo=1, routed) 0.000 10.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[817] + SLICE_X160Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.544 37.716 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X47Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016]/C - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X47Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.059 11.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X160Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817]/C + clock pessimism -0.498 10.732 + clock uncertainty -0.093 10.639 + SLICE_X160Y37 FDCE (Setup_fdce_C_D) 0.064 10.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817] ------------------------------------------------------------------- - required time 37.162 - arrival time -25.471 + required time 10.703 + arrival time -10.480 ------------------------------------------------------------------- - slack 11.690 + slack 0.223 -Slack (MET) : 11.731ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.230ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.172ns (logic 0.704ns (2.499%) route 27.468ns (97.501%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.947ns (logic 0.732ns (5.654%) route 12.215ns (94.346%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.207ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.775ns = ( 11.225 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7904,61 +8402,59 @@ Slack (MET) : 11.731ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.230 25.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X42Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.482 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1005]_i_1/O - net (fo=1, routed) 0.000 25.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1171 - SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.215 10.192 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X156Y32 MUXF7 (Prop_muxf7_S_O) 0.276 10.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[874]_i_1/O + net (fo=1, routed) 0.000 10.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[874] + SLICE_X156Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X42Y134 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.054 11.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X156Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874]/C + clock pessimism -0.498 10.727 + clock uncertainty -0.093 10.634 + SLICE_X156Y32 FDCE (Setup_fdce_C_D) 0.064 10.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874] ------------------------------------------------------------------- - required time 37.213 - arrival time -25.482 + required time 10.698 + arrival time -10.468 ------------------------------------------------------------------- - slack 11.731 + slack 0.230 -Slack (MET) : 11.735ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.236ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.114ns (logic 0.704ns (2.504%) route 27.410ns (97.496%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.497ns (logic 4.945ns (39.570%) route 7.552ns (60.430%)) + Logic Levels: 17 (CARRY4=6 LUT2=2 LUT5=2 LUT6=3 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -7968,61 +8464,98 @@ Slack (MET) : 11.735ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.173 25.301 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X50Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.425 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[653]_i_1/O - net (fo=1, routed) 0.000 25.425 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_906 - SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653]/D + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.651 6.519 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y85 LUT2 (Prop_lut2_I0_O) 0.150 6.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_182/O + net (fo=1, routed) 0.617 7.286 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub1[0] + SLICE_X139Y86 CARRY4 (Prop_carry4_CYINIT_CO[3]) + 0.788 8.074 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100/CO[3] + net (fo=1, routed) 0.000 8.074 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100_n_0 + SLICE_X139Y87 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 8.188 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_87/CO[3] + net (fo=1, routed) 0.000 8.188 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_87_n_0 + SLICE_X139Y88 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 8.522 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_75/O[1] + net (fo=1, routed) 0.896 9.417 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[9] + SLICE_X141Y88 LUT6 (Prop_lut6_I0_O) 0.303 9.720 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_23/O + net (fo=1, routed) 0.296 10.016 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[10] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X50Y129 FDCE (Setup_fdce_C_D) 0.029 37.160 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[10]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.160 - arrival time -25.425 + required time 10.252 + arrival time -10.016 ------------------------------------------------------------------- - slack 11.735 + slack 0.236 -Slack (MET) : 11.764ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.240ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[4] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.140ns (logic 0.704ns (2.502%) route 27.436ns (97.498%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.447ns (logic 3.218ns (25.853%) route 9.229ns (74.147%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8032,61 +8565,86 @@ Slack (MET) : 11.764ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.198 25.326 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.450 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[880]_i_1/O - net (fo=1, routed) 0.000 25.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1117 - SLICE_X44Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880]/D + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[0]) + 0.235 6.988 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[0] + net (fo=2, routed) 0.975 7.962 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[4] + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.299 8.261 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_141__0/O + net (fo=1, routed) 0.445 8.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_6 + SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.831 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_90__0/O + net (fo=1, routed) 0.437 9.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_90__0_n_0 + SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.391 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_31__0/O + net (fo=1, routed) 0.536 9.928 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[4] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[4] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.544 37.716 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880]/C - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X44Y131 FDCE (Setup_fdce_C_D) 0.081 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[4]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.214 - arrival time -25.450 + required time 10.168 + arrival time -9.928 ------------------------------------------------------------------- - slack 11.764 + slack 0.240 -Slack (MET) : 11.777ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.241ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1002]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.166ns (logic 0.704ns (2.499%) route 27.462ns (97.501%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.012ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.985ns (logic 0.748ns (5.760%) route 12.237ns (94.240%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.207ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.775ns = ( 11.225 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8096,61 +8654,59 @@ Slack (MET) : 11.777ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.225 25.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X41Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[968]_i_1/O - net (fo=1, routed) 0.000 25.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1142 - SLICE_X41Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.237 10.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X158Y32 MUXF7 (Prop_muxf7_S_O) 0.292 10.506 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1002]_i_1/O + net (fo=1, routed) 0.000 10.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[1002] + SLICE_X158Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1002]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.633 37.805 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X41Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968]/C - clock pessimism -0.507 37.298 - clock uncertainty -0.077 37.222 - SLICE_X41Y134 FDCE (Setup_fdce_C_D) 0.031 37.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.054 11.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X158Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1002]/C + clock pessimism -0.498 10.727 + clock uncertainty -0.093 10.634 + SLICE_X158Y32 FDCE (Setup_fdce_C_D) 0.113 10.747 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1002] ------------------------------------------------------------------- - required time 37.253 - arrival time -25.476 + required time 10.747 + arrival time -10.506 ------------------------------------------------------------------- - slack 11.777 + slack 0.241 -Slack (MET) : 11.846ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.246ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[729]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.007ns (logic 0.704ns (2.514%) route 27.303ns (97.486%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.908ns (logic 0.748ns (5.795%) route 12.160ns (94.205%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8160,61 +8716,59 @@ Slack (MET) : 11.846ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.066 25.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.318 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[825]_i_1/O - net (fo=1, routed) 0.000 25.318 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_468 - SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.160 10.137 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X148Y37 MUXF7 (Prop_muxf7_S_O) 0.292 10.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[729]_i_1/O + net (fo=1, routed) 0.000 10.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[729] + SLICE_X148Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[729]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X43Y133 FDCE (Setup_fdce_C_D) 0.029 37.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X148Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[729]/C + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X148Y37 FDCE (Setup_fdce_C_D) 0.113 10.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[729] ------------------------------------------------------------------- - required time 37.164 - arrival time -25.318 + required time 10.675 + arrival time -10.429 ------------------------------------------------------------------- - slack 11.846 + slack 0.246 -Slack (MET) : 11.849ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.247ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[743]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.006ns (logic 0.704ns (2.514%) route 27.302ns (97.486%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.908ns (logic 0.748ns (5.795%) route 12.160ns (94.205%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.136ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.846ns = ( 11.154 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8224,61 +8778,59 @@ Slack (MET) : 11.849ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.065 25.193 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.317 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[921]_i_1/O - net (fo=1, routed) 0.000 25.317 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1006 - SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.160 10.137 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X148Y38 MUXF7 (Prop_muxf7_S_O) 0.292 10.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[743]_i_2/O + net (fo=1, routed) 0.000 10.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[743] + SLICE_X148Y38 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[743]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X43Y133 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.983 11.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X148Y38 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[743]/C + clock pessimism -0.498 10.656 + clock uncertainty -0.093 10.563 + SLICE_X148Y38 FDCE (Setup_fdce_C_D) 0.113 10.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[743] ------------------------------------------------------------------- - required time 37.166 - arrival time -25.317 + required time 10.676 + arrival time -10.429 ------------------------------------------------------------------- - slack 11.849 + slack 0.247 -Slack (MET) : 11.911ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.252ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[8] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.944ns (logic 0.704ns (2.519%) route 27.240ns (97.481%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.435ns (logic 3.332ns (26.795%) route 9.103ns (73.205%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8288,61 +8840,89 @@ Slack (MET) : 11.911ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.002 25.130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.254 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[794]_i_1/O - net (fo=1, routed) 0.000 25.254 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1000 - SLICE_X43Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794]/D + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[0]) + 0.235 7.111 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[0] + net (fo=2, routed) 0.804 7.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[8] + SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.299 8.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_130/O + net (fo=1, routed) 0.473 8.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_10 + SLICE_X135Y74 LUT6 (Prop_lut6_I5_O) 0.124 8.811 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_84__0/O + net (fo=1, routed) 0.298 9.109 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_84__0_n_0 + SLICE_X137Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_27__0/O + net (fo=1, routed) 0.682 9.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[8] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[8] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X43Y134 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[8]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.165 - arrival time -25.254 + required time 10.168 + arrival time -9.915 ------------------------------------------------------------------- - slack 11.911 + slack 0.252 -Slack (MET) : 11.944ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.261ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[819]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.955ns (logic 0.704ns (2.518%) route 27.251ns (97.482%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.102ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.285ns = ( 37.715 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.970ns (logic 0.770ns (5.937%) route 12.200ns (94.063%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.211ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.771ns = ( 11.229 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8352,61 +8932,59 @@ Slack (MET) : 11.944ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.013 25.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y130 LUT6 (Prop_lut6_I1_O) 0.124 25.265 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[941]_i_1/O - net (fo=1, routed) 0.000 25.265 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_335 - SLICE_X46Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.200 10.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y36 MUXF7 (Prop_muxf7_S_O) 0.314 10.490 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[819]_i_1/O + net (fo=1, routed) 0.000 10.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[819] + SLICE_X162Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[819]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.543 37.715 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X46Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941]/C - clock pessimism -0.507 37.208 - clock uncertainty -0.077 37.132 - SLICE_X46Y130 FDCE (Setup_fdce_C_D) 0.077 37.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.058 11.229 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X162Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[819]/C + clock pessimism -0.498 10.731 + clock uncertainty -0.093 10.638 + SLICE_X162Y36 FDCE (Setup_fdce_C_D) 0.113 10.751 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[819] ------------------------------------------------------------------- - required time 37.209 - arrival time -25.265 + required time 10.751 + arrival time -10.490 ------------------------------------------------------------------- - slack 11.944 + slack 0.261 -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.271ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.462ns (logic 4.562ns (36.608%) route 7.900ns (63.392%)) + Logic Levels: 15 (CARRY4=4 LUT2=2 LUT5=2 LUT6=3 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8416,69 +8994,92 @@ Slack (MET) : 11.945ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C + net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114]/CE + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.651 6.519 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y85 LUT2 (Prop_lut2_I0_O) 0.150 6.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_182/O + net (fo=1, routed) 0.617 7.286 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub1[0] + SLICE_X139Y86 CARRY4 (Prop_carry4_CYINIT_O[3]) + 0.850 8.136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100/O[3] + net (fo=1, routed) 1.041 9.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[3] + SLICE_X140Y88 LUT6 (Prop_lut6_I0_O) 0.306 9.482 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_29/O + net (fo=1, routed) 0.499 9.981 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[4] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[4] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 + required time 10.252 + arrival time -9.981 ------------------------------------------------------------------- - slack 11.945 + slack 0.271 -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.271ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[951]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.961ns (logic 0.789ns (6.087%) route 12.172ns (93.913%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.213ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.769ns = ( 11.231 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8488,69 +9089,61 @@ Slack (MET) : 11.945ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115]/CE + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.172 10.148 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X158Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.272 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[951]_i_3/O + net (fo=1, routed) 0.000 10.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[951]_i_3_n_0 + SLICE_X158Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.481 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[951]_i_2/O + net (fo=1, routed) 0.000 10.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[951] + SLICE_X158Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[951]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.060 11.231 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X158Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[951]/C + clock pessimism -0.498 10.733 + clock uncertainty -0.093 10.640 + SLICE_X158Y40 FDCE (Setup_fdce_C_D) 0.113 10.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[951] ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 + required time 10.753 + arrival time -10.481 ------------------------------------------------------------------- - slack 11.945 + slack 0.271 -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.282ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[825]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.903ns (logic 0.792ns (6.138%) route 12.111ns (93.862%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.215ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.767ns = ( 11.233 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8560,69 +9153,61 @@ Slack (MET) : 11.945ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331]/CE + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.111 10.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X163Y41 LUT4 (Prop_lut4_I2_O) 0.124 10.211 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[825]_i_2/O + net (fo=1, routed) 0.000 10.211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[825]_i_2_n_0 + SLICE_X163Y41 MUXF7 (Prop_muxf7_I0_O) 0.212 10.423 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[825]_i_1/O + net (fo=1, routed) 0.000 10.423 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[825] + SLICE_X163Y41 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[825]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.062 11.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X163Y41 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[825]/C + clock pessimism -0.498 10.735 + clock uncertainty -0.093 10.642 + SLICE_X163Y41 FDCE (Setup_fdce_C_D) 0.064 10.706 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[825] ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 + required time 10.706 + arrival time -10.423 ------------------------------------------------------------------- - slack 11.945 + slack 0.282 -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.284ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.448ns (logic 3.752ns (30.141%) route 8.696ns (69.859%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8632,69 +9217,93 @@ Slack (MET) : 11.945ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C + net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401]/CE + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O + net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 + SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O + net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 + SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O + net (fo=12, routed) 0.714 9.320 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 + SLICE_X141Y86 LUT6 (Prop_lut6_I2_O) 0.124 9.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_33__0/O + net (fo=1, routed) 0.523 9.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[0] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[0] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[0]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 + required time 10.252 + arrival time -9.968 ------------------------------------------------------------------- - slack 11.945 + slack 0.284 -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.288ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[848]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.897ns (logic 0.792ns (6.141%) route 12.105ns (93.859%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.215ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.767ns = ( 11.233 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8704,69 +9313,61 @@ Slack (MET) : 11.945ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435]/CE + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.105 10.082 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X157Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[848]_i_2/O + net (fo=1, routed) 0.000 10.206 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[848]_i_2_n_0 + SLICE_X157Y43 MUXF7 (Prop_muxf7_I0_O) 0.212 10.418 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[848]_i_1/O + net (fo=1, routed) 0.000 10.418 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[848] + SLICE_X157Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[848]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.062 11.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X157Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[848]/C + clock pessimism -0.498 10.735 + clock uncertainty -0.093 10.642 + SLICE_X157Y43 FDCE (Setup_fdce_C_D) 0.064 10.706 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[848] ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 + required time 10.706 + arrival time -10.418 ------------------------------------------------------------------- - slack 11.945 + slack 0.288 -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.299ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[7] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.388ns (logic 3.319ns (26.792%) route 9.069ns (73.208%)) + Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8776,69 +9377,86 @@ Slack (MET) : 11.945ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829]/CE + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[3]) + 0.329 7.082 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[3] + net (fo=2, routed) 0.954 8.036 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[7] + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.306 8.342 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_134/O + net (fo=1, routed) 0.451 8.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_9 + SLICE_X137Y74 LUT6 (Prop_lut6_I5_O) 0.124 8.917 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_86__1/O + net (fo=1, routed) 0.294 9.211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_86__1_n_0 + SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.335 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_28__0/O + net (fo=1, routed) 0.533 9.869 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[7] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[7] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[7]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 + required time 10.168 + arrival time -9.869 ------------------------------------------------------------------- - slack 11.945 + slack 0.299 -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.305ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.427ns (logic 3.951ns (31.793%) route 8.476ns (68.207%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8848,69 +9466,93 @@ Slack (MET) : 11.945ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C + net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860]/CE + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 0.937 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y87 LUT6 (Prop_lut6_I3_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_22/O + net (fo=1, routed) 0.313 9.947 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[11] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[11] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[11]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 + required time 10.252 + arrival time -9.947 ------------------------------------------------------------------- - slack 11.945 + slack 0.305 -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.310ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[1] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.377ns (logic 2.879ns (23.261%) route 9.498ns (76.739%)) + Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8920,69 +9562,83 @@ Slack (MET) : 11.945ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924]/CE + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[1]) + 0.424 6.645 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[1] + net (fo=2, routed) 0.964 7.608 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[1] + SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 7.911 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_152/O + net (fo=1, routed) 0.454 8.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_3 + SLICE_X136Y74 LUT6 (Prop_lut6_I5_O) 0.124 8.489 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_95__0/O + net (fo=1, routed) 0.481 8.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_95__0_n_0 + SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_34/O + net (fo=1, routed) 0.763 9.858 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[1] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[1] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[1]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 + required time 10.168 + arrival time -9.858 ------------------------------------------------------------------- - slack 11.945 + slack 0.310 -Slack (MET) : 11.947ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.325ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[944]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.960ns (logic 0.704ns (2.518%) route 27.256ns (97.482%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.855ns (logic 0.732ns (5.694%) route 12.123ns (94.306%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -8992,61 +9648,59 @@ Slack (MET) : 11.947ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.018 25.146 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X42Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1006]_i_1/O - net (fo=1, routed) 0.000 25.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1172 - SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.123 10.100 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.376 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[944]_i_1/O + net (fo=1, routed) 0.000 10.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[944] + SLICE_X160Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[944]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X42Y134 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X160Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[944]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X160Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[944] ------------------------------------------------------------------- - required time 37.217 - arrival time -25.270 + required time 10.701 + arrival time -10.376 ------------------------------------------------------------------- - slack 11.947 + slack 0.325 -Slack (MET) : 11.958ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[2] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.891ns (logic 0.704ns (2.524%) route 27.187ns (97.476%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.404ns (logic 4.515ns (36.399%) route 7.889ns (63.601%)) + Logic Levels: 15 (CARRY4=4 LUT2=2 LUT5=2 LUT6=3 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9056,61 +9710,92 @@ Slack (MET) : 11.958ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.950 25.078 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X51Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[698]_i_1/O - net (fo=1, routed) 0.000 25.202 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_462 - SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698]/D + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.651 6.519 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y85 LUT2 (Prop_lut2_I0_O) 0.150 6.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_182/O + net (fo=1, routed) 0.617 7.286 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub1[0] + SLICE_X139Y86 CARRY4 (Prop_carry4_CYINIT_O[1]) + 0.806 8.092 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100/O[1] + net (fo=1, routed) 1.043 9.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[1] + SLICE_X141Y87 LUT6 (Prop_lut6_I0_O) 0.303 9.438 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_31/O + net (fo=1, routed) 0.486 9.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[2] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[2] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X51Y129 FDCE (Setup_fdce_C_D) 0.029 37.160 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[2]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.160 - arrival time -25.202 + required time 10.252 + arrival time -9.924 ------------------------------------------------------------------- - slack 11.958 + slack 0.328 -Slack (MET) : 11.960ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.330ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.891ns (logic 0.704ns (2.524%) route 27.187ns (97.476%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.402ns (logic 3.951ns (31.858%) route 8.451ns (68.142%)) + Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) + Clock Path Skew: 0.066ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) + Source Clock Delay (SCD): -2.481ns + Clock Pessimism Removal (CPR): -0.426ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9120,61 +9805,93 @@ Slack (MET) : 11.960ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.950 25.078 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X50Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[996]_i_1/O - net (fo=1, routed) 0.000 25.202 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_785 - SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996]/D + SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q + net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] + SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O + net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 + SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O + net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 + SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O + net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 + SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O + net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 + SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O + net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 + SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O + net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 + SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O + net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 + SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] + net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 + SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] + net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] + SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] + net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] + SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O + net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 + SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O + net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 + SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O + net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 + SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O + net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 + SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O + net (fo=12, routed) 0.914 9.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 + SLICE_X140Y87 LUT6 (Prop_lut6_I3_O) 0.124 9.611 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_25/O + net (fo=1, routed) 0.310 9.921 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[8] + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[8] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X50Y129 FDCE (Setup_fdce_C_D) 0.031 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk + RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK + clock pessimism -0.426 10.586 + clock uncertainty -0.093 10.493 + RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[8]) + -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- - required time 37.162 - arrival time -25.202 + required time 10.252 + arrival time -9.921 ------------------------------------------------------------------- - slack 11.960 + slack 0.330 -Slack (MET) : 11.962ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.331ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[947]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.889ns (logic 0.704ns (2.524%) route 27.185ns (97.476%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.849ns (logic 0.732ns (5.697%) route 12.117ns (94.303%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9184,61 +9901,59 @@ Slack (MET) : 11.962ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.948 25.076 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X51Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[997]_i_1/O - net (fo=1, routed) 0.000 25.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_786 - SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.117 10.094 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X161Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.370 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[947]_i_1/O + net (fo=1, routed) 0.000 10.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[947] + SLICE_X161Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[947]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X51Y129 FDCE (Setup_fdce_C_D) 0.031 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X161Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[947]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X161Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[947] ------------------------------------------------------------------- - required time 37.162 - arrival time -25.200 + required time 10.701 + arrival time -10.370 ------------------------------------------------------------------- - slack 11.962 + slack 0.331 -Slack (MET) : 11.975ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.331ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[828]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.867ns (logic 0.704ns (2.526%) route 27.163ns (97.474%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.110ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.293ns = ( 37.707 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.903ns (logic 0.789ns (6.115%) route 12.114ns (93.885%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: 0.215ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.767ns = ( 11.233 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9248,61 +9963,61 @@ Slack (MET) : 11.975ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.926 25.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X55Y125 LUT6 (Prop_lut6_I1_O) 0.124 25.178 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[713]_i_1/O - net (fo=1, routed) 0.000 25.178 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1029 - SLICE_X55Y125 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 12.114 10.090 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X162Y41 LUT4 (Prop_lut4_I2_O) 0.124 10.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[828]_i_2/O + net (fo=1, routed) 0.000 10.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[828]_i_2_n_0 + SLICE_X162Y41 MUXF7 (Prop_muxf7_I0_O) 0.209 10.423 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[828]_i_1/O + net (fo=1, routed) 0.000 10.423 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[828] + SLICE_X162Y41 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[828]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.535 37.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X55Y125 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713]/C - clock pessimism -0.507 37.200 - clock uncertainty -0.077 37.124 - SLICE_X55Y125 FDCE (Setup_fdce_C_D) 0.029 37.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.062 11.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X162Y41 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[828]/C + clock pessimism -0.498 10.735 + clock uncertainty -0.093 10.642 + SLICE_X162Y41 FDCE (Setup_fdce_C_D) 0.113 10.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[828] ------------------------------------------------------------------- - required time 37.153 - arrival time -25.178 + required time 10.755 + arrival time -10.423 ------------------------------------------------------------------- - slack 11.975 + slack 0.331 -Slack (MET) : 12.001ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.333ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] + (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.895ns (logic 0.704ns (2.524%) route 27.191ns (97.476%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.104ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.287ns = ( 37.713 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.354ns (logic 3.036ns (24.575%) route 9.318ns (75.425%)) + Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) + Clock Path Skew: 0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) + Source Clock Delay (SCD): -2.520ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9312,61 +10027,89 @@ Slack (MET) : 12.001ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.954 25.082 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X52Y128 LUT6 (Prop_lut6_I1_O) 0.124 25.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[714]_i_1/O - net (fo=1, routed) 0.000 25.206 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1030 - SLICE_X52Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714]/D + SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q + net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 + SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O + net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 + SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O + net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 + SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O + net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 + SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O + net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 + SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O + net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 + SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O + net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 + SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O + net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 + SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O + net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 + SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 + SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 + SLICE_X106Y75 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.990 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CO[3] + net (fo=2, routed) 1.126 8.115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[11] + SLICE_X130Y75 LUT6 (Prop_lut6_I1_O) 0.124 8.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_121__0/O + net (fo=1, routed) 0.612 8.852 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_13 + SLICE_X136Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.976 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_77__0/O + net (fo=1, routed) 0.293 9.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_77__0_n_0 + SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.393 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_24__0/O + net (fo=1, routed) 0.442 9.835 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[11] + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[11] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.541 37.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X52Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714]/C - clock pessimism -0.507 37.206 - clock uncertainty -0.077 37.130 - SLICE_X52Y128 FDCE (Setup_fdce_C_D) 0.077 37.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk + RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK + clock pessimism -0.498 10.502 + clock uncertainty -0.093 10.409 + RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[11]) + -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- - required time 37.207 - arrival time -25.206 + required time 10.168 + arrival time -9.835 ------------------------------------------------------------------- - slack 12.001 + slack 0.333 -Slack (MET) : 12.017ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.333ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[805]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.835ns (logic 0.704ns (2.529%) route 27.131ns (97.471%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.737ns (logic 0.580ns (4.554%) route 12.157ns (95.446%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9376,61 +10119,59 @@ Slack (MET) : 12.017ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.894 25.021 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X53Y130 LUT6 (Prop_lut6_I1_O) 0.124 25.145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[701]_i_1/O - net (fo=1, routed) 0.000 25.145 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_465 - SLICE_X53Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.157 10.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X153Y36 LUT5 (Prop_lut5_I2_O) 0.124 10.258 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[805]_i_1/O + net (fo=1, routed) 0.000 10.258 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[805] + SLICE_X153Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[805]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X53Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X53Y130 FDCE (Setup_fdce_C_D) 0.031 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X153Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[805]/C + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X153Y36 FDCE (Setup_fdce_C_D) 0.029 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[805] ------------------------------------------------------------------- - required time 37.162 - arrival time -25.145 + required time 10.591 + arrival time -10.258 ------------------------------------------------------------------- - slack 12.017 + slack 0.333 -Slack (MET) : 12.030ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.333ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[806]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.826ns (logic 0.704ns (2.530%) route 27.122ns (97.470%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.739ns (logic 0.580ns (4.553%) route 12.159ns (95.447%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.135ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9440,61 +10181,59 @@ Slack (MET) : 12.030ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.884 25.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1002]_i_1/O - net (fo=1, routed) 0.000 25.136 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1168 - SLICE_X43Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.159 10.136 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X153Y36 LUT5 (Prop_lut5_I2_O) 0.124 10.260 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[806]_i_1/O + net (fo=1, routed) 0.000 10.260 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[806] + SLICE_X153Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[806]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002]/C - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X43Y135 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X153Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[806]/C + clock pessimism -0.498 10.655 + clock uncertainty -0.093 10.562 + SLICE_X153Y36 FDCE (Setup_fdce_C_D) 0.031 10.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[806] ------------------------------------------------------------------- - required time 37.166 - arrival time -25.136 + required time 10.593 + arrival time -10.260 ------------------------------------------------------------------- - slack 12.030 + slack 0.333 -Slack (MET) : 12.046ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.339ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1014]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.810ns (logic 0.704ns (2.531%) route 27.106ns (97.469%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.809ns (logic 0.580ns (4.528%) route 12.229ns (95.472%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9504,61 +10243,59 @@ Slack (MET) : 12.046ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.869 24.997 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.121 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[781]_i_1/O - net (fo=1, routed) 0.000 25.121 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_913 - SLICE_X45Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.229 10.205 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X156Y36 LUT5 (Prop_lut5_I2_O) 0.124 10.329 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1014]_i_1/O + net (fo=1, routed) 0.000 10.329 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[1014] + SLICE_X156Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1014]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y136 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X156Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1014]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X156Y36 FDCE (Setup_fdce_C_D) 0.032 10.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1014] ------------------------------------------------------------------- - required time 37.167 - arrival time -25.121 + required time 10.669 + arrival time -10.329 ------------------------------------------------------------------- - slack 12.046 + slack 0.339 -Slack (MET) : 12.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.340ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1013]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.826ns (logic 0.704ns (2.530%) route 27.122ns (97.470%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.108ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.291ns = ( 37.709 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.808ns (logic 0.580ns (4.529%) route 12.228ns (95.471%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9568,61 +10305,59 @@ Slack (MET) : 12.066ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.885 25.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X56Y126 LUT6 (Prop_lut6_I1_O) 0.124 25.137 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[712]_i_1/O - net (fo=1, routed) 0.000 25.137 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1028 - SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.228 10.204 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X156Y36 LUT5 (Prop_lut5_I2_O) 0.124 10.328 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1013]_i_1/O + net (fo=1, routed) 0.000 10.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[1013] + SLICE_X156Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1013]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.537 37.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712]/C - clock pessimism -0.507 37.202 - clock uncertainty -0.077 37.126 - SLICE_X56Y126 FDCE (Setup_fdce_C_D) 0.077 37.203 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X156Y36 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1013]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X156Y36 FDCE (Setup_fdce_C_D) 0.031 10.668 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1013] ------------------------------------------------------------------- - required time 37.203 - arrival time -25.137 + required time 10.668 + arrival time -10.328 ------------------------------------------------------------------- - slack 12.066 + slack 0.340 -Slack (MET) : 12.080ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.349ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[945]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.816ns (logic 0.704ns (2.531%) route 27.112ns (97.469%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.108ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.291ns = ( 37.709 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.831ns (logic 0.752ns (5.861%) route 12.079ns (94.139%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.210ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9632,61 +10367,59 @@ Slack (MET) : 12.080ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.875 25.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X56Y126 LUT6 (Prop_lut6_I1_O) 0.124 25.127 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[716]_i_1/O - net (fo=1, routed) 0.000 25.127 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1032 - SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.079 10.056 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X160Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.352 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[945]_i_1/O + net (fo=1, routed) 0.000 10.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[945] + SLICE_X160Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[945]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.537 37.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716]/C - clock pessimism -0.507 37.202 - clock uncertainty -0.077 37.126 - SLICE_X56Y126 FDCE (Setup_fdce_C_D) 0.081 37.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X160Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[945]/C + clock pessimism -0.498 10.730 + clock uncertainty -0.093 10.637 + SLICE_X160Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[945] ------------------------------------------------------------------- - required time 37.207 - arrival time -25.127 + required time 10.701 + arrival time -10.352 ------------------------------------------------------------------- - slack 12.080 + slack 0.349 -Slack (MET) : 12.098ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.362ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[809]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.803ns (logic 0.704ns (2.532%) route 27.099ns (97.468%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.817ns (logic 0.732ns (5.711%) route 12.085ns (94.289%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9696,61 +10429,59 @@ Slack (MET) : 12.098ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.862 24.990 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X42Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.114 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[920]_i_1/O - net (fo=1, routed) 0.000 25.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1005 - SLICE_X42Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920]/D + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.085 10.062 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X159Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.338 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[809]_i_1/O + net (fo=1, routed) 0.000 10.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[809] + SLICE_X159Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[809]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X42Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X42Y133 FDCE (Setup_fdce_C_D) 0.077 37.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.056 11.227 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X159Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[809]/C + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X159Y34 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[809] ------------------------------------------------------------------- - required time 37.212 - arrival time -25.114 + required time 10.700 + arrival time -10.338 ------------------------------------------------------------------- - slack 12.098 + slack 0.362 -Slack (MET) : 12.111ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.371ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[924]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.340ns (logic 1.594ns (5.830%) route 25.746ns (94.170%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.180ns = ( 37.820 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.860ns (logic 0.748ns (5.817%) route 12.112ns (94.183%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.211ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.771ns = ( 11.229 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9760,69 +10491,59 @@ Slack (MET) : 12.111ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 7.963 24.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490]/CE + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.112 10.088 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X162Y35 MUXF7 (Prop_muxf7_S_O) 0.292 10.380 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[924]_i_1/O + net (fo=1, routed) 0.000 10.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[924] + SLICE_X162Y35 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[924]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.648 37.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490]/C - clock pessimism -0.507 37.313 - clock uncertainty -0.077 37.237 - SLICE_X22Y111 FDCE (Setup_fdce_C_CE) -0.371 36.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.058 11.229 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X162Y35 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[924]/C + clock pessimism -0.498 10.731 + clock uncertainty -0.093 10.638 + SLICE_X162Y35 FDCE (Setup_fdce_C_D) 0.113 10.751 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[924] ------------------------------------------------------------------- - required time 36.866 - arrival time -24.755 + required time 10.751 + arrival time -10.380 ------------------------------------------------------------------- - slack 12.111 + slack 0.371 -Slack (MET) : 12.111ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.375ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[985]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.340ns (logic 1.594ns (5.830%) route 25.746ns (94.170%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.180ns = ( 37.820 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.804ns (logic 0.732ns (5.717%) route 12.072ns (94.283%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9832,69 +10553,59 @@ Slack (MET) : 12.111ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 7.963 24.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491]/CE + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.072 10.049 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X156Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.325 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[985]_i_1/O + net (fo=1, routed) 0.000 10.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[985] + SLICE_X156Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[985]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.648 37.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491]/C - clock pessimism -0.507 37.313 - clock uncertainty -0.077 37.237 - SLICE_X22Y111 FDCE (Setup_fdce_C_CE) -0.371 36.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.056 11.227 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X156Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[985]/C + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X156Y34 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[985] ------------------------------------------------------------------- - required time 36.866 - arrival time -24.755 + required time 10.700 + arrival time -10.325 ------------------------------------------------------------------- - slack 12.111 + slack 0.375 -Slack (MET) : 12.111ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.379ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[988]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.340ns (logic 1.594ns (5.830%) route 25.746ns (94.170%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.180ns = ( 37.820 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 12.801ns (logic 0.752ns (5.875%) route 12.049ns (94.125%)) + Logic Levels: 1 (MUXF7=1) + Clock Path Skew: 0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) + Source Clock Delay (SCD): -2.480ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -9904,46 +10615,36 @@ Slack (MET) : 12.111ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C + net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 7.963 24.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778]/CE + SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q + net (fo=1088, routed) 12.049 10.025 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 + SLICE_X157Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.321 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[988]_i_1/O + net (fo=1, routed) 0.000 10.321 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[988] + SLICE_X157Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[988]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.648 37.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778]/C - clock pessimism -0.507 37.313 - clock uncertainty -0.077 37.237 - SLICE_X22Y111 FDCE (Setup_fdce_C_CE) -0.371 36.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 2.056 11.227 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X157Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[988]/C + clock pessimism -0.498 10.729 + clock uncertainty -0.093 10.636 + SLICE_X157Y34 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[988] ------------------------------------------------------------------- - required time 36.866 - arrival time -24.755 + required time 10.700 + arrival time -10.321 ------------------------------------------------------------------- - slack 12.111 + slack 0.379 @@ -9951,163 +10652,163 @@ Slack (MET) : 12.111ns (required time - arrival time) Pulse Width Checks -------------------------------------------------------------------------------------- -Clock Name: mlkem_clk_clk_pll -Waveform(ns): { 0.000 20.000 } -Period(ns): 40.000 +Clock Name: mlkem_clk +Waveform(ns): { 0.000 6.500 } +Period(ns): 13.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I -Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 40.000 38.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X103Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[897]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X101Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[898]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y118 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[899]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[89]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[900]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[901]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[902]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[903]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X56Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[904]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[905]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[906]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[907]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[908]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[909]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[90]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[910]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[911]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[912]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[913]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X92Y115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[914]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X148Y176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][3]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][4]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][5]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X125Y187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][6]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X132Y173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][7]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][8]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X150Y179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][9]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X130Y211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][0]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][10]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][11]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X121Y226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][1]/C -Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 40.000 120.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y39 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y38 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y40 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y41 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB36_X7Y14 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y37 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X8Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X6Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y44 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y43 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y42 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y45 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y39 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y38 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y40 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y41 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB36_X7Y14 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y37 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X8Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X6Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y44 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y43 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y42 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y45 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg/CLKBWRCLK +Min Period n/a BUFG/I n/a 2.155 13.000 10.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I +Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 13.000 11.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X160Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[0]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[1]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[2]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[3]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[4]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X160Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[5]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[6]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[7]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X102Y84 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[94]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X105Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[95]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X102Y84 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[96]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X107Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[97]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X109Y78 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[98]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X111Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[99]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X127Y86 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[9]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X155Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/snt_ack_reg/C +Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 13.000 147.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK @@ -10115,7 +10816,7 @@ High Pulse Width Fast RAMD32/CLK n/a 1.250 20.00 From Clock: sys_clk To Clock: sys_clk -Setup : 0 Failing Endpoints, Worst Slack 0.167ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 0.125ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- @@ -10123,24 +10824,24 @@ PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Vio Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.125ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -10154,30 +10855,30 @@ Slack (MET) : 0.167ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I + AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 r ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.197 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- @@ -10189,106 +10890,32 @@ Slack (MET) : 0.167ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 + required time 13.322 + arrival time -13.197 ------------------------------------------------------------------- - slack 0.167 + slack 0.125 -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.253ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -10302,47 +10929,44 @@ Slack (MET) : 0.377ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] + 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.069 ext_ram_data[21] AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- @@ -10354,32 +10978,32 @@ Slack (MET) : 0.377ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 + required time 13.322 + arrival time -13.069 ------------------------------------------------------------------- - slack 0.377 + slack 0.253 -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.342ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] + Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -10393,48 +11017,45 @@ Slack (MET) : 0.414ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.980 ext_ram_data[22] + Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -10445,106 +11066,32 @@ Slack (MET) : 0.414ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 + required time 13.322 + arrival time -12.980 ------------------------------------------------------------------- - slack 0.414 + slack 0.342 -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.395ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -10558,30 +11105,30 @@ Slack (MET) : 0.431ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O + net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] + SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O + net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 + SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O + net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] + SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O + net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] + SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O + net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I + AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 r ext_ram_data_IOBUF[20]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.927 ext_ram_data[20] AD18 r ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- @@ -10593,32 +11140,32 @@ Slack (MET) : 0.431ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 + required time 13.322 + arrival time -12.927 ------------------------------------------------------------------- - slack 0.431 + slack 0.395 -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.403ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] + Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -10632,48 +11179,45 @@ Slack (MET) : 0.455ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.919 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -10684,32 +11228,32 @@ Slack (MET) : 0.455ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 + required time 13.322 + arrival time -12.919 ------------------------------------------------------------------- - slack 0.455 + slack 0.403 -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.416ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] + Destination: ext_ram_data[6] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -10723,31 +11267,29 @@ Slack (MET) : 0.477ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.820 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O + net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38] + SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 r u_matmul_axi_slave/ram_reg_i_46/O + net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] + SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O + net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 + SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O + net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I + AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 r ext_ram_data_IOBUF[6]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.906 ext_ram_data[6] + AE20 r ext_ram_data[6] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -10758,487 +11300,32 @@ Slack (MET) : 0.477ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 + required time 13.322 + arrival time -12.906 ------------------------------------------------------------------- - slack 0.477 + slack 0.416 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.558ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[24] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.118ns (logic 6.871ns (45.448%) route 8.247ns (54.552%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.444 9.239 ext_ram_data_IOBUF[24]_inst/T - AD17 OBUFT (TriStatE_obuft_T_O) - 3.558 12.797 r ext_ram_data_IOBUF[24]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.797 ext_ram_data[24] - AD17 r ext_ram_data[24] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.797 - ------------------------------------------------------------------- - slack 0.558 - -Slack (MET) : 0.584ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[17] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.092ns (logic 6.859ns (45.448%) route 8.233ns (54.552%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.694 9.224 base_ram_data_IOBUF[17]_inst/T - M21 OBUFT (TriStatE_obuft_T_O) - 3.546 12.770 r base_ram_data_IOBUF[17]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.770 base_ram_data[17] - M21 r base_ram_data[17] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.770 - ------------------------------------------------------------------- - slack 0.584 - -Slack (MET) : 0.597ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[23] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.079ns (logic 6.848ns (45.415%) route 8.231ns (54.585%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.693 9.222 base_ram_data_IOBUF[23]_inst/T - N21 OBUFT (TriStatE_obuft_T_O) - 3.535 12.757 r base_ram_data_IOBUF[23]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.757 base_ram_data[23] - N21 r base_ram_data[23] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.757 - ------------------------------------------------------------------- - slack 0.597 - -Slack (MET) : 0.647ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[19] + Destination: ext_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.124ns (logic 5.128ns (33.905%) route 9.996ns (66.095%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -11252,31 +11339,31 @@ Slack (MET) : 0.647ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.513 2.665 u_matmul_axi_slave/b0_c_reg_r2_0_15_48_53/ADDRB0 - SLICE_X36Y74 RAMD32 (Prop_ramd32_RADR0_O) - 0.124 2.789 r u_matmul_axi_slave/b0_c_reg_r2_0_15_48_53/RAMB_D1/O - net (fo=1, routed) 0.605 3.393 u_snix_axil_cdma_mux_8ch/ep_rd_c0[51] - SLICE_X34Y74 LUT6 (Prop_lut6_I1_O) 0.124 3.517 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_14__0/O - net (fo=2, routed) 0.775 4.293 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[19]_inst_i_1_0 - SLICE_X30Y77 LUT5 (Prop_lut5_I3_O) 0.124 4.417 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_7__0/O - net (fo=2, routed) 1.453 5.869 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[19] - SLICE_X6Y79 LUT3 (Prop_lut3_I0_O) 0.124 5.993 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[19]_inst_i_1/O - net (fo=2, routed) 3.172 9.165 ext_ram_data_IOBUF[19]_inst/I - AC18 OBUFT (Prop_obuft_I_O) 3.542 12.707 r ext_ram_data_IOBUF[19]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.707 ext_ram_data[19] - AC18 r ext_ram_data[19] (INOUT) + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I + AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.900 ext_ram_data[31] + AC23 r ext_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -11287,32 +11374,32 @@ Slack (MET) : 0.647ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.707 + required time 13.322 + arrival time -12.900 ------------------------------------------------------------------- - slack 0.647 + slack 0.422 -Slack (MET) : 0.675ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.475ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_be_n[2] + Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.000ns (logic 6.848ns (45.654%) route 8.152ns (54.346%)) - Logic Levels: 14 (CARRY4=7 LUT4=1 LUT5=1 LUT6=4 OBUF=1) + Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -11326,47 +11413,45 @@ Slack (MET) : 0.675ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 2.270 7.078 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] - SLICE_X11Y127 LUT6 (Prop_lut6_I5_O) 0.124 7.202 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[2]_inst_i_1/O - net (fo=1, routed) 1.941 9.143 base_ram_be_n_OBUF[2] - L23 OBUF (Prop_obuf_I_O) 3.535 12.679 r base_ram_be_n_OBUF[2]_inst/O - net (fo=0) 0.000 12.679 base_ram_be_n[2] - L23 r base_ram_be_n[2] (OUT) + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.847 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -11377,544 +11462,32 @@ Slack (MET) : 0.675ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.679 + required time 13.322 + arrival time -12.847 ------------------------------------------------------------------- - slack 0.675 + slack 0.475 -Slack (MET) : 0.680ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.996ns (logic 6.840ns (45.614%) route 8.156ns (54.386%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.617 9.147 base_ram_data_IOBUF[16]_inst/T - P21 OBUFT (TriStatE_obuft_T_O) - 3.527 12.674 r base_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.674 base_ram_data[16] - P21 r base_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.674 - ------------------------------------------------------------------- - slack 0.680 - -Slack (MET) : 0.681ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.483ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.090ns (logic 5.359ns (35.512%) route 9.732ns (64.488%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.167 9.136 base_ram_data_IOBUF[22]_inst/I - N24 OBUFT (Prop_obuft_I_O) 3.537 12.673 r base_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.673 base_ram_data[22] - N24 r base_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.673 - ------------------------------------------------------------------- - slack 0.681 - -Slack (MET) : 0.682ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[0] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.993ns (logic 6.873ns (45.840%) route 8.120ns (54.160%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.582 9.112 base_ram_data_IOBUF[0]_inst/T - L24 OBUFT (TriStatE_obuft_T_O) - 3.560 12.672 r base_ram_data_IOBUF[0]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.672 base_ram_data[0] - L24 r base_ram_data[0] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.672 - ------------------------------------------------------------------- - slack 0.682 - -Slack (MET) : 0.692ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[23] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.984ns (logic 6.855ns (45.753%) route 8.128ns (54.247%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.325 9.120 ext_ram_data_IOBUF[23]_inst/T - AA15 OBUFT (TriStatE_obuft_T_O) - 3.542 12.662 r ext_ram_data_IOBUF[23]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.662 ext_ram_data[23] - AA15 r ext_ram_data[23] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.662 - ------------------------------------------------------------------- - slack 0.692 - -Slack (MET) : 0.697ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[29] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.075ns (logic 5.121ns (33.974%) route 9.953ns (66.026%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.174 2.506 u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/ADDRA1 - SLICE_X36Y75 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.630 r u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/RAMA_D1/O - net (fo=1, routed) 0.969 3.598 u_snix_axil_cdma_mux_8ch/ep_rd_c0[61] - SLICE_X35Y72 LUT6 (Prop_lut6_I1_O) 0.124 3.722 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_26__0/O - net (fo=1, routed) 0.767 4.489 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][29]_i_2 - SLICE_X34Y70 LUT4 (Prop_lut4_I2_O) 0.124 4.613 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_11__0/O - net (fo=7, routed) 1.469 6.082 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_3 - SLICE_X6Y65 LUT3 (Prop_lut3_I0_O) 0.124 6.206 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[29]_inst_i_1/O - net (fo=2, routed) 2.916 9.122 base_ram_data_IOBUF[29]_inst/I - N23 OBUFT (Prop_obuft_I_O) 3.535 12.657 r base_ram_data_IOBUF[29]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.657 base_ram_data[29] - N23 r base_ram_data[29] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.657 - ------------------------------------------------------------------- - slack 0.697 - -Slack (MET) : 0.700ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[3] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.976ns (logic 6.883ns (45.959%) route 8.093ns (54.041%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.555 9.084 base_ram_data_IOBUF[3]_inst/T - M25 OBUFT (TriStatE_obuft_T_O) - 3.570 12.654 r base_ram_data_IOBUF[3]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.654 base_ram_data[3] - M25 r base_ram_data[3] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.654 - ------------------------------------------------------------------- - slack 0.700 - -Slack (MET) : 0.717ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.959ns (logic 6.859ns (45.853%) route 8.100ns (54.147%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -11928,47 +11501,30 @@ Slack (MET) : 0.717ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.562 9.091 base_ram_data_IOBUF[31]_inst/T - M22 OBUFT (TriStatE_obuft_T_O) - 3.546 12.638 r base_ram_data_IOBUF[31]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.638 base_ram_data[31] + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O + net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] + SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O + net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O + net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] + SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O + net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] + SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O + net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I + M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.839 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- @@ -11980,328 +11536,32 @@ Slack (MET) : 0.717ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.638 + required time 13.322 + arrival time -12.839 ------------------------------------------------------------------- - slack 0.717 + slack 0.483 -Slack (MET) : 0.724ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.048ns (logic 5.340ns (35.487%) route 9.708ns (64.513%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 2.954 9.128 base_ram_data_IOBUF[20]_inst/I - N19 OBUFT (Prop_obuft_I_O) 3.502 12.630 r base_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.630 base_ram_data[20] - N19 r base_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.630 - ------------------------------------------------------------------- - slack 0.724 - -Slack (MET) : 0.737ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.035ns (logic 5.349ns (35.580%) route 9.685ns (64.420%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 3.564 9.084 base_ram_data_IOBUF[18]_inst/I - P23 OBUFT (Prop_obuft_I_O) 3.533 12.617 r base_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.617 base_ram_data[18] - P23 r base_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.617 - ------------------------------------------------------------------- - slack 0.737 - -Slack (MET) : 0.793ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.978ns (logic 5.374ns (35.881%) route 9.604ns (64.119%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 2.870 9.008 ext_ram_data_IOBUF[28]_inst/I - AD21 OBUFT (Prop_obuft_I_O) 3.552 12.561 r ext_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.561 ext_ram_data[28] - AD21 r ext_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.561 - ------------------------------------------------------------------- - slack 0.793 - -Slack (MET) : 0.827ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[26] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.945ns (logic 5.374ns (35.959%) route 9.571ns (64.041%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 0.957 2.289 u_matmul_axi_slave/b1_c_reg_r2_0_15_54_59/ADDRC1 - SLICE_X36Y70 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.442 r u_matmul_axi_slave/b1_c_reg_r2_0_15_54_59/RAMC/O - net (fo=1, routed) 0.739 3.181 u_snix_axil_cdma_mux_8ch/ep_rd_c1[58] - SLICE_X39Y71 LUT6 (Prop_lut6_I0_O) 0.331 3.512 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_23__0/O - net (fo=1, routed) 0.706 4.218 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][26]_i_2_0 - SLICE_X35Y73 LUT4 (Prop_lut4_I2_O) 0.124 4.342 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_10__0/O - net (fo=6, routed) 1.406 5.748 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[26] - SLICE_X2Y73 LUT3 (Prop_lut3_I0_O) 0.124 5.872 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[26]_inst_i_1/O - net (fo=2, routed) 3.104 8.975 ext_ram_data_IOBUF[26]_inst/I - AD20 OBUFT (Prop_obuft_I_O) 3.552 12.527 r ext_ram_data_IOBUF[26]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.527 ext_ram_data[26] - AD20 r ext_ram_data[26] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.527 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.830ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.489ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[19] + Destination: ext_ram_data[19] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.845ns (logic 6.831ns (46.012%) route 8.015ns (53.988%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -12315,48 +11575,45 @@ Slack (MET) : 0.830ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.476 9.006 base_ram_data_IOBUF[19]_inst/T - P19 OBUFT (TriStatE_obuft_T_O) - 3.518 12.524 r base_ram_data_IOBUF[19]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.524 base_ram_data[19] - P19 r base_ram_data[19] (INOUT) + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.833 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -12367,129 +11624,32 @@ Slack (MET) : 0.830ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.524 + required time 13.322 + arrival time -12.833 ------------------------------------------------------------------- - slack 0.830 + slack 0.489 -Slack (MET) : 0.836ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[2]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.109ns (logic 5.382ns (28.164%) route 13.727ns (71.836%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT3=1 LUT4=4 LUT5=2 LUT6=5) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 1.005 16.243 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X71Y60 LUT3 (Prop_lut3_I1_O) 0.331 16.574 r u_matmul_axi_slave/crc_reg[2]_i_1/O - net (fo=1, routed) 0.000 16.574 u_matmul_axi_slave/crc32_word_next1_return[2] - SLICE_X71Y60 FDSE r u_matmul_axi_slave/crc_reg_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X71Y60 FDSE r u_matmul_axi_slave/crc_reg_reg[2]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X71Y60 FDSE (Setup_fdse_C_D) 0.031 17.410 u_matmul_axi_slave/crc_reg_reg[2] - ------------------------------------------------------------------- - required time 17.410 - arrival time -16.574 - ------------------------------------------------------------------- - slack 0.836 - -Slack (MET) : 0.845ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.508ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_be_n[0] + Destination: ext_ram_data[23] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.830ns (logic 6.844ns (46.150%) route 7.986ns (53.850%)) - Logic Levels: 14 (CARRY4=7 LUT4=1 LUT5=1 LUT6=4 OBUF=1) + Data Path Delay: 15.143ns (logic 6.882ns (45.449%) route 8.261ns (54.551%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -12503,47 +11663,45 @@ Slack (MET) : 0.845ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 1.799 6.608 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] - SLICE_X0Y112 LUT6 (Prop_lut6_I5_O) 0.124 6.732 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O - net (fo=1, routed) 2.246 8.977 base_ram_be_n_OBUF[0] - L20 OBUF (Prop_obuf_I_O) 3.531 12.509 r base_ram_be_n_OBUF[0]_inst/O - net (fo=0) 0.000 12.509 base_ram_be_n[0] - L20 r base_ram_be_n[0] (OUT) + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.595 9.272 ext_ram_data_IOBUF[23]_inst/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 12.815 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.815 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -12554,425 +11712,32 @@ Slack (MET) : 0.845ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.509 + required time 13.322 + arrival time -12.815 ------------------------------------------------------------------- - slack 0.845 + slack 0.508 -Slack (MET) : 0.860ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[17] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.912ns (logic 5.126ns (34.375%) route 9.786ns (65.625%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.285 2.617 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 - SLICE_X40Y73 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.741 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA_D1/O - net (fo=1, routed) 0.600 3.341 u_snix_axil_cdma_mux_8ch/ep_rd_c1[49] - SLICE_X35Y74 LUT6 (Prop_lut6_I0_O) 0.124 3.465 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_12_17_i_6__0/O - net (fo=2, routed) 0.596 4.061 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[17]_inst_i_1_0 - SLICE_X34Y73 LUT5 (Prop_lut5_I3_O) 0.124 4.185 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_12_17_i_3__0/O - net (fo=2, routed) 1.313 5.498 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[17] - SLICE_X8Y69 LUT3 (Prop_lut3_I0_O) 0.124 5.622 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[17]_inst_i_1/O - net (fo=2, routed) 3.333 8.954 ext_ram_data_IOBUF[17]_inst/I - AC19 OBUFT (Prop_obuft_I_O) 3.540 12.494 r ext_ram_data_IOBUF[17]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.494 ext_ram_data[17] - AC19 r ext_ram_data[17] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.494 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.862ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[29] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.910ns (logic 5.133ns (34.429%) route 9.777ns (65.571%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.174 2.506 u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/ADDRA1 - SLICE_X36Y75 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.630 r u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/RAMA_D1/O - net (fo=1, routed) 0.969 3.598 u_snix_axil_cdma_mux_8ch/ep_rd_c0[61] - SLICE_X35Y72 LUT6 (Prop_lut6_I1_O) 0.124 3.722 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_26__0/O - net (fo=1, routed) 0.767 4.489 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][29]_i_2 - SLICE_X34Y70 LUT4 (Prop_lut4_I2_O) 0.124 4.613 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_11__0/O - net (fo=7, routed) 1.469 6.082 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_3 - SLICE_X6Y65 LUT3 (Prop_lut3_I0_O) 0.124 6.206 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[29]_inst_i_1/O - net (fo=2, routed) 2.740 8.945 ext_ram_data_IOBUF[29]_inst/I - AC21 OBUFT (Prop_obuft_I_O) 3.547 12.492 r ext_ram_data_IOBUF[29]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.492 ext_ram_data[29] - AC21 r ext_ram_data[29] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.492 - ------------------------------------------------------------------- - slack 0.862 - -Slack (MET) : 0.870ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[19]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.071ns (logic 5.382ns (28.221%) route 13.689ns (71.779%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=2 LUT6=6) - Clock Path Skew: -0.018ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.967 16.204 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X71Y64 LUT6 (Prop_lut6_I3_O) 0.331 16.535 r u_matmul_axi_slave/crc_reg[19]_i_1/O - net (fo=1, routed) 0.000 16.535 u_matmul_axi_slave/crc32_word_next1_return[19] - SLICE_X71Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.701 17.873 u_matmul_axi_slave/sys_clk - SLICE_X71Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[19]/C - clock pessimism -0.426 17.446 - clock uncertainty -0.071 17.376 - SLICE_X71Y64 FDSE (Setup_fdse_C_D) 0.029 17.405 u_matmul_axi_slave/crc_reg_reg[19] - ------------------------------------------------------------------- - required time 17.405 - arrival time -16.535 - ------------------------------------------------------------------- - slack 0.870 - -Slack (MET) : 0.875ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[27] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.896ns (logic 5.131ns (34.446%) route 9.765ns (65.554%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.268 2.600 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/ADDRB1 - SLICE_X36Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.724 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB_D1/O - net (fo=1, routed) 0.724 3.448 u_snix_axil_cdma_mux_8ch/ep_rd_c0[27] - SLICE_X34Y71 LUT6 (Prop_lut6_I1_O) 0.124 3.572 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_21__0/O - net (fo=1, routed) 0.977 4.549 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][27]_i_2_1 - SLICE_X23Y72 LUT4 (Prop_lut4_I3_O) 0.124 4.673 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_9__0/O - net (fo=6, routed) 1.188 5.861 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[27] - SLICE_X0Y75 LUT3 (Prop_lut3_I0_O) 0.124 5.985 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[27]_inst_i_1/O - net (fo=2, routed) 2.949 8.934 ext_ram_data_IOBUF[27]_inst/I - AB21 OBUFT (Prop_obuft_I_O) 3.545 12.479 r ext_ram_data_IOBUF[27]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.479 ext_ram_data[27] - AB21 r ext_ram_data[27] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.479 - ------------------------------------------------------------------- - slack 0.875 - -Slack (MET) : 0.883ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[0] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.888ns (logic 5.398ns (36.257%) route 9.490ns (63.743%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.146 2.991 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/O - net (fo=1, routed) 0.751 3.742 u_snix_axil_cdma_mux_8ch/ep_rd_c0[0] - SLICE_X34Y76 LUT6 (Prop_lut6_I1_O) 0.328 4.070 r u_snix_axil_cdma_mux_8ch/ram_reg_i_80/O - net (fo=1, routed) 0.416 4.485 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.609 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_48/O - net (fo=9, routed) 1.361 5.971 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.095 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O - net (fo=2, routed) 2.790 8.885 ext_ram_data_IOBUF[0]_inst/I - AF24 OBUFT (Prop_obuft_I_O) 3.586 12.471 r ext_ram_data_IOBUF[0]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.471 ext_ram_data[0] - AF24 r ext_ram_data[0] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.471 - ------------------------------------------------------------------- - slack 0.883 - -Slack (MET) : 0.890ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.518ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_addr[16] + Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.786ns (logic 6.749ns (45.642%) route 8.037ns (54.358%)) - Logic Levels: 13 (CARRY4=7 LUT4=1 LUT5=1 LUT6=3 OBUF=1) + Data Path Delay: 15.133ns (logic 6.891ns (45.538%) route 8.241ns (54.462%)) + Logic Levels: 13 (CARRY4=6 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -12986,45 +11751,44 @@ Slack (MET) : 0.890ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.925 4.220 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X0Y70 LUT6 (Prop_lut6_I5_O) 0.313 4.533 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[16]_inst_i_2/O - net (fo=2, routed) 0.648 5.181 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[16]_inst_i_2_n_0 - SLICE_X0Y71 LUT6 (Prop_lut6_I1_O) 0.124 5.305 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[16]_inst_i_1/O - net (fo=2, routed) 3.599 8.905 ext_ram_addr_OBUF[16] - AE17 OBUF (Prop_obuf_I_O) 3.560 12.464 r ext_ram_addr_OBUF[16]_inst/O - net (fo=0) 0.000 12.464 ext_ram_addr[16] - AE17 r ext_ram_addr[16] (OUT) + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 2.371 7.266 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y129 LUT6 (Prop_lut6_I5_O) 0.124 7.390 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 1.863 9.253 base_ram_be_n_OBUF[3] + K25 OBUF (Prop_obuf_I_O) 3.551 12.804 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 12.804 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -13035,300 +11799,32 @@ Slack (MET) : 0.890ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.464 + required time 13.322 + arrival time -12.804 ------------------------------------------------------------------- - slack 0.890 + slack 0.518 -Slack (MET) : 0.905ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[18]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.087ns (logic 5.382ns (28.198%) route 13.705ns (71.802%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=2 LUT6=6) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.983 16.220 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X68Y64 LUT6 (Prop_lut6_I2_O) 0.331 16.551 r u_matmul_axi_slave/crc_reg[18]_i_1/O - net (fo=1, routed) 0.000 16.551 u_matmul_axi_slave/crc32_word_next1_return[18] - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[18]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X68Y64 FDSE (Setup_fdse_C_D) 0.077 17.456 u_matmul_axi_slave/crc_reg_reg[18] - ------------------------------------------------------------------- - required time 17.456 - arrival time -16.551 - ------------------------------------------------------------------- - slack 0.905 - -Slack (MET) : 0.911ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[25]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.085ns (logic 5.382ns (28.201%) route 13.703ns (71.799%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=2 LUT6=6) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.981 16.218 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X68Y64 LUT6 (Prop_lut6_I2_O) 0.331 16.549 r u_matmul_axi_slave/crc_reg[25]_i_1/O - net (fo=1, routed) 0.000 16.549 u_matmul_axi_slave/crc32_word_next1_return0[23] - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[25]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X68Y64 FDSE (Setup_fdse_C_D) 0.081 17.460 u_matmul_axi_slave/crc_reg_reg[25] - ------------------------------------------------------------------- - required time 17.460 - arrival time -16.549 - ------------------------------------------------------------------- - slack 0.911 - -Slack (MET) : 0.948ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.823ns (logic 5.154ns (34.770%) route 9.669ns (65.230%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 2.927 8.838 ext_ram_data_IOBUF[1]_inst/I - AE23 OBUFT (Prop_obuft_I_O) 3.568 12.406 r ext_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.406 ext_ram_data[1] - AE23 r ext_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.406 - ------------------------------------------------------------------- - slack 0.948 - -Slack (MET) : 0.949ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.535ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[26] + Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.726ns (logic 6.846ns (46.488%) route 7.880ns (53.512%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.116ns (logic 6.893ns (45.603%) route 8.223ns (54.397%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -13342,48 +11838,45 @@ Slack (MET) : 0.949ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.342 8.872 base_ram_data_IOBUF[26]_inst/T - R21 OBUFT (TriStatE_obuft_T_O) - 3.533 12.405 r base_ram_data_IOBUF[26]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.405 base_ram_data[26] - R21 r base_ram_data[26] (INOUT) + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.557 9.234 ext_ram_data_IOBUF[25]_inst/T + AC17 OBUFT (TriStatE_obuft_T_O) + 3.553 12.788 r ext_ram_data_IOBUF[25]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.788 ext_ram_data[25] + AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -13394,583 +11887,32 @@ Slack (MET) : 0.949ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.405 + required time 13.322 + arrival time -12.788 ------------------------------------------------------------------- - slack 0.949 + slack 0.535 -Slack (MET) : 0.959ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C +Slack (MET) : 0.557ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[13]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.035ns (logic 5.382ns (28.275%) route 13.653ns (71.725%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=5 LUT5=2 LUT6=5) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.931 16.168 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X68Y64 LUT4 (Prop_lut4_I1_O) 0.331 16.499 r u_matmul_axi_slave/crc_reg[13]_i_1/O - net (fo=1, routed) 0.000 16.499 u_matmul_axi_slave/crc32_word_next1_return[13] - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[13]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X68Y64 FDSE (Setup_fdse_C_D) 0.079 17.458 u_matmul_axi_slave/crc_reg_reg[13] - ------------------------------------------------------------------- - required time 17.458 - arrival time -16.499 - ------------------------------------------------------------------- - slack 0.959 - -Slack (MET) : 0.962ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[29]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.029ns (logic 5.382ns (28.283%) route 13.647ns (71.717%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=3 LUT6=5) - Clock Path Skew: -0.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.126ns = ( 17.874 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.925 16.162 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X70Y62 LUT5 (Prop_lut5_I4_O) 0.331 16.493 r u_matmul_axi_slave/crc_reg[29]_i_1/O - net (fo=1, routed) 0.000 16.493 u_matmul_axi_slave/crc32_word_next1_return0[27] - SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.702 17.874 u_matmul_axi_slave/sys_clk - SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[29]/C - clock pessimism -0.426 17.447 - clock uncertainty -0.071 17.377 - SLICE_X70Y62 FDSE (Setup_fdse_C_D) 0.079 17.456 u_matmul_axi_slave/crc_reg_reg[29] - ------------------------------------------------------------------- - required time 17.456 - arrival time -16.493 - ------------------------------------------------------------------- - slack 0.962 - -Slack (MET) : 0.969ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[30]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.061ns (logic 5.414ns (28.404%) route 13.647ns (71.596%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=5 LUT5=2 LUT6=5) - Clock Path Skew: -0.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.126ns = ( 17.874 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.925 16.162 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X70Y62 LUT4 (Prop_lut4_I3_O) 0.363 16.525 r u_matmul_axi_slave/crc_reg[30]_i_1/O - net (fo=1, routed) 0.000 16.525 u_matmul_axi_slave/crc32_word_next1_return0[28] - SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.702 17.874 u_matmul_axi_slave/sys_clk - SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[30]/C - clock pessimism -0.426 17.447 - clock uncertainty -0.071 17.377 - SLICE_X70Y62 FDSE (Setup_fdse_C_D) 0.118 17.495 u_matmul_axi_slave/crc_reg_reg[30] - ------------------------------------------------------------------- - required time 17.495 - arrival time -16.525 - ------------------------------------------------------------------- - slack 0.969 - -Slack (MET) : 0.971ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[27]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 18.975ns (logic 5.382ns (28.364%) route 13.593ns (71.636%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=3 LUT6=5) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.871 16.108 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X69Y63 LUT5 (Prop_lut5_I3_O) 0.331 16.439 r u_matmul_axi_slave/crc_reg[27]_i_1/O - net (fo=1, routed) 0.000 16.439 u_matmul_axi_slave/crc32_word_next1_return0[25] - SLICE_X69Y63 FDSE r u_matmul_axi_slave/crc_reg_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X69Y63 FDSE r u_matmul_axi_slave/crc_reg_reg[27]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X69Y63 FDSE (Setup_fdse_C_D) 0.031 17.410 u_matmul_axi_slave/crc_reg_reg[27] - ------------------------------------------------------------------- - required time 17.410 - arrival time -16.439 - ------------------------------------------------------------------- - slack 0.971 - -Slack (MET) : 1.008ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[5] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.764ns (logic 5.026ns (34.045%) route 9.738ns (65.955%)) - Logic Levels: 8 (LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.515 2.847 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.971 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/O - net (fo=1, routed) 0.999 3.970 u_snix_axil_cdma_mux_8ch/ep_rd_c0[5] - SLICE_X38Y78 LUT6 (Prop_lut6_I1_O) 0.124 4.094 r u_snix_axil_cdma_mux_8ch/ram_reg_i_37/O - net (fo=3, routed) 0.879 4.973 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_29 - SLICE_X43Y73 LUT6 (Prop_lut6_I3_O) 0.124 5.097 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[5]_inst_i_1/O - net (fo=2, routed) 3.685 8.782 ext_ram_data_IOBUF[5]_inst/I - AE21 OBUFT (Prop_obuft_I_O) 3.564 12.347 r ext_ram_data_IOBUF[5]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.347 ext_ram_data[5] - AE21 r ext_ram_data[5] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.347 - ------------------------------------------------------------------- - slack 1.008 - -Slack (MET) : 1.012ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[27] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.664ns (logic 6.836ns (46.615%) route 7.828ns (53.385%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.290 8.820 base_ram_data_IOBUF[27]_inst/T - P20 OBUFT (TriStatE_obuft_T_O) - 3.523 12.342 r base_ram_data_IOBUF[27]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.342 base_ram_data[27] - P20 r base_ram_data[27] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.342 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.016ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.660ns (logic 6.906ns (47.111%) route 7.753ns (52.889%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.173ns (logic 5.026ns (33.126%) route 10.147ns (66.874%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -13984,47 +11926,29 @@ Slack (MET) : 1.016ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 2.950 8.745 ext_ram_data_IOBUF[3]_inst/T - AE22 OBUFT (TriStatE_obuft_T_O) - 3.593 12.338 r ext_ram_data_IOBUF[3]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.338 ext_ram_data[3] + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 0.971 1.949 u_snix_axil_cdma_mux_8ch/ep_rd_elem[1] + SLICE_X21Y79 LUT6 (Prop_lut6_I3_O) 0.124 2.073 r u_snix_axil_cdma_mux_8ch/ram_reg_i_77/O + net (fo=32, routed) 1.329 3.402 u_matmul_axi_slave/ram_reg_i_51_1 + SLICE_X24Y84 LUT4 (Prop_lut4_I3_O) 0.124 3.526 r u_matmul_axi_slave/ram_reg_i_67/O + net (fo=1, routed) 0.500 4.026 u_matmul_axi_slave/ram_reg_i_67_n_0 + SLICE_X25Y84 LUT5 (Prop_lut5_I4_O) 0.124 4.150 r u_matmul_axi_slave/ram_reg_i_49/O + net (fo=1, routed) 0.645 4.795 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[3] + SLICE_X29Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.919 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_33/O + net (fo=3, routed) 0.413 5.332 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[3] + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.456 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[3]_inst_i_1/O + net (fo=2, routed) 3.731 9.187 ext_ram_data_IOBUF[3]_inst/I + AE22 OBUFT (Prop_obuft_I_O) 3.578 12.765 r ext_ram_data_IOBUF[3]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.765 ext_ram_data[3] AE22 r ext_ram_data[3] (INOUT) ------------------------------------------------------------------- ------------------- @@ -14036,213 +11960,32 @@ Slack (MET) : 1.016ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.338 + required time 13.322 + arrival time -12.765 ------------------------------------------------------------------- - slack 1.016 + slack 0.557 -Slack (MET) : 1.017ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_be_n[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.659ns (logic 6.844ns (46.685%) route 7.815ns (53.314%)) - Logic Levels: 14 (CARRY4=7 LUT4=1 LUT5=1 LUT6=4 OBUF=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 1.983 6.791 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] - SLICE_X0Y121 LUT6 (Prop_lut6_I5_O) 0.124 6.915 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O - net (fo=1, routed) 1.892 8.807 base_ram_be_n_OBUF[1] - L22 OBUF (Prop_obuf_I_O) 3.531 12.337 r base_ram_be_n_OBUF[1]_inst/O - net (fo=0) 0.000 12.337 base_ram_be_n[1] - L22 r base_ram_be_n[1] (OUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.337 - ------------------------------------------------------------------- - slack 1.017 - -Slack (MET) : 1.017ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[4] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.659ns (logic 6.905ns (47.105%) route 7.754ns (52.895%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 2.951 8.745 ext_ram_data_IOBUF[4]_inst/T - AF22 OBUFT (TriStatE_obuft_T_O) - 3.592 12.337 r ext_ram_data_IOBUF[4]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.337 ext_ram_data[4] - AF22 r ext_ram_data[4] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.337 - ------------------------------------------------------------------- - slack 1.017 - -Slack (MET) : 1.018ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.561ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[5] + Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.754ns (logic 5.001ns (33.893%) route 9.753ns (66.107%)) - Logic Levels: 8 (LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) + Data Path Delay: 15.169ns (logic 5.223ns (34.430%) route 9.946ns (65.570%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT6=4 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -14256,29 +11999,31 @@ Slack (MET) : 1.018ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.515 2.847 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.971 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/O - net (fo=1, routed) 0.999 3.970 u_snix_axil_cdma_mux_8ch/ep_rd_c0[5] - SLICE_X38Y78 LUT6 (Prop_lut6_I1_O) 0.124 4.094 r u_snix_axil_cdma_mux_8ch/ram_reg_i_37/O - net (fo=3, routed) 0.879 4.973 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_29 - SLICE_X43Y73 LUT6 (Prop_lut6_I3_O) 0.124 5.097 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[5]_inst_i_1/O - net (fo=2, routed) 3.700 8.798 base_ram_data_IOBUF[5]_inst/I - P24 OBUFT (Prop_obuft_I_O) 3.539 12.336 r base_ram_data_IOBUF[5]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.336 base_ram_data[5] - P24 r base_ram_data[5] (INOUT) + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.303 2.393 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA0 + SLICE_X22Y84 RAMD32 (Prop_ramd32_RADR0_O) + 0.150 2.543 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/O + net (fo=1, routed) 0.961 3.504 u_matmul_axi_slave/ep_rd_c0[0] + SLICE_X24Y82 LUT4 (Prop_lut4_I2_O) 0.328 3.832 r u_matmul_axi_slave/ram_reg_i_73/O + net (fo=1, routed) 0.667 4.499 u_matmul_axi_slave/ram_reg_i_73_n_0 + SLICE_X24Y82 LUT6 (Prop_lut6_I0_O) 0.124 4.623 r u_matmul_axi_slave/ram_reg_i_52/O + net (fo=1, routed) 0.414 5.036 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[0] + SLICE_X26Y82 LUT6 (Prop_lut6_I5_O) 0.124 5.160 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_36/O + net (fo=3, routed) 0.309 5.470 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] + SLICE_X27Y83 LUT3 (Prop_lut3_I0_O) 0.124 5.594 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O + net (fo=2, routed) 3.623 9.217 base_ram_data_IOBUF[0]_inst/I + L24 OBUFT (Prop_obuft_I_O) 3.545 12.761 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.761 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -14289,32 +12034,518 @@ Slack (MET) : 1.018ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.336 + required time 13.322 + arrival time -12.761 ------------------------------------------------------------------- - slack 1.018 + slack 0.561 -Slack (MET) : 1.019ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.585ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.145ns (logic 5.222ns (34.482%) route 9.923ns (65.518%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.356 2.446 u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y85 RAMD32 (Prop_ramd32_RADR0_O) + 0.150 2.596 r u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/RAMA/O + net (fo=1, routed) 0.805 3.401 u_matmul_axi_slave/ep_rd_c0[30] + SLICE_X24Y83 LUT4 (Prop_lut4_I2_O) 0.328 3.729 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0/O + net (fo=1, routed) 0.428 4.157 u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0_n_0 + SLICE_X26Y82 LUT5 (Prop_lut5_I4_O) 0.124 4.281 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O + net (fo=1, routed) 0.462 4.742 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[30] + SLICE_X28Y82 LUT6 (Prop_lut6_I5_O) 0.124 4.866 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_8__1/O + net (fo=3, routed) 0.482 5.348 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[30] + SLICE_X28Y82 LUT3 (Prop_lut3_I0_O) 0.124 5.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O + net (fo=2, routed) 3.721 9.193 base_ram_data_IOBUF[30]_inst/I + M24 OBUFT (Prop_obuft_I_O) 3.544 12.737 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.737 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.737 + ------------------------------------------------------------------- + slack 0.585 + +Slack (MET) : 0.587ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.143ns (logic 5.221ns (34.475%) route 9.923ns (65.525%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.328 2.418 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/ADDRA0 + SLICE_X22Y82 RAMD32 (Prop_ramd32_RADR0_O) + 0.150 2.568 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA/O + net (fo=1, routed) 0.801 3.369 u_matmul_axi_slave/ep_rd_c0[24] + SLICE_X19Y77 LUT4 (Prop_lut4_I2_O) 0.328 3.697 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_20__0/O + net (fo=1, routed) 0.151 3.848 u_matmul_axi_slave/ram_reg_0_7_24_29_i_20__0_n_0 + SLICE_X19Y77 LUT5 (Prop_lut5_I4_O) 0.124 3.972 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_14__0/O + net (fo=1, routed) 0.433 4.405 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[24] + SLICE_X19Y77 LUT6 (Prop_lut6_I5_O) 0.124 4.529 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_8__1/O + net (fo=3, routed) 0.840 5.368 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[24] + SLICE_X11Y71 LUT3 (Prop_lut3_I0_O) 0.124 5.492 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[24]_inst_i_1/O + net (fo=2, routed) 3.701 9.193 ext_ram_data_IOBUF[24]_inst/I + AD17 OBUFT (Prop_obuft_I_O) 3.543 12.736 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.736 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.736 + ------------------------------------------------------------------- + slack 0.587 + +Slack (MET) : 0.616ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.035ns (logic 6.884ns (45.785%) route 8.151ns (54.215%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.367 9.162 base_ram_data_IOBUF[21]_inst/T + M20 OBUFT (TriStatE_obuft_T_O) + 3.544 12.706 r base_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.706 base_ram_data[21] + M20 r base_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.706 + ------------------------------------------------------------------- + slack 0.616 + +Slack (MET) : 0.622ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.029ns (logic 6.910ns (45.974%) route 8.120ns (54.026%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.335 9.131 base_ram_data_IOBUF[3]_inst/T + M25 OBUFT (TriStatE_obuft_T_O) + 3.570 12.701 r base_ram_data_IOBUF[3]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.701 base_ram_data[3] + M25 r base_ram_data[3] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.701 + ------------------------------------------------------------------- + slack 0.622 + +Slack (MET) : 0.628ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[18] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.102ns (logic 5.207ns (34.482%) route 9.895ns (65.518%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O + net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] + SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O + net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 + SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O + net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] + SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O + net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O + net (fo=2, routed) 3.505 9.161 base_ram_data_IOBUF[18]_inst/I + P23 OBUFT (Prop_obuft_I_O) 3.533 12.694 r base_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.694 base_ram_data[18] + P23 r base_ram_data[18] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.694 + ------------------------------------------------------------------- + slack 0.628 + +Slack (MET) : 0.632ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[17] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.019ns (logic 6.895ns (45.909%) route 8.124ns (54.091%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.458 9.135 ext_ram_data_IOBUF[17]_inst/T + AC19 OBUFT (TriStatE_obuft_T_O) + 3.555 12.691 r ext_ram_data_IOBUF[17]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.691 ext_ram_data[17] + AC19 r ext_ram_data[17] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.691 + ------------------------------------------------------------------- + slack 0.632 + +Slack (MET) : 0.636ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.656ns (logic 6.857ns (46.787%) route 7.799ns (53.213%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.094ns (logic 5.207ns (34.496%) route 9.887ns (65.504%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -14328,47 +12559,30 @@ Slack (MET) : 1.019ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 2.996 8.790 ext_ram_data_IOBUF[30]_inst/T - AA19 OBUFT (TriStatE_obuft_T_O) - 3.544 12.335 r ext_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.335 ext_ram_data[30] + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.356 2.446 u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/ADDRA0 + SLICE_X22Y85 RAMD32 (Prop_ramd32_RADR0_O) + 0.150 2.596 r u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/RAMA/O + net (fo=1, routed) 0.805 3.401 u_matmul_axi_slave/ep_rd_c0[30] + SLICE_X24Y83 LUT4 (Prop_lut4_I2_O) 0.328 3.729 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0/O + net (fo=1, routed) 0.428 4.157 u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0_n_0 + SLICE_X26Y82 LUT5 (Prop_lut5_I4_O) 0.124 4.281 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O + net (fo=1, routed) 0.462 4.742 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[30] + SLICE_X28Y82 LUT6 (Prop_lut6_I5_O) 0.124 4.866 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_8__1/O + net (fo=3, routed) 0.482 5.348 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[30] + SLICE_X28Y82 LUT3 (Prop_lut3_I0_O) 0.124 5.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O + net (fo=2, routed) 3.685 9.158 ext_ram_data_IOBUF[30]_inst/I + AA19 OBUFT (Prop_obuft_I_O) 3.529 12.687 r ext_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.687 ext_ram_data[30] AA19 r ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- @@ -14380,13 +12594,2322 @@ Slack (MET) : 1.019ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 ------------------------------------------------------------------- - required time 13.354 - arrival time -12.335 + required time 13.322 + arrival time -12.687 ------------------------------------------------------------------- - slack 1.019 + slack 0.636 + +Slack (MET) : 0.692ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[17] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.958ns (logic 6.886ns (46.033%) route 8.073ns (53.967%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.288 9.084 base_ram_data_IOBUF[17]_inst/T + M21 OBUFT (TriStatE_obuft_T_O) + 3.546 12.630 r base_ram_data_IOBUF[17]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.630 base_ram_data[17] + M21 r base_ram_data[17] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.630 + ------------------------------------------------------------------- + slack 0.692 + +Slack (MET) : 0.732ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[20] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.997ns (logic 5.202ns (34.686%) route 9.795ns (65.314%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 + SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) + 0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O + net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] + SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O + net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 + SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O + net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] + SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O + net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] + SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O + net (fo=2, routed) 3.539 9.088 base_ram_data_IOBUF[20]_inst/I + N19 OBUFT (Prop_obuft_I_O) 3.502 12.590 r base_ram_data_IOBUF[20]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.590 base_ram_data[20] + N19 r base_ram_data[20] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.590 + ------------------------------------------------------------------- + slack 0.732 + +Slack (MET) : 0.760ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[27] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.890ns (logic 6.863ns (46.087%) route 8.028ns (53.913%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.244 9.039 base_ram_data_IOBUF[27]_inst/T + P20 OBUFT (TriStatE_obuft_T_O) + 3.523 12.562 r base_ram_data_IOBUF[27]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.562 base_ram_data[27] + P20 r base_ram_data[27] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.562 + ------------------------------------------------------------------- + slack 0.760 + +Slack (MET) : 0.761ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[26] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.969ns (logic 5.252ns (35.086%) route 9.717ns (64.914%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.318 2.408 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/ADDRB0 + SLICE_X22Y82 RAMD32 (Prop_ramd32_RADR0_O) + 0.152 2.560 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB/O + net (fo=1, routed) 0.643 3.203 u_matmul_axi_slave/ep_rd_c0[26] + SLICE_X23Y81 LUT4 (Prop_lut4_I2_O) 0.348 3.551 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_22__0/O + net (fo=1, routed) 0.434 3.985 u_matmul_axi_slave/ram_reg_0_7_24_29_i_22__0_n_0 + SLICE_X23Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.109 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_16__0/O + net (fo=1, routed) 0.676 4.785 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[26] + SLICE_X26Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.909 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_10__1/O + net (fo=3, routed) 0.455 5.364 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[26] + SLICE_X27Y84 LUT3 (Prop_lut3_I0_O) 0.124 5.488 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[26]_inst_i_1/O + net (fo=2, routed) 3.522 9.010 ext_ram_data_IOBUF[26]_inst/I + AD20 OBUFT (Prop_obuft_I_O) 3.552 12.562 r ext_ram_data_IOBUF[26]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.562 ext_ram_data[26] + AD20 r ext_ram_data[26] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.562 + ------------------------------------------------------------------- + slack 0.761 + +Slack (MET) : 0.781ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[27] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.870ns (logic 6.901ns (46.406%) route 7.969ns (53.594%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.304 8.981 ext_ram_data_IOBUF[27]_inst/T + AB21 OBUFT (TriStatE_obuft_T_O) + 3.561 12.541 r ext_ram_data_IOBUF[27]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.541 ext_ram_data[27] + AB21 r ext_ram_data[27] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.541 + ------------------------------------------------------------------- + slack 0.781 + +Slack (MET) : 0.788ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[4] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.942ns (logic 5.261ns (35.206%) route 9.682ns (64.794%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.421 2.399 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 + SLICE_X22Y84 RAMD32 (Prop_ramd32_RADR1_O) + 0.153 2.552 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC/O + net (fo=1, routed) 0.575 3.127 u_matmul_axi_slave/ep_rd_c0[4] + SLICE_X23Y84 LUT4 (Prop_lut4_I2_O) 0.331 3.458 r u_matmul_axi_slave/ram_reg_i_66/O + net (fo=1, routed) 0.672 4.130 u_matmul_axi_slave/ram_reg_i_66_n_0 + SLICE_X26Y82 LUT5 (Prop_lut5_I4_O) 0.124 4.254 r u_matmul_axi_slave/ram_reg_i_48/O + net (fo=1, routed) 0.485 4.738 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[4] + SLICE_X27Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.862 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_32/O + net (fo=3, routed) 0.276 5.138 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[4] + SLICE_X27Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.262 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[4]_inst_i_1/O + net (fo=2, routed) 3.696 8.958 ext_ram_data_IOBUF[4]_inst/I + AF22 OBUFT (Prop_obuft_I_O) 3.577 12.535 r ext_ram_data_IOBUF[4]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.535 ext_ram_data[4] + AF22 r ext_ram_data[4] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.535 + ------------------------------------------------------------------- + slack 0.788 + +Slack (MET) : 0.790ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[5] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.940ns (logic 5.012ns (33.550%) route 9.928ns (66.450%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.421 2.399 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 + SLICE_X22Y84 RAMD32 (Prop_ramd32_RADR1_O) + 0.124 2.523 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/O + net (fo=1, routed) 0.664 3.188 u_matmul_axi_slave/ep_rd_c0[5] + SLICE_X24Y84 LUT4 (Prop_lut4_I2_O) 0.124 3.312 r u_matmul_axi_slave/ram_reg_i_65/O + net (fo=1, routed) 0.582 3.893 u_matmul_axi_slave/ram_reg_i_65_n_0 + SLICE_X26Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.017 r u_matmul_axi_slave/ram_reg_i_47/O + net (fo=1, routed) 0.489 4.506 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[5] + SLICE_X26Y81 LUT6 (Prop_lut6_I5_O) 0.124 4.630 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_31/O + net (fo=4, routed) 0.747 5.377 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_0 + SLICE_X20Y75 LUT3 (Prop_lut3_I0_O) 0.124 5.501 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[5]_inst_i_1/O + net (fo=2, routed) 3.467 8.968 ext_ram_data_IOBUF[5]_inst/I + AE21 OBUFT (Prop_obuft_I_O) 3.564 12.533 r ext_ram_data_IOBUF[5]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.533 ext_ram_data[5] + AE21 r ext_ram_data[5] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.533 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.795ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[2] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.935ns (logic 5.281ns (35.363%) route 9.654ns (64.637%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.300 2.389 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRB0 + SLICE_X20Y84 RAMD32 (Prop_ramd32_RADR0_O) + 0.152 2.541 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMB/O + net (fo=1, routed) 0.661 3.203 u_matmul_axi_slave/ep_rd_c1[2] + SLICE_X23Y83 LUT4 (Prop_lut4_I0_O) 0.348 3.551 r u_matmul_axi_slave/ram_reg_i_68/O + net (fo=1, routed) 0.507 4.057 u_matmul_axi_slave/ram_reg_i_68_n_0 + SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.181 r u_matmul_axi_slave/ram_reg_i_50/O + net (fo=1, routed) 0.598 4.780 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[2] + SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.904 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_34/O + net (fo=3, routed) 0.464 5.368 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[2] + SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.492 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[2]_inst_i_1/O + net (fo=2, routed) 3.454 8.946 ext_ram_data_IOBUF[2]_inst/I + AF23 OBUFT (Prop_obuft_I_O) 3.581 12.528 r ext_ram_data_IOBUF[2]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.528 ext_ram_data[2] + AF23 r ext_ram_data[2] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.528 + ------------------------------------------------------------------- + slack 0.795 + +Slack (MET) : 0.796ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.934ns (logic 5.264ns (35.250%) route 9.670ns (64.750%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT6=4 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=136, routed) 1.303 2.393 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA0 + SLICE_X22Y84 RAMD32 (Prop_ramd32_RADR0_O) + 0.150 2.543 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/O + net (fo=1, routed) 0.961 3.504 u_matmul_axi_slave/ep_rd_c0[0] + SLICE_X24Y82 LUT4 (Prop_lut4_I2_O) 0.328 3.832 r u_matmul_axi_slave/ram_reg_i_73/O + net (fo=1, routed) 0.667 4.499 u_matmul_axi_slave/ram_reg_i_73_n_0 + SLICE_X24Y82 LUT6 (Prop_lut6_I0_O) 0.124 4.623 r u_matmul_axi_slave/ram_reg_i_52/O + net (fo=1, routed) 0.414 5.036 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[0] + SLICE_X26Y82 LUT6 (Prop_lut6_I5_O) 0.124 5.160 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_36/O + net (fo=3, routed) 0.309 5.470 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] + SLICE_X27Y83 LUT3 (Prop_lut3_I0_O) 0.124 5.594 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O + net (fo=2, routed) 3.346 8.940 ext_ram_data_IOBUF[0]_inst/I + AF24 OBUFT (Prop_obuft_I_O) 3.586 12.526 r ext_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.526 ext_ram_data[0] + AF24 r ext_ram_data[0] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.526 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.801ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ch_mode_reg[2][1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_addr[15] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.932ns (logic 4.764ns (31.902%) route 10.168ns (68.098%)) + Logic Levels: 7 (LUT3=2 LUT5=1 LUT6=3 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.865ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.411ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.931 -2.411 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X37Y90 FDRE r u_snix_axil_cdma_mux_8ch/ch_mode_reg[2][1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y90 FDRE (Prop_fdre_C_Q) 0.456 -1.955 r u_snix_axil_cdma_mux_8ch/ch_mode_reg[2][1]/Q + net (fo=3, routed) 1.018 -0.936 u_snix_axil_cdma_mux_8ch/u_core_engine/ep_axi_addr_reg[0]_2[1] + SLICE_X37Y90 LUT6 (Prop_lut6_I5_O) 0.124 -0.812 r u_snix_axil_cdma_mux_8ch/u_core_engine/FSM_onehot_ep_state[6]_i_10/O + net (fo=62, routed) 0.448 -0.364 u_snix_axil_cdma_mux_8ch/u_core_engine_n_398 + SLICE_X36Y89 LUT3 (Prop_lut3_I1_O) 0.124 -0.240 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_30_35_i_9__1/O + net (fo=103, routed) 1.352 1.112 u_snix_axil_cdma_mux_8ch/u_core_engine/_zz_ram_port1_reg[31]_3 + SLICE_X49Y96 LUT5 (Prop_lut5_I1_O) 0.124 1.236 r u_snix_axil_cdma_mux_8ch/u_core_engine/ram_reg_0_3_12_17_i_9/O + net (fo=2, routed) 1.285 2.521 u_Axi_CDC/arFifo/dma_m_araddr[17] + SLICE_X41Y81 LUT3 (Prop_lut3_I2_O) 0.124 2.645 r u_Axi_CDC/arFifo/ax_req_q_addr[17]_i_2/O + net (fo=3, routed) 1.789 4.434 u_Axi_CDC/arFifo/ram_araddr[15] + SLICE_X8Y70 LUT6 (Prop_lut6_I0_O) 0.124 4.558 r u_Axi_CDC/arFifo/base_ram_addr_OBUF[15]_inst_i_3/O + net (fo=1, routed) 0.884 5.442 u_axi_ram/u_axi_sram_sp/ext_ram_addr[15] + SLICE_X2Y64 LUT6 (Prop_lut6_I2_O) 0.124 5.566 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[15]_inst_i_1/O + net (fo=2, routed) 3.391 8.958 ext_ram_addr_OBUF[15] + AF17 OBUF (Prop_obuf_I_O) 3.564 12.521 r ext_ram_addr_OBUF[15]_inst/O + net (fo=0) 0.000 12.521 ext_ram_addr[15] + AF17 r ext_ram_addr[15] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.521 + ------------------------------------------------------------------- + slack 0.801 + +Slack (MET) : 0.801ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[29] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.850ns (logic 6.891ns (46.403%) route 7.959ns (53.597%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.175 8.970 base_ram_data_IOBUF[29]_inst/T + N23 OBUFT (TriStatE_obuft_T_O) + 3.551 12.521 r base_ram_data_IOBUF[29]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.521 base_ram_data[29] + N23 r base_ram_data[29] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.521 + ------------------------------------------------------------------- + slack 0.801 + +Slack (MET) : 0.821ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_we_n + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.830ns (logic 6.884ns (46.415%) route 7.947ns (53.585%)) + Logic Levels: 13 (CARRY4=6 LUT2=1 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 2.411 7.306 u_axi_ram/u_axi_sram_sp/ax_req_q_burst_reg[0]_0 + SLICE_X1Y21 LUT2 (Prop_lut2_I0_O) 0.124 7.430 r u_axi_ram/u_axi_sram_sp/ext_ram_we_n_OBUF_inst_i_1/O + net (fo=1, routed) 1.529 8.958 ext_ram_we_n_OBUF + AD19 OBUF (Prop_obuf_I_O) 3.544 12.502 r ext_ram_we_n_OBUF_inst/O + net (fo=0) 0.000 12.502 ext_ram_we_n + AD19 r ext_ram_we_n (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.502 + ------------------------------------------------------------------- + slack 0.821 + +Slack (MET) : 0.822ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.828ns (logic 6.867ns (46.312%) route 7.961ns (53.688%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.177 8.973 base_ram_data_IOBUF[16]_inst/T + P21 OBUFT (TriStatE_obuft_T_O) + 3.527 12.500 r base_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.500 base_ram_data[16] + P21 r base_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.500 + ------------------------------------------------------------------- + slack 0.822 + +Slack (MET) : 0.823ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.828ns (logic 6.871ns (46.339%) route 7.957ns (53.661%)) + Logic Levels: 13 (CARRY4=6 LUT5=1 LUT6=5 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.454 5.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] + SLICE_X0Y74 LUT6 (Prop_lut6_I5_O) 0.124 5.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O + net (fo=1, routed) 3.496 8.968 base_ram_be_n_OBUF[0] + L20 OBUF (Prop_obuf_I_O) 3.531 12.499 r base_ram_be_n_OBUF[0]_inst/O + net (fo=0) 0.000 12.499 base_ram_be_n[0] + L20 r base_ram_be_n[0] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.499 + ------------------------------------------------------------------- + slack 0.823 + +Slack (MET) : 0.828ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[2] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.822ns (logic 6.875ns (46.384%) route 7.947ns (53.616%)) + Logic Levels: 13 (CARRY4=6 LUT5=1 LUT6=5 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.593 5.487 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y74 LUT6 (Prop_lut6_I5_O) 0.124 5.611 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[2]_inst_i_1/O + net (fo=1, routed) 3.348 8.959 base_ram_be_n_OBUF[2] + L23 OBUF (Prop_obuf_I_O) 3.535 12.494 r base_ram_be_n_OBUF[2]_inst/O + net (fo=0) 0.000 12.494 base_ram_be_n[2] + L23 r base_ram_be_n[2] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.494 + ------------------------------------------------------------------- + slack 0.828 + +Slack (MET) : 0.837ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[26] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.814ns (logic 6.873ns (46.396%) route 7.941ns (53.604%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.157 8.952 base_ram_data_IOBUF[26]_inst/T + R21 OBUFT (TriStatE_obuft_T_O) + 3.533 12.485 r base_ram_data_IOBUF[26]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.485 base_ram_data[26] + R21 r base_ram_data[26] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.485 + ------------------------------------------------------------------- + slack 0.837 + +Slack (MET) : 0.840ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_addr[8] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.811ns (logic 6.738ns (45.495%) route 8.072ns (54.505%)) + Logic Levels: 12 (CARRY4=6 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.832 4.091 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X3Y68 LUT6 (Prop_lut6_I5_O) 0.313 4.404 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[8]_inst_i_2/O + net (fo=2, routed) 0.840 5.244 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[8]_inst_i_2_n_0 + SLICE_X3Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.368 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[8]_inst_i_1/O + net (fo=2, routed) 3.591 8.960 ext_ram_addr_OBUF[8] + AA17 OBUF (Prop_obuf_I_O) 3.522 12.482 r ext_ram_addr_OBUF[8]_inst/O + net (fo=0) 0.000 12.482 ext_ram_addr[8] + AA17 r ext_ram_addr[8] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.482 + ------------------------------------------------------------------- + slack 0.840 + +Slack (MET) : 0.849ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_oe_n + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.802ns (logic 6.872ns (46.430%) route 7.929ns (53.570%)) + Logic Levels: 13 (CARRY4=6 LUT2=1 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.354 6.248 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y53 LUT2 (Prop_lut2_I1_O) 0.124 6.372 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_oe_n_OBUF_inst_i_1/O + net (fo=1, routed) 2.568 8.941 ext_ram_oe_n_OBUF + AB19 OBUF (Prop_obuf_I_O) 3.532 12.473 r ext_ram_oe_n_OBUF_inst/O + net (fo=0) 0.000 12.473 ext_ram_oe_n + AB19 r ext_ram_oe_n (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.473 + ------------------------------------------------------------------- + slack 0.849 + +Slack (MET) : 0.871ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[5] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.859ns (logic 4.987ns (33.560%) route 9.872ns (66.440%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.421 2.399 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 + SLICE_X22Y84 RAMD32 (Prop_ramd32_RADR1_O) + 0.124 2.523 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/O + net (fo=1, routed) 0.664 3.188 u_matmul_axi_slave/ep_rd_c0[5] + SLICE_X24Y84 LUT4 (Prop_lut4_I2_O) 0.124 3.312 r u_matmul_axi_slave/ram_reg_i_65/O + net (fo=1, routed) 0.582 3.893 u_matmul_axi_slave/ram_reg_i_65_n_0 + SLICE_X26Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.017 r u_matmul_axi_slave/ram_reg_i_47/O + net (fo=1, routed) 0.489 4.506 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[5] + SLICE_X26Y81 LUT6 (Prop_lut6_I5_O) 0.124 4.630 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_31/O + net (fo=4, routed) 0.747 5.377 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_0 + SLICE_X20Y75 LUT3 (Prop_lut3_I0_O) 0.124 5.501 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[5]_inst_i_1/O + net (fo=2, routed) 3.411 8.912 base_ram_data_IOBUF[5]_inst/I + P24 OBUFT (Prop_obuft_I_O) 3.539 12.451 r base_ram_data_IOBUF[5]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.451 base_ram_data[5] + P24 r base_ram_data[5] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.451 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.872ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[29] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.858ns (logic 4.995ns (33.620%) route 9.863ns (66.380%)) + Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.324 2.301 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/ADDRC1 + SLICE_X22Y82 RAMD32 (Prop_ramd32_RADR1_O) + 0.124 2.425 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMC_D1/O + net (fo=1, routed) 0.709 3.134 u_matmul_axi_slave/ep_rd_c0[29] + SLICE_X24Y82 LUT4 (Prop_lut4_I2_O) 0.124 3.258 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_23__0/O + net (fo=1, routed) 0.481 3.738 u_matmul_axi_slave/ram_reg_0_7_24_29_i_23__0_n_0 + SLICE_X25Y82 LUT5 (Prop_lut5_I4_O) 0.124 3.862 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_17__0/O + net (fo=1, routed) 0.578 4.441 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[29] + SLICE_X30Y81 LUT6 (Prop_lut6_I5_O) 0.124 4.565 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_11__1/O + net (fo=3, routed) 0.456 5.021 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[29] + SLICE_X31Y82 LUT3 (Prop_lut3_I0_O) 0.124 5.145 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[29]_inst_i_1/O + net (fo=2, routed) 3.758 8.903 ext_ram_data_IOBUF[29]_inst/I + AC21 OBUFT (Prop_obuft_I_O) 3.547 12.451 r ext_ram_data_IOBUF[29]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.451 ext_ram_data[29] + AC21 r ext_ram_data[29] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.451 + ------------------------------------------------------------------- + slack 0.872 + +Slack (MET) : 0.875ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.776ns (logic 6.875ns (46.530%) route 7.901ns (53.470%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.116 8.912 base_ram_data_IOBUF[23]_inst/T + N21 OBUFT (TriStatE_obuft_T_O) + 3.535 12.447 r base_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.447 base_ram_data[23] + N21 r base_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.447 + ------------------------------------------------------------------- + slack 0.875 + +Slack (MET) : 0.889ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.762ns (logic 6.871ns (46.543%) route 7.891ns (53.457%)) + Logic Levels: 13 (CARRY4=6 LUT5=1 LUT6=5 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.457 5.351 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y74 LUT6 (Prop_lut6_I5_O) 0.124 5.475 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 3.427 8.903 base_ram_be_n_OBUF[1] + L22 OBUF (Prop_obuf_I_O) 3.531 12.433 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 12.433 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.433 + ------------------------------------------------------------------- + slack 0.889 + +Slack (MET) : 0.896ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[7] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.834ns (logic 4.899ns (33.025%) route 9.935ns (66.975%)) + Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.868ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.408ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q + net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] + SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O + net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] + SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] + SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O + net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 + SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) + 0.124 2.792 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB_D1/O + net (fo=1, routed) 1.211 4.003 u_matmul_axi_slave/ep_rd_c1[39] + SLICE_X21Y80 LUT5 (Prop_lut5_I3_O) 0.124 4.127 r u_matmul_axi_slave/ram_reg_i_45/O + net (fo=1, routed) 0.499 4.626 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[7] + SLICE_X17Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.750 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_29/O + net (fo=4, routed) 0.556 5.306 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_2 + SLICE_X15Y79 LUT3 (Prop_lut3_I0_O) 0.124 5.430 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[7]_inst_i_1/O + net (fo=2, routed) 3.422 8.852 ext_ram_data_IOBUF[7]_inst/I + AF20 OBUFT (Prop_obuft_I_O) 3.575 12.426 r ext_ram_data_IOBUF[7]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.426 ext_ram_data[7] + AF20 r ext_ram_data[7] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.426 + ------------------------------------------------------------------- + slack 0.896 + +Slack (MET) : 0.897ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[28] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.754ns (logic 6.876ns (46.603%) route 7.878ns (53.397%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.094 8.890 base_ram_data_IOBUF[28]_inst/T + N22 OBUFT (TriStatE_obuft_T_O) + 3.536 12.425 r base_ram_data_IOBUF[28]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.425 base_ram_data[28] + N22 r base_ram_data[28] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.425 + ------------------------------------------------------------------- + slack 0.897 + +Slack (MET) : 0.940ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[22] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.711ns (logic 6.892ns (46.850%) route 7.819ns (53.150%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.035 8.830 base_ram_data_IOBUF[22]_inst/T + N24 OBUFT (TriStatE_obuft_T_O) + 3.552 12.383 r base_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.383 base_ram_data[22] + N24 r base_ram_data[22] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.383 + ------------------------------------------------------------------- + slack 0.940 + +Slack (MET) : 0.944ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[28] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.707ns (logic 6.908ns (46.969%) route 7.799ns (53.031%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.134 8.811 ext_ram_data_IOBUF[28]_inst/T + AD21 OBUFT (TriStatE_obuft_T_O) + 3.568 12.378 r ext_ram_data_IOBUF[28]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.378 ext_ram_data[28] + AD21 r ext_ram_data[28] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.378 + ------------------------------------------------------------------- + slack 0.944 + +Slack (MET) : 0.945ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[4] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.706ns (logic 6.913ns (47.012%) route 7.792ns (52.988%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.008 8.804 base_ram_data_IOBUF[4]_inst/T + N26 OBUFT (TriStatE_obuft_T_O) + 3.573 12.377 r base_ram_data_IOBUF[4]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.377 base_ram_data[4] + N26 r base_ram_data[4] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.377 + ------------------------------------------------------------------- + slack 0.945 + +Slack (MET) : 0.953ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[7] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 14.698ns (logic 6.900ns (46.942%) route 7.799ns (53.058%)) + Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.329ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q + net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] + SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O + net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 + SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O + net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] + SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) + 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] + net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 + SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] + net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 + SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] + net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] + SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O + net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 + SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] + net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.014 8.810 base_ram_data_IOBUF[7]_inst/T + P25 OBUFT (TriStatE_obuft_T_O) + 3.560 12.370 r base_ram_data_IOBUF[7]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.370 base_ram_data[7] + P25 r base_ram_data[7] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.102 13.622 + output delay -0.300 13.322 + ------------------------------------------------------------------- + required time 13.322 + arrival time -12.370 + ------------------------------------------------------------------- + slack 0.953 @@ -14400,6175 +14923,157 @@ Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X2Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X2Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X2Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X2Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y6 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y68 cdma_axil_b_bridge_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X24Y67 cdma_axil_r_bridge_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y67 cdma_axil_wr_active_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y67 cdma_axil_wr_bridge_hold_reg/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[1]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[5]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[6]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[7]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[9]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[11]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X20Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[13]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[14]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[1]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[2]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[3]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[4]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[5]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[6]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[7]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[9]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y121 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[34]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y121 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[35]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[36]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[37]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[38]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[39]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X11Y112 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[3]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[40]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[41]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[42]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[43]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X69Y104 cdma_axil_b_bridge_reg/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X46Y92 u_matmul_axi_slave/b0_b_reg[0][0]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X72Y108 cdma_axil_r_bridge_reg/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X67Y105 cdma_axil_wr_active_reg/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X69Y105 cdma_axil_wr_bridge_hold_reg/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X12Y105 u_matmul_axi_slave/b0_b_reg[0][10]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y92 u_matmul_axi_slave/b0_b_reg[0][11]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y79 u_matmul_axi_slave/b0_b_reg[0][12]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X4Y86 u_matmul_axi_slave/b0_b_reg[0][13]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X22Y103 u_matmul_axi_slave/b0_b_reg[0][14]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X2Y94 u_matmul_axi_slave/b0_b_reg[0][15]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X4Y86 u_matmul_axi_slave/b0_b_reg[0][16]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X37Y77 u_matmul_axi_slave/b0_b_reg[0][17]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X34Y76 u_matmul_axi_slave/b0_b_reg[0][18]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X47Y74 u_matmul_axi_slave/b0_b_reg[0][19]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y92 u_matmul_axi_slave/b0_b_reg[0][1]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X46Y78 u_matmul_axi_slave/b0_b_reg[0][20]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y69 u_matmul_axi_slave/b0_b_reg[0][21]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X2Y94 u_matmul_axi_slave/b0_b_reg[0][22]/C Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: sys_clk - To Clock: mlkem_clk_clk_pll - -Setup : 0 Failing Endpoints, Worst Slack 14.363ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 14.363ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.986ns (logic 1.344ns (26.958%) route 3.642ns (73.042%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 3.642 22.469 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[12] - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/C - clock pessimism -0.601 37.289 - clock uncertainty -0.197 37.092 - SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.260 36.832 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12] - ------------------------------------------------------------------- - required time 36.832 - arrival time -22.469 - ------------------------------------------------------------------- - slack 14.363 - -Slack (MET) : 14.642ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.902ns (logic 1.317ns (26.864%) route 3.585ns (73.136%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.800 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 3.585 22.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[15] - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/C - clock pessimism -0.601 37.289 - clock uncertainty -0.197 37.092 - SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.064 37.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 37.028 - arrival time -22.386 - ------------------------------------------------------------------- - slack 14.642 - -Slack (MET) : 14.889ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.419ns (logic 1.344ns (30.411%) route 3.075ns (69.589%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.829 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 3.075 21.905 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[18] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.299 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18] - ------------------------------------------------------------------- - required time 36.794 - arrival time -21.905 - ------------------------------------------------------------------- - slack 14.889 - -Slack (MET) : 15.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.297ns (logic 1.336ns (31.089%) route 2.961ns (68.911%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.821 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 2.961 21.783 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[28] - SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/C - clock pessimism -0.601 37.291 - clock uncertainty -0.197 37.094 - SLICE_X116Y76 FDRE (Setup_fdre_C_D) -0.252 36.842 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28] - ------------------------------------------------------------------- - required time 36.842 - arrival time -21.783 - ------------------------------------------------------------------- - slack 15.059 - -Slack (MET) : 15.085ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.257ns (logic 1.344ns (31.570%) route 2.913ns (68.429%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.829 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 2.913 21.743 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.266 36.827 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24] - ------------------------------------------------------------------- - required time 36.827 - arrival time -21.743 - ------------------------------------------------------------------- - slack 15.085 - -Slack (MET) : 15.131ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.202ns (logic 1.344ns (31.982%) route 2.858ns (68.018%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.511ns = ( 17.489 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.831 17.489 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/WCLK - SLICE_X56Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.833 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/O - net (fo=1, routed) 2.858 21.692 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[36] - SLICE_X110Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X110Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/C - clock pessimism -0.601 37.291 - clock uncertainty -0.197 37.094 - SLICE_X110Y71 FDRE (Setup_fdre_C_D) -0.271 36.823 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 36.823 - arrival time -21.692 - ------------------------------------------------------------------- - slack 15.131 - -Slack (MET) : 15.149ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.015ns (logic 1.344ns (33.474%) route 2.671ns (66.526%)) - Logic Levels: 0 - Clock Path Skew: -0.327ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) - Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.926 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/O - net (fo=1, routed) 2.671 21.597 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[6] - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/C - clock pessimism -0.601 37.256 - clock uncertainty -0.197 37.059 - SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.313 36.746 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 36.746 - arrival time -21.597 - ------------------------------------------------------------------- - slack 15.149 - -Slack (MET) : 15.187ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.166ns (logic 1.336ns (32.067%) route 2.830ns (67.933%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.821 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 2.830 21.652 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[22] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.254 36.839 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22] - ------------------------------------------------------------------- - required time 36.839 - arrival time -21.652 - ------------------------------------------------------------------- - slack 15.187 - -Slack (MET) : 15.190ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.336ns (logic 1.314ns (30.303%) route 3.022ns (69.697%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 3.022 21.822 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[23] - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.081 37.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 37.012 - arrival time -21.822 - ------------------------------------------------------------------- - slack 15.190 - -Slack (MET) : 15.238ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.936ns (logic 1.344ns (34.149%) route 2.592ns (65.851%)) - Logic Levels: 0 - Clock Path Skew: -0.321ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.139ns = ( 37.861 - 40.000 ) - Source Clock Delay (SCD): -2.420ns = ( 17.580 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.922 17.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.924 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/O - net (fo=1, routed) 2.592 21.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[0] - SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.689 37.861 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/C - clock pessimism -0.601 37.260 - clock uncertainty -0.197 37.063 - SLICE_X77Y70 FDRE (Setup_fdre_C_D) -0.309 36.754 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0] - ------------------------------------------------------------------- - required time 36.754 - arrival time -21.516 - ------------------------------------------------------------------- - slack 15.238 - -Slack (MET) : 15.346ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.027ns (logic 1.336ns (33.179%) route 2.691ns (66.821%)) - Logic Levels: 0 - Clock Path Skew: -0.193ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 2.691 21.510 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[16] - SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/C - clock pessimism -0.601 37.291 - clock uncertainty -0.197 37.094 - SLICE_X116Y76 FDRE (Setup_fdre_C_D) -0.238 36.856 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16] - ------------------------------------------------------------------- - required time 36.856 - arrival time -21.510 - ------------------------------------------------------------------- - slack 15.346 - -Slack (MET) : 15.359ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.218ns (logic 1.317ns (31.224%) route 2.901ns (68.776%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.807 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 2.901 21.708 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[3] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.028 37.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3] - ------------------------------------------------------------------- - required time 37.067 - arrival time -21.708 - ------------------------------------------------------------------- - slack 15.359 - -Slack (MET) : 15.360ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.008ns (logic 1.336ns (33.331%) route 2.672ns (66.669%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.826 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/O - net (fo=1, routed) 2.672 21.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[4] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.237 36.858 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 36.858 - arrival time -21.499 - ------------------------------------------------------------------- - slack 15.360 - -Slack (MET) : 15.365ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.184ns (logic 1.309ns (31.283%) route 2.875ns (68.717%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.792 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 2.875 21.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[13] - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/C - clock pessimism -0.601 37.289 - clock uncertainty -0.197 37.092 - SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.059 37.033 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13] - ------------------------------------------------------------------- - required time 37.033 - arrival time -21.668 - ------------------------------------------------------------------- - slack 15.365 - -Slack (MET) : 15.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.144ns (logic 1.309ns (31.591%) route 2.835ns (68.409%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.794 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 2.835 21.629 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[19] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.093 37.000 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19] - ------------------------------------------------------------------- - required time 37.000 - arrival time -21.629 - ------------------------------------------------------------------- - slack 15.371 - -Slack (MET) : 15.375ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.000ns (logic 1.309ns (32.724%) route 2.691ns (67.276%)) - Logic Levels: 0 - Clock Path Skew: -0.327ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) - Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O - net (fo=1, routed) 2.691 21.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7] - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/C - clock pessimism -0.601 37.256 - clock uncertainty -0.197 37.059 - SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.102 36.957 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7] - ------------------------------------------------------------------- - required time 36.957 - arrival time -21.583 - ------------------------------------------------------------------- - slack 15.375 - -Slack (MET) : 15.382ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.988ns (logic 1.344ns (33.703%) route 2.644ns (66.297%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.834 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 2.644 21.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[0] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.235 36.860 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0] - ------------------------------------------------------------------- - required time 36.860 - arrival time -21.478 - ------------------------------------------------------------------- - slack 15.382 - -Slack (MET) : 15.406ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.814ns (logic 1.344ns (35.240%) route 2.470ns (64.760%)) - Logic Levels: 0 - Clock Path Skew: -0.324ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.919 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O - net (fo=1, routed) 2.470 21.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0] - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/C - clock pessimism -0.601 37.252 - clock uncertainty -0.197 37.055 - SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.260 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0] - ------------------------------------------------------------------- - required time 36.795 - arrival time -21.389 - ------------------------------------------------------------------- - slack 15.406 - -Slack (MET) : 15.426ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.896ns (logic 1.343ns (34.471%) route 2.553ns (65.529%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.826 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 2.553 21.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[14] - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/C - clock pessimism -0.601 37.289 - clock uncertainty -0.197 37.092 - SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.287 36.805 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 36.805 - arrival time -21.379 - ------------------------------------------------------------------- - slack 15.426 - -Slack (MET) : 15.429ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.762ns (logic 1.343ns (35.695%) route 2.419ns (64.305%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.919 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/O - net (fo=1, routed) 2.419 21.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[8] - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/C - clock pessimism -0.601 37.252 - clock uncertainty -0.197 37.055 - SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.287 36.768 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 36.768 - arrival time -21.339 - ------------------------------------------------------------------- - slack 15.429 - -Slack (MET) : 15.440ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.128ns (logic 1.314ns (31.835%) route 2.814ns (68.165%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 2.814 21.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[29] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.040 37.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29] - ------------------------------------------------------------------- - required time 37.053 - arrival time -21.613 - ------------------------------------------------------------------- - slack 15.440 - -Slack (MET) : 15.459ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.955ns (logic 1.317ns (33.302%) route 2.638ns (66.698%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.893 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/O - net (fo=1, routed) 2.638 21.531 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[9] - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/C - clock pessimism -0.601 37.252 - clock uncertainty -0.197 37.055 - SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.065 36.990 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9] - ------------------------------------------------------------------- - required time 36.990 - arrival time -21.531 - ------------------------------------------------------------------- - slack 15.459 - -Slack (MET) : 15.477ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.733ns (logic 1.336ns (35.784%) route 2.397ns (64.216%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.912 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/O - net (fo=1, routed) 2.397 21.310 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[10] - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/C - clock pessimism -0.601 37.252 - clock uncertainty -0.197 37.055 - SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.268 36.787 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10] - ------------------------------------------------------------------- - required time 36.787 - arrival time -21.310 - ------------------------------------------------------------------- - slack 15.477 - -Slack (MET) : 15.480ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.063ns (logic 1.314ns (32.340%) route 2.749ns (67.660%)) - Logic Levels: 0 - Clock Path Skew: -0.194ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.797 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 2.749 21.547 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[17] - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.067 37.026 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17] - ------------------------------------------------------------------- - required time 37.026 - arrival time -21.547 - ------------------------------------------------------------------- - slack 15.480 - -Slack (MET) : 15.482ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.864ns (logic 1.344ns (34.786%) route 2.520ns (65.214%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 2.520 21.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[30] - SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X117Y77 FDRE (Setup_fdre_C_D) -0.271 36.824 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 36.824 - arrival time -21.342 - ------------------------------------------------------------------- - slack 15.482 - -Slack (MET) : 15.506ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.864ns (logic 1.317ns (34.080%) route 2.547ns (65.920%)) - Logic Levels: 0 - Clock Path Skew: -0.328ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) - Source Clock Delay (SCD): -2.417ns = ( 17.583 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.925 17.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK - SLICE_X36Y66 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y66 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.900 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/O - net (fo=1, routed) 2.547 21.448 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[15] - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/C - clock pessimism -0.601 37.256 - clock uncertainty -0.197 37.059 - SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.105 36.954 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 36.954 - arrival time -21.448 - ------------------------------------------------------------------- - slack 15.506 - -Slack (MET) : 15.550ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.822ns (logic 1.309ns (34.245%) route 2.513ns (65.755%)) - Logic Levels: 0 - Clock Path Skew: -0.328ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) - Source Clock Delay (SCD): -2.417ns = ( 17.583 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.925 17.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK - SLICE_X36Y66 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y66 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.892 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/O - net (fo=1, routed) 2.513 21.406 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[13] - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/C - clock pessimism -0.601 37.256 - clock uncertainty -0.197 37.059 - SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.103 36.956 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13] - ------------------------------------------------------------------- - required time 36.956 - arrival time -21.406 - ------------------------------------------------------------------- - slack 15.550 - -Slack (MET) : 15.552ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.834ns (logic 1.309ns (34.141%) route 2.525ns (65.859%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.884 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/O - net (fo=1, routed) 2.525 21.410 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[1] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.093 36.961 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1] - ------------------------------------------------------------------- - required time 36.961 - arrival time -21.410 - ------------------------------------------------------------------- - slack 15.552 - -Slack (MET) : 15.552ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.012ns (logic 1.317ns (32.824%) route 2.695ns (67.176%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.802 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 2.695 21.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[27] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.043 37.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27] - ------------------------------------------------------------------- - required time 37.050 - arrival time -21.498 - ------------------------------------------------------------------- - slack 15.552 - -Slack (MET) : 15.555ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.961ns (logic 1.317ns (33.248%) route 2.644ns (66.752%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.802 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 2.644 21.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[21] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.092 37.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 37.001 - arrival time -21.447 - ------------------------------------------------------------------- - slack 15.555 - -Slack (MET) : 15.555ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.607ns (logic 1.343ns (37.237%) route 2.264ns (62.763%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.918 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O - net (fo=1, routed) 2.264 21.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.317 36.737 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2] - ------------------------------------------------------------------- - required time 36.737 - arrival time -21.182 - ------------------------------------------------------------------- - slack 15.555 - -Slack (MET) : 15.654ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.719ns (logic 1.309ns (35.195%) route 2.410ns (64.805%)) - Logic Levels: 0 - Clock Path Skew: -0.328ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.150ns = ( 37.850 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.885 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/O - net (fo=1, routed) 2.410 21.296 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[7] - SLICE_X78Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.678 37.850 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X78Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/C - clock pessimism -0.601 37.249 - clock uncertainty -0.197 37.052 - SLICE_X78Y72 FDRE (Setup_fdre_C_D) -0.103 36.949 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7] - ------------------------------------------------------------------- - required time 36.949 - arrival time -21.296 - ------------------------------------------------------------------- - slack 15.654 - -Slack (MET) : 15.659ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.762ns (logic 1.317ns (35.012%) route 2.445ns (64.988%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.892 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/O - net (fo=1, routed) 2.445 21.337 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[3] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.058 36.996 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3] - ------------------------------------------------------------------- - required time 36.996 - arrival time -21.337 - ------------------------------------------------------------------- - slack 15.659 - -Slack (MET) : 15.683ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.690ns (logic 1.309ns (35.473%) route 2.381ns (64.527%)) - Logic Levels: 0 - Clock Path Skew: -0.328ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.146ns = ( 37.854 - 40.000 ) - Source Clock Delay (SCD): -2.420ns = ( 17.580 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.922 17.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/O - net (fo=1, routed) 2.381 21.271 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[1] - SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.682 37.854 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/C - clock pessimism -0.601 37.253 - clock uncertainty -0.197 37.056 - SLICE_X78Y68 FDRE (Setup_fdre_C_D) -0.103 36.953 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1] - ------------------------------------------------------------------- - required time 36.953 - arrival time -21.271 - ------------------------------------------------------------------- - slack 15.683 - -Slack (MET) : 15.729ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.413ns (logic 1.343ns (39.347%) route 2.070ns (60.653%)) - Logic Levels: 0 - Clock Path Skew: -0.330ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.146ns = ( 37.854 - 40.000 ) - Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.925 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/O - net (fo=1, routed) 2.070 20.996 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[8] - SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.682 37.854 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/C - clock pessimism -0.601 37.253 - clock uncertainty -0.197 37.056 - SLICE_X78Y68 FDRE (Setup_fdre_C_D) -0.332 36.724 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 36.724 - arrival time -20.996 - ------------------------------------------------------------------- - slack 15.729 - -Slack (MET) : 15.768ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.779ns (logic 1.309ns (34.643%) route 2.470ns (65.357%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.794 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 2.470 21.264 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.061 37.032 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25] - ------------------------------------------------------------------- - required time 37.032 - arrival time -21.264 - ------------------------------------------------------------------- - slack 15.768 - -Slack (MET) : 15.770ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.381ns (logic 1.343ns (39.723%) route 2.038ns (60.277%)) - Logic Levels: 0 - Clock Path Skew: -0.324ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.139ns = ( 37.861 - 40.000 ) - Source Clock Delay (SCD): -2.417ns = ( 17.583 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.925 17.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK - SLICE_X36Y66 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y66 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.926 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 2.038 20.964 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[14] - SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.689 37.861 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C - clock pessimism -0.601 37.260 - clock uncertainty -0.197 37.063 - SLICE_X77Y70 FDRE (Setup_fdre_C_D) -0.329 36.734 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 36.734 - arrival time -20.964 - ------------------------------------------------------------------- - slack 15.770 - -Slack (MET) : 15.794ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.497ns (logic 1.343ns (38.409%) route 2.154ns (61.591%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.828 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 2.154 20.982 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[20] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.317 36.776 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20] - ------------------------------------------------------------------- - required time 36.776 - arrival time -20.982 - ------------------------------------------------------------------- - slack 15.794 - -Slack (MET) : 15.816ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.720ns (logic 1.309ns (35.188%) route 2.411ns (64.812%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.787 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 2.411 21.198 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[31] - SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X117Y77 FDRE (Setup_fdre_C_D) -0.081 37.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31] - ------------------------------------------------------------------- - required time 37.014 - arrival time -21.198 - ------------------------------------------------------------------- - slack 15.816 - -Slack (MET) : 15.821ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.408ns (logic 1.336ns (39.197%) route 2.072ns (60.803%)) - Logic Levels: 0 - Clock Path Skew: -0.320ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.136ns = ( 37.864 - 40.000 ) - Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.918 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/O - net (fo=1, routed) 2.072 20.991 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[10] - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.692 37.864 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/C - clock pessimism -0.601 37.263 - clock uncertainty -0.197 37.066 - SLICE_X76Y67 FDRE (Setup_fdre_C_D) -0.254 36.812 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10] - ------------------------------------------------------------------- - required time 36.812 - arrival time -20.991 - ------------------------------------------------------------------- - slack 15.821 - -Slack (MET) : 15.826ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.590ns (logic 1.314ns (36.599%) route 2.276ns (63.401%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/O - net (fo=1, routed) 2.276 21.166 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[5] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.062 36.992 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5] - ------------------------------------------------------------------- - required time 36.992 - arrival time -21.166 - ------------------------------------------------------------------- - slack 15.826 - -Slack (MET) : 15.830ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.395ns (logic 1.336ns (39.356%) route 2.059ns (60.644%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.911 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 2.059 20.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[4] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.254 36.800 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 36.800 - arrival time -20.970 - ------------------------------------------------------------------- - slack 15.830 - -Slack (MET) : 15.834ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.501ns (logic 1.343ns (38.357%) route 2.158ns (61.643%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.833 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 2.158 20.992 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[2] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.269 36.826 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2] - ------------------------------------------------------------------- - required time 36.826 - arrival time -20.992 - ------------------------------------------------------------------- - slack 15.834 - -Slack (MET) : 15.836ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.395ns (logic 1.344ns (39.592%) route 2.051ns (60.408%)) - Logic Levels: 0 - Clock Path Skew: -0.326ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.920 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/O - net (fo=1, routed) 2.051 20.971 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[6] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.247 36.807 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 36.807 - arrival time -20.971 - ------------------------------------------------------------------- - slack 15.836 - -Slack (MET) : 15.842ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.469ns (logic 1.344ns (38.739%) route 2.125ns (61.261%)) - Logic Levels: 0 - Clock Path Skew: -0.185ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.525ns = ( 17.475 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.475 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 2.125 20.945 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6] - SLICE_X114Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/C - clock pessimism -0.601 37.291 - clock uncertainty -0.197 37.094 - SLICE_X114Y72 FDRE (Setup_fdre_C_D) -0.307 36.787 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 36.787 - arrival time -20.945 - ------------------------------------------------------------------- - slack 15.842 - -Slack (MET) : 15.908ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.473ns (logic 1.336ns (38.463%) route 2.137ns (61.537%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.814 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 2.137 20.952 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[34] - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X116Y77 FDRE (Setup_fdre_C_D) -0.235 36.860 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 36.860 - arrival time -20.952 - ------------------------------------------------------------------- - slack 15.908 - -Slack (MET) : 15.958ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.613ns (logic 1.317ns (36.447%) route 2.296ns (63.553%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.795 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/O - net (fo=1, routed) 2.296 21.092 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[33] - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X116Y77 FDRE (Setup_fdre_C_D) -0.045 37.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time 37.050 - arrival time -21.092 - ------------------------------------------------------------------- - slack 15.958 - -Slack (MET) : 15.958ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.633ns (logic 1.314ns (36.165%) route 2.319ns (63.835%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.804 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 2.319 21.124 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[5] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.013 37.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5] - ------------------------------------------------------------------- - required time 37.082 - arrival time -21.124 - ------------------------------------------------------------------- - slack 15.958 - -Slack (MET) : 15.961ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.365ns (logic 1.343ns (39.913%) route 2.022ns (60.087%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.828 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 2.022 20.850 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[26] - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.282 36.811 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26] - ------------------------------------------------------------------- - required time 36.811 - arrival time -20.850 - ------------------------------------------------------------------- - slack 15.961 - -Slack (MET) : 15.990ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.572ns (logic 1.309ns (36.651%) route 2.263ns (63.349%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 2.263 21.062 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.043 37.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1] - ------------------------------------------------------------------- - required time 37.052 - arrival time -21.062 - ------------------------------------------------------------------- - slack 15.990 - - - - - ---------------------------------------------------------------------------------------------------- -From Clock: mlkem_clk_clk_pll - To Clock: sys_clk - -Setup : 0 Failing Endpoints, Worst Slack 16.175ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 16.175ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.211ns (logic 1.343ns (41.819%) route 1.868ns (58.181%)) - Logic Levels: 0 - Clock Path Skew: -0.112ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.178 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 1.868 0.691 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[14] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.305 16.866 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 16.866 - arrival time -0.691 - ------------------------------------------------------------------- - slack 16.175 - -Slack (MET) : 16.288ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.133ns (logic 1.344ns (42.898%) route 1.789ns (57.102%)) - Logic Levels: 0 - Clock Path Skew: -0.112ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.177 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 1.789 0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.271 16.900 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12] - ------------------------------------------------------------------- - required time 16.900 - arrival time -0.612 - ------------------------------------------------------------------- - slack 16.288 - -Slack (MET) : 16.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.253ns (logic 1.309ns (40.244%) route 1.944ns (59.756%)) - Logic Levels: 0 - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O - net (fo=1, routed) 1.944 0.738 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.109 17.060 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7] - ------------------------------------------------------------------- - required time 17.060 - arrival time -0.738 - ------------------------------------------------------------------- - slack 16.322 - -Slack (MET) : 16.382ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.989ns (logic 1.343ns (44.934%) route 1.646ns (55.066%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.173 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 1.646 0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.316 16.855 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2] - ------------------------------------------------------------------- - required time 16.855 - arrival time -0.473 - ------------------------------------------------------------------- - slack 16.382 - -Slack (MET) : 16.446ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.152ns (logic 1.309ns (41.524%) route 1.843ns (58.476%)) - Logic Levels: 0 - Clock Path Skew: -0.112ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.212 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 1.843 0.632 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.093 17.078 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13] - ------------------------------------------------------------------- - required time 17.078 - arrival time -0.632 - ------------------------------------------------------------------- - slack 16.446 - -Slack (MET) : 16.520ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.917ns (logic 1.336ns (45.800%) route 1.581ns (54.200%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.180 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O - net (fo=1, routed) 1.581 0.401 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.250 16.921 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 16.921 - arrival time -0.401 - ------------------------------------------------------------------- - slack 16.520 - -Slack (MET) : 16.587ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.822ns (logic 1.336ns (47.335%) route 1.486ns (52.665%)) - Logic Levels: 0 - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.179 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O - net (fo=1, routed) 1.486 0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.274 16.895 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10] - ------------------------------------------------------------------- - required time 16.895 - arrival time -0.308 - ------------------------------------------------------------------- - slack 16.587 - -Slack (MET) : 16.599ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.995ns (logic 1.309ns (43.709%) route 1.686ns (56.291%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 1.686 0.479 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.093 17.078 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1] - ------------------------------------------------------------------- - required time 17.078 - arrival time -0.479 - ------------------------------------------------------------------- - slack 16.599 - -Slack (MET) : 16.680ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.736ns (logic 1.344ns (49.121%) route 1.392ns (50.879%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.172 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 1.392 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.271 16.900 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0] - ------------------------------------------------------------------- - required time 16.900 - arrival time -0.221 - ------------------------------------------------------------------- - slack 16.680 - -Slack (MET) : 16.714ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.930ns (logic 1.314ns (44.850%) route 1.616ns (55.150%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 1.616 0.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.043 17.128 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5] - ------------------------------------------------------------------- - required time 17.128 - arrival time -0.414 - ------------------------------------------------------------------- - slack 16.714 - -Slack (MET) : 16.930ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.383ns (logic 1.343ns (56.369%) route 1.040ns (43.631%)) - Logic Levels: 0 - Clock Path Skew: -0.205ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.177 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 1.040 -0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.286 16.793 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26] - ------------------------------------------------------------------- - required time 16.793 - arrival time 0.137 - ------------------------------------------------------------------- - slack 16.930 - -Slack (MET) : 16.970ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.472ns (logic 1.344ns (54.377%) route 1.128ns (45.623%)) - Logic Levels: 0 - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.171 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 1.128 -0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.244 16.927 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 16.927 - arrival time 0.043 - ------------------------------------------------------------------- - slack 16.970 - -Slack (MET) : 16.987ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.297ns (logic 1.343ns (58.459%) route 0.954ns (41.541%)) - Logic Levels: 0 - Clock Path Skew: -0.202ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.180 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 0.954 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.317 16.762 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20] - ------------------------------------------------------------------- - required time 16.762 - arrival time 0.225 - ------------------------------------------------------------------- - slack 16.987 - -Slack (MET) : 16.991ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.542ns (logic 1.317ns (51.811%) route 1.225ns (48.189%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.022ns = ( 17.978 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O - net (fo=1, routed) 1.225 0.128 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 17.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C - clock pessimism -0.601 17.377 - clock uncertainty -0.197 17.180 - SLICE_X19Y76 FDRE (Setup_fdre_C_D) -0.061 17.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time 17.119 - arrival time -0.128 - ------------------------------------------------------------------- - slack 16.991 - -Slack (MET) : 17.017ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.587ns (logic 1.317ns (50.909%) route 1.270ns (49.091%)) - Logic Levels: 0 - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.199 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 1.270 0.071 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.081 17.088 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3] - ------------------------------------------------------------------- - required time 17.088 - arrival time -0.071 - ------------------------------------------------------------------- - slack 17.017 - -Slack (MET) : 17.045ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.595ns (logic 1.317ns (50.744%) route 1.278ns (49.256%)) - Logic Levels: 0 - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.198 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 1.278 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.043 17.126 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9] - ------------------------------------------------------------------- - required time 17.126 - arrival time -0.081 - ------------------------------------------------------------------- - slack 17.045 - -Slack (MET) : 17.067ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.418ns (logic 0.456ns (18.857%) route 1.962ns (81.143%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) - Source Clock Delay (SCD): -2.419ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.923 -2.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.456 -1.963 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 1.962 -0.000 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] - SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.798 17.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.601 17.369 - clock uncertainty -0.197 17.172 - SLICE_X24Y73 FDCE (Setup_fdce_C_D) -0.105 17.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 17.067 - arrival time 0.000 - ------------------------------------------------------------------- - slack 17.067 - -Slack (MET) : 17.092ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.462ns (logic 1.314ns (53.376%) route 1.148ns (46.624%)) - Logic Levels: 0 - Clock Path Skew: -0.207ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 1.148 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.043 17.034 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29] - ------------------------------------------------------------------- - required time 17.034 - arrival time 0.058 - ------------------------------------------------------------------- - slack 17.092 - -Slack (MET) : 17.095ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.436ns (logic 1.317ns (54.066%) route 1.119ns (45.934%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) - Source Clock Delay (SCD): -2.409ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.092 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O - net (fo=1, routed) 1.119 0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C - clock pessimism -0.601 17.380 - clock uncertainty -0.197 17.183 - SLICE_X17Y78 FDRE (Setup_fdre_C_D) -0.061 17.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39] - ------------------------------------------------------------------- - required time 17.122 - arrival time -0.027 - ------------------------------------------------------------------- - slack 17.095 - -Slack (MET) : 17.100ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.301ns (logic 1.343ns (58.359%) route 0.958ns (41.641%)) - Logic Levels: 0 - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.172 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.958 -0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.282 16.887 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 16.887 - arrival time 0.213 - ------------------------------------------------------------------- - slack 17.100 - -Slack (MET) : 17.150ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.212ns (logic 1.336ns (60.403%) route 0.876ns (39.597%)) - Logic Levels: 0 - Clock Path Skew: -0.204ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.187 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 0.876 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X62Y81 FDRE (Setup_fdre_C_D) -0.238 16.839 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22] - ------------------------------------------------------------------- - required time 16.839 - arrival time 0.311 - ------------------------------------------------------------------- - slack 17.150 - -Slack (MET) : 17.198ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.407ns (logic 1.314ns (54.587%) route 1.093ns (45.413%)) - Logic Levels: 0 - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.201 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 1.093 -0.107 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.081 17.090 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11] - ------------------------------------------------------------------- - required time 17.090 - arrival time 0.107 - ------------------------------------------------------------------- - slack 17.198 - -Slack (MET) : 17.220ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.336ns (logic 1.317ns (56.385%) route 1.019ns (43.615%)) - Logic Levels: 0 - Clock Path Skew: -0.205ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 1.019 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.043 17.036 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27] - ------------------------------------------------------------------- - required time 17.036 - arrival time 0.184 - ------------------------------------------------------------------- - slack 17.220 - -Slack (MET) : 17.264ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.241ns (logic 1.314ns (58.629%) route 0.927ns (41.371%)) - Logic Levels: 0 - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.927 -0.279 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.093 16.984 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17] - ------------------------------------------------------------------- - required time 16.984 - arrival time 0.279 - ------------------------------------------------------------------- - slack 17.264 - -Slack (MET) : 17.264ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.063ns (logic 1.336ns (64.747%) route 0.727ns (35.253%)) - Logic Levels: 0 - Clock Path Skew: -0.207ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.184 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 0.727 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.269 16.808 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28] - ------------------------------------------------------------------- - required time 16.808 - arrival time 0.456 - ------------------------------------------------------------------- - slack 17.264 - -Slack (MET) : 17.267ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.053ns (logic 1.336ns (65.060%) route 0.717ns (34.940%)) - Logic Levels: 0 - Clock Path Skew: -0.218ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK - SLICE_X22Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y72 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.078 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 0.717 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] - SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.798 17.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C - clock pessimism -0.601 17.369 - clock uncertainty -0.197 17.172 - SLICE_X28Y72 FDRE (Setup_fdre_C_D) -0.265 16.907 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 16.907 - arrival time 0.360 - ------------------------------------------------------------------- - slack 17.267 - -Slack (MET) : 17.269ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.055ns (logic 1.336ns (65.010%) route 0.719ns (34.990%)) - Logic Levels: 0 - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 0.719 -0.466 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.274 16.803 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16] - ------------------------------------------------------------------- - required time 16.803 - arrival time 0.466 - ------------------------------------------------------------------- - slack 17.269 - -Slack (MET) : 17.276ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.013ns (logic 1.343ns (66.730%) route 0.670ns (33.270%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.022ns = ( 17.978 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.071 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O - net (fo=1, routed) 0.670 -0.401 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 17.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C - clock pessimism -0.601 17.377 - clock uncertainty -0.197 17.180 - SLICE_X19Y76 FDRE (Setup_fdre_C_D) -0.305 16.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32] - ------------------------------------------------------------------- - required time 16.875 - arrival time 0.401 - ------------------------------------------------------------------- - slack 17.276 - -Slack (MET) : 17.295ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.030ns (logic 0.419ns (20.636%) route 1.611ns (79.364%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) - Source Clock Delay (SCD): -2.400ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.419 -1.981 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=5, routed) 1.611 -0.369 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism -0.601 17.388 - clock uncertainty -0.197 17.191 - SLICE_X15Y87 FDCE (Setup_fdce_C_D) -0.265 16.926 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 16.926 - arrival time 0.369 - ------------------------------------------------------------------- - slack 17.295 - -Slack (MET) : 17.298ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.211ns (logic 1.309ns (59.215%) route 0.902ns (40.785%)) - Logic Levels: 0 - Clock Path Skew: -0.202ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 0.902 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.093 16.986 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19] - ------------------------------------------------------------------- - required time 16.986 - arrival time 0.312 - ------------------------------------------------------------------- - slack 17.298 - -Slack (MET) : 17.298ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.200ns (logic 0.456ns (20.732%) route 1.744ns (79.268%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.027ns = ( 17.973 - 20.000 ) - Source Clock Delay (SCD): -2.416ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.926 -2.416 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y79 FDCE (Prop_fdce_C_Q) 0.456 -1.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 1.744 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.801 17.973 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.372 - clock uncertainty -0.197 17.175 - SLICE_X27Y78 FDCE (Setup_fdce_C_D) -0.093 17.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 17.082 - arrival time 0.216 - ------------------------------------------------------------------- - slack 17.298 - -Slack (MET) : 17.351ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.004ns (logic 0.419ns (20.911%) route 1.585ns (79.089%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) - Source Clock Delay (SCD): -2.419ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.923 -2.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.419 -2.000 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 1.585 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.798 17.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.369 - clock uncertainty -0.197 17.172 - SLICE_X26Y73 FDCE (Setup_fdce_C_D) -0.236 16.936 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 16.936 - arrival time 0.415 - ------------------------------------------------------------------- - slack 17.351 - -Slack (MET) : 17.368ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.159ns (logic 1.309ns (60.638%) route 0.850ns (39.362%)) - Logic Levels: 0 - Clock Path Skew: -0.219ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 0.850 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.058 17.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31] - ------------------------------------------------------------------- - required time 17.113 - arrival time 0.255 - ------------------------------------------------------------------- - slack 17.368 - -Slack (MET) : 17.377ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.108ns (logic 0.456ns (21.629%) route 1.652ns (78.371%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) - Source Clock Delay (SCD): -2.400ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.456 -1.944 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=3, routed) 1.652 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.388 - clock uncertainty -0.197 17.191 - SLICE_X15Y87 FDCE (Setup_fdce_C_D) -0.105 17.086 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 17.086 - arrival time 0.291 - ------------------------------------------------------------------- - slack 17.377 - -Slack (MET) : 17.380ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.944ns (logic 0.419ns (21.557%) route 1.525ns (78.443%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 17.891 - 20.000 ) - Source Clock Delay (SCD): -2.501ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.841 -2.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.419 -2.082 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 1.525 -0.557 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.719 17.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.290 - clock uncertainty -0.197 17.093 - SLICE_X114Y76 FDCE (Setup_fdce_C_D) -0.270 16.823 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 16.823 - arrival time 0.557 - ------------------------------------------------------------------- - slack 17.380 - -Slack (MET) : 17.388ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.108ns (logic 0.456ns (21.629%) route 1.652ns (78.371%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.027ns = ( 17.973 - 20.000 ) - Source Clock Delay (SCD): -2.417ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.925 -2.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y78 FDCE (Prop_fdce_C_Q) 0.456 -1.961 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 1.652 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.801 17.973 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.601 17.372 - clock uncertainty -0.197 17.175 - SLICE_X27Y78 FDCE (Setup_fdce_C_D) -0.095 17.080 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 17.080 - arrival time 0.308 - ------------------------------------------------------------------- - slack 17.388 - -Slack (MET) : 17.399ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.106ns (logic 0.518ns (24.592%) route 1.588ns (75.408%)) - Logic Levels: 0 - Clock Path Skew: -0.203ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.096ns = ( 17.904 - 20.000 ) - Source Clock Delay (SCD): -2.495ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X112Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X112Y71 FDCE (Prop_fdce_C_Q) 0.518 -1.977 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q - net (fo=2, routed) 1.588 -0.388 u_fft_mlkem_axi_slave/mlkem_intr_m - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.732 17.904 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - clock pessimism -0.601 17.303 - clock uncertainty -0.197 17.106 - SLICE_X117Y61 FDCE (Setup_fdce_C_D) -0.095 17.011 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0] - ------------------------------------------------------------------- - required time 17.011 - arrival time 0.388 - ------------------------------------------------------------------- - slack 17.399 - -Slack (MET) : 17.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.095ns (logic 0.456ns (21.761%) route 1.639ns (78.239%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.425ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.917 -2.425 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X33Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y74 FDCE (Prop_fdce_C_Q) 0.456 -1.969 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 1.639 -0.329 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] - SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X30Y74 FDCE (Setup_fdce_C_D) -0.095 17.074 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 17.074 - arrival time 0.329 - ------------------------------------------------------------------- - slack 17.403 - -Slack (MET) : 17.408ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.088ns (logic 0.456ns (21.835%) route 1.632ns (78.165%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns = ( 17.990 - 20.000 ) - Source Clock Delay (SCD): -2.400ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.456 -1.944 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 1.632 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 17.990 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.601 17.389 - clock uncertainty -0.197 17.192 - SLICE_X15Y88 FDCE (Setup_fdce_C_D) -0.095 17.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 17.097 - arrival time 0.311 - ------------------------------------------------------------------- - slack 17.408 - -Slack (MET) : 17.411ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.087ns (logic 0.456ns (21.845%) route 1.631ns (78.155%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns = ( 17.990 - 20.000 ) - Source Clock Delay (SCD): -2.400ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.456 -1.944 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 1.631 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 17.990 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.601 17.389 - clock uncertainty -0.197 17.192 - SLICE_X15Y88 FDCE (Setup_fdce_C_D) -0.093 17.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 17.099 - arrival time 0.312 - ------------------------------------------------------------------- - slack 17.411 - -Slack (MET) : 17.415ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.084ns (logic 0.456ns (21.879%) route 1.628ns (78.121%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.423ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.919 -2.423 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X31Y74 FDCE (Prop_fdce_C_Q) 0.456 -1.967 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 1.628 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X29Y74 FDCE (Setup_fdce_C_D) -0.093 17.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 17.076 - arrival time 0.338 - ------------------------------------------------------------------- - slack 17.415 - -Slack (MET) : 17.422ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.877ns (logic 1.344ns (71.587%) route 0.533ns (28.413%)) - Logic Levels: 0 - Clock Path Skew: -0.207ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.176 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 0.533 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.297 16.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24] - ------------------------------------------------------------------- - required time 16.780 - arrival time 0.642 - ------------------------------------------------------------------- - slack 17.422 - -Slack (MET) : 17.426ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.860ns (logic 1.343ns (72.194%) route 0.517ns (27.806%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) - Source Clock Delay (SCD): -2.409ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.066 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.517 -0.548 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C - clock pessimism -0.601 17.380 - clock uncertainty -0.197 17.183 - SLICE_X17Y78 FDRE (Setup_fdre_C_D) -0.305 16.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 16.878 - arrival time 0.548 - ------------------------------------------------------------------- - slack 17.426 - -Slack (MET) : 17.461ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.860ns (logic 1.344ns (72.269%) route 0.516ns (27.731%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) - Source Clock Delay (SCD): -2.409ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.065 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O - net (fo=1, routed) 0.516 -0.549 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C - clock pessimism -0.601 17.380 - clock uncertainty -0.197 17.183 - SLICE_X17Y78 FDRE (Setup_fdre_C_D) -0.271 16.912 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 16.912 - arrival time 0.549 - ------------------------------------------------------------------- - slack 17.461 - -Slack (MET) : 17.463ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.069ns (logic 1.317ns (63.642%) route 0.752ns (36.358%)) - Logic Levels: 0 - Clock Path Skew: -0.204ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.204 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.752 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.067 17.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 17.012 - arrival time 0.451 - ------------------------------------------------------------------- - slack 17.463 - -Slack (MET) : 17.464ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.079ns (logic 1.317ns (63.334%) route 0.762ns (36.666%)) - Logic Levels: 0 - Clock Path Skew: -0.202ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.762 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.058 17.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 17.021 - arrival time 0.443 - ------------------------------------------------------------------- - slack 17.464 - -Slack (MET) : 17.494ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.834ns (logic 1.336ns (72.831%) route 0.498ns (27.169%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.022ns = ( 17.978 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.078 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.498 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 17.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C - clock pessimism -0.601 17.377 - clock uncertainty -0.197 17.180 - SLICE_X19Y76 FDRE (Setup_fdre_C_D) -0.265 16.915 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 16.915 - arrival time 0.579 - ------------------------------------------------------------------- - slack 17.494 - -Slack (MET) : 17.513ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.042ns (logic 1.314ns (64.342%) route 0.728ns (35.658%)) - Logic Levels: 0 - Clock Path Skew: -0.204ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.728 -0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X62Y81 FDRE (Setup_fdre_C_D) -0.045 17.032 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 17.032 - arrival time 0.480 - ------------------------------------------------------------------- - slack 17.513 - -Slack (MET) : 17.526ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.999ns (logic 1.309ns (65.487%) route 0.690ns (34.513%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) - Source Clock Delay (SCD): -2.409ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.100 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.690 -0.410 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C - clock pessimism -0.601 17.380 - clock uncertainty -0.197 17.183 - SLICE_X15Y78 FDRE (Setup_fdre_C_D) -0.067 17.116 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time 17.116 - arrival time 0.410 - ------------------------------------------------------------------- - slack 17.526 - -Slack (MET) : 17.534ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.826ns (logic 1.344ns (73.607%) route 0.482ns (26.393%)) - Logic Levels: 0 - Clock Path Skew: -0.209ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.130ns = ( 17.870 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.179 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 0.482 -0.697 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] - SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.698 17.870 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C - clock pessimism -0.601 17.269 - clock uncertainty -0.197 17.072 - SLICE_X62Y76 FDRE (Setup_fdre_C_D) -0.235 16.837 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18] - ------------------------------------------------------------------- - required time 16.837 - arrival time 0.697 - ------------------------------------------------------------------- - slack 17.534 - - +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA_D1/CLK @@ -20577,1650 +15082,30 @@ Path Group: **async_default** From Clock: cpu_clk To Clock: cpu_clk -Setup : 0 Failing Endpoints, Worst Slack 25.793ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 26.018ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.837ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.361 27.371 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] - ------------------------------------------------------------------- - required time 27.371 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.837 - -Slack (MET) : 25.837ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.361 27.371 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] - ------------------------------------------------------------------- - required time 27.371 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.837 - -Slack (MET) : 25.879ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.319 27.413 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] - ------------------------------------------------------------------- - required time 27.413 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.879 - -Slack (MET) : 25.879ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.319 27.413 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] - ------------------------------------------------------------------- - required time 27.413 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.879 - -Slack (MET) : 25.879ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.319 27.413 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] - ------------------------------------------------------------------- - required time 27.413 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.879 - -Slack (MET) : 25.990ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.361 27.372 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 27.372 - arrival time -1.382 - ------------------------------------------------------------------- - slack 25.990 - -Slack (MET) : 25.990ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.361 27.372 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 27.372 - arrival time -1.382 - ------------------------------------------------------------------- - slack 25.990 - -Slack (MET) : 25.990ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.361 27.372 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 27.372 - arrival time -1.382 - ------------------------------------------------------------------- - slack 25.990 - -Slack (MET) : 25.995ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] - ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 - ------------------------------------------------------------------- - slack 25.995 - -Slack (MET) : 25.995ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] - ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 - ------------------------------------------------------------------- - slack 25.995 - -Slack (MET) : 25.995ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] - ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 - ------------------------------------------------------------------- - slack 25.995 - -Slack (MET) : 25.995ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] - ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 - ------------------------------------------------------------------- - slack 25.995 - -Slack (MET) : 25.995ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] - ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 - ------------------------------------------------------------------- - slack 25.995 - -Slack (MET) : 26.032ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.319 27.414 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 27.414 - arrival time -1.382 - ------------------------------------------------------------------- - slack 26.032 - -Slack (MET) : 26.032ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.319 27.414 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 27.414 - arrival time -1.382 - ------------------------------------------------------------------- - slack 26.032 - -Slack (MET) : 26.032ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.319 27.414 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 27.414 - arrival time -1.382 - ------------------------------------------------------------------- - slack 26.032 - -Slack (MET) : 26.072ns (required time - arrival time) +Slack (MET) : 26.018ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.804ns (logic 0.718ns (18.873%) route 3.086ns (81.127%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.455 1.401 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X4Y76 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/cpu_clk - SLICE_X4Y76 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X4Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.401 - ------------------------------------------------------------------- - slack 26.072 - -Slack (MET) : 26.072ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.804ns (logic 0.718ns (18.873%) route 3.086ns (81.127%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.455 1.401 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X4Y76 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/cpu_clk - SLICE_X4Y76 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X4Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.401 - ------------------------------------------------------------------- - slack 26.072 - -Slack (MET) : 26.072ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.804ns (logic 0.718ns (18.873%) route 3.086ns (81.127%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.455 1.401 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X4Y76 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/cpu_clk - SLICE_X4Y76 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X4Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.401 - ------------------------------------------------------------------- - slack 26.072 - -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 - ------------------------------------------------------------------- - slack 26.076 - -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 - ------------------------------------------------------------------- - slack 26.076 - -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22234,473 +15119,53 @@ Slack (MET) : 26.076ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 + required time 26.696 + arrival time -0.678 ------------------------------------------------------------------- - slack 26.076 + slack 26.018 -Slack (MET) : 26.076ns (required time - arrival time) +Slack (MET) : 26.018ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 - ------------------------------------------------------------------- - slack 26.076 - -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 - ------------------------------------------------------------------- - slack 26.076 - -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 - ------------------------------------------------------------------- - slack 26.076 - -Slack (MET) : 26.198ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 27.471 - arrival time -1.273 - ------------------------------------------------------------------- - slack 26.198 - -Slack (MET) : 26.198ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 27.471 - arrival time -1.273 - ------------------------------------------------------------------- - slack 26.198 - -Slack (MET) : 26.198ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 27.471 - arrival time -1.273 - ------------------------------------------------------------------- - slack 26.198 - -Slack (MET) : 26.198ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] - ------------------------------------------------------------------- - required time 27.471 - arrival time -1.273 - ------------------------------------------------------------------- - slack 26.198 - -Slack (MET) : 26.255ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.620ns (logic 0.718ns (19.836%) route 2.902ns (80.164%)) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22714,53 +15179,113 @@ Slack (MET) : 26.255ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.270 1.216 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y75 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- - required time 27.471 - arrival time -1.216 + required time 26.696 + arrival time -0.678 ------------------------------------------------------------------- - slack 26.255 + slack 26.018 -Slack (MET) : 26.255ns (required time - arrival time) +Slack (MET) : 26.018ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 26.696 + arrival time -0.678 + ------------------------------------------------------------------- + slack 26.018 + +Slack (MET) : 26.018ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.620ns (logic 0.718ns (19.836%) route 2.902ns (80.164%)) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22774,53 +15299,53 @@ Slack (MET) : 26.255ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.270 1.216 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y75 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- - required time 27.471 - arrival time -1.216 + required time 26.696 + arrival time -0.678 ------------------------------------------------------------------- - slack 26.255 + slack 26.018 -Slack (MET) : 26.639ns (required time - arrival time) +Slack (MET) : 26.062ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.322ns (logic 0.718ns (21.614%) route 2.604ns (78.386%)) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22834,53 +15359,53 @@ Slack (MET) : 26.639ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.972 0.918 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X6Y74 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X6Y74 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X6Y74 FDCE (Recov_fdce_C_CLR) -0.319 27.557 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.361 26.740 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- - required time 27.557 - arrival time -0.918 + required time 26.740 + arrival time -0.678 ------------------------------------------------------------------- - slack 26.639 + slack 26.062 -Slack (MET) : 27.242ns (required time - arrival time) +Slack (MET) : 26.062ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22894,53 +15419,53 @@ Slack (MET) : 27.242ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.361 26.740 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 + required time 26.740 + arrival time -0.678 ------------------------------------------------------------------- - slack 27.242 + slack 26.062 -Slack (MET) : 27.242ns (required time - arrival time) +Slack (MET) : 26.104ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22954,53 +15479,53 @@ Slack (MET) : 27.242ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.782 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 + required time 26.782 + arrival time -0.678 ------------------------------------------------------------------- - slack 27.242 + slack 26.104 -Slack (MET) : 27.242ns (required time - arrival time) +Slack (MET) : 26.104ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23014,533 +15539,53 @@ Slack (MET) : 27.242ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.507 27.214 + clock uncertainty -0.113 27.101 + SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.782 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 + required time 26.782 + arrival time -0.678 ------------------------------------------------------------------- - slack 27.242 + slack 26.104 -Slack (MET) : 27.242ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 - ------------------------------------------------------------------- - slack 27.242 - -Slack (MET) : 27.242ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 - ------------------------------------------------------------------- - slack 27.242 - -Slack (MET) : 27.242ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 - ------------------------------------------------------------------- - slack 27.242 - -Slack (MET) : 27.242ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X19Y59 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 - ------------------------------------------------------------------- - slack 27.242 - -Slack (MET) : 27.248ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.426 27.888 - clock uncertainty -0.074 27.814 - SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 27.409 - arrival time -0.161 - ------------------------------------------------------------------- - slack 27.248 - -Slack (MET) : 27.248ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.426 27.888 - clock uncertainty -0.074 27.814 - SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 27.409 - arrival time -0.161 - ------------------------------------------------------------------- - slack 27.248 - -Slack (MET) : 27.248ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.426 27.888 - clock uncertainty -0.074 27.814 - SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 27.409 - arrival time -0.161 - ------------------------------------------------------------------- - slack 27.248 - -Slack (MET) : 27.248ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.426 27.888 - clock uncertainty -0.074 27.814 - SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 27.409 - arrival time -0.161 - ------------------------------------------------------------------- - slack 27.248 - -Slack (MET) : 27.338ns (required time - arrival time) +Slack (MET) : 26.156ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.252ns (logic 0.580ns (25.756%) route 1.672ns (74.244%)) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.270ns (logic 0.642ns (19.635%) route 2.628ns (80.365%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.298ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.928ns = ( 28.394 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.056ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.299ns = ( 27.701 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23554,35 +15599,2495 @@ Slack (MET) : 27.338ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.014 0.123 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.986 0.592 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y127 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.900 28.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.498 27.896 - clock uncertainty -0.074 27.822 - SLICE_X6Y50 FDCE (Recov_fdce_C_CLR) -0.361 27.461 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.529 27.701 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y127 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.435 27.266 + clock uncertainty -0.113 27.153 + SLICE_X89Y127 FDCE (Recov_fdce_C_CLR) -0.405 26.748 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- - required time 27.461 - arrival time -0.123 + required time 26.748 + arrival time -0.592 ------------------------------------------------------------------- - slack 27.338 + slack 26.156 + +Slack (MET) : 26.156ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.270ns (logic 0.642ns (19.635%) route 2.628ns (80.365%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.056ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.299ns = ( 27.701 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.986 0.592 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y127 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.529 27.701 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y127 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C + clock pessimism -0.435 27.266 + clock uncertainty -0.113 27.153 + SLICE_X89Y127 FDCE (Recov_fdce_C_CLR) -0.405 26.748 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] + ------------------------------------------------------------------- + required time 26.748 + arrival time -0.592 + ------------------------------------------------------------------- + slack 26.156 + +Slack (MET) : 26.290ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.110ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.507 27.212 + clock uncertainty -0.113 27.099 + SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.361 26.738 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 26.738 + arrival time -0.448 + ------------------------------------------------------------------- + slack 26.290 + +Slack (MET) : 26.332ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.110ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.507 27.212 + clock uncertainty -0.113 27.099 + SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.319 26.780 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 26.780 + arrival time -0.448 + ------------------------------------------------------------------- + slack 26.332 + +Slack (MET) : 26.332ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.110ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.507 27.212 + clock uncertainty -0.113 27.099 + SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.319 26.780 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 26.780 + arrival time -0.448 + ------------------------------------------------------------------- + slack 26.332 + +Slack (MET) : 26.332ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.110ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C + clock pessimism -0.507 27.212 + clock uncertainty -0.113 27.099 + SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.319 26.780 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 26.780 + arrival time -0.448 + ------------------------------------------------------------------- + slack 26.332 + +Slack (MET) : 26.351ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.109ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.507 27.213 + clock uncertainty -0.113 27.100 + SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.361 26.739 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 26.739 + arrival time -0.388 + ------------------------------------------------------------------- + slack 26.351 + +Slack (MET) : 26.393ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.109ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.507 27.213 + clock uncertainty -0.113 27.100 + SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.781 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 26.781 + arrival time -0.388 + ------------------------------------------------------------------- + slack 26.393 + +Slack (MET) : 26.393ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.109ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.507 27.213 + clock uncertainty -0.113 27.100 + SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.781 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 26.781 + arrival time -0.388 + ------------------------------------------------------------------- + slack 26.393 + +Slack (MET) : 26.393ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.109ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C + clock pessimism -0.507 27.213 + clock uncertainty -0.113 27.100 + SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.781 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] + ------------------------------------------------------------------- + required time 26.781 + arrival time -0.388 + ------------------------------------------------------------------- + slack 26.393 + +Slack (MET) : 26.825ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.077 + ------------------------------------------------------------------- + slack 26.825 + +Slack (MET) : 26.825ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.077 + ------------------------------------------------------------------- + slack 26.825 + +Slack (MET) : 26.825ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.077 + ------------------------------------------------------------------- + slack 26.825 + +Slack (MET) : 26.825ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.077 + ------------------------------------------------------------------- + slack 26.825 + +Slack (MET) : 26.825ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.077 + ------------------------------------------------------------------- + slack 26.825 + +Slack (MET) : 26.825ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.077 + ------------------------------------------------------------------- + slack 26.825 + +Slack (MET) : 26.890ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.532ns (logic 0.642ns (25.351%) route 1.890ns (74.649%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.059ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 27.698 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.249 -0.145 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 27.698 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.435 27.263 + clock uncertainty -0.113 27.150 + SLICE_X89Y125 FDCE (Recov_fdce_C_CLR) -0.405 26.745 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] + ------------------------------------------------------------------- + required time 26.745 + arrival time 0.145 + ------------------------------------------------------------------- + slack 26.890 + +Slack (MET) : 26.890ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.532ns (logic 0.642ns (25.351%) route 1.890ns (74.649%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.059ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 27.698 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.249 -0.145 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 27.698 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.435 27.263 + clock uncertainty -0.113 27.150 + SLICE_X89Y125 FDCE (Recov_fdce_C_CLR) -0.405 26.745 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] + ------------------------------------------------------------------- + required time 26.745 + arrival time 0.145 + ------------------------------------------------------------------- + slack 26.890 + +Slack (MET) : 26.890ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.532ns (logic 0.642ns (25.351%) route 1.890ns (74.649%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.059ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 27.698 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.249 -0.145 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 27.698 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + clock pessimism -0.435 27.263 + clock uncertainty -0.113 27.150 + SLICE_X89Y125 FDCE (Recov_fdce_C_CLR) -0.405 26.745 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] + ------------------------------------------------------------------- + required time 26.745 + arrival time 0.145 + ------------------------------------------------------------------- + slack 26.890 + +Slack (MET) : 26.890ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.532ns (logic 0.642ns (25.351%) route 1.890ns (74.649%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.059ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 27.698 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.249 -0.145 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 27.698 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.435 27.263 + clock uncertainty -0.113 27.150 + SLICE_X89Y125 FDCE (Recov_fdce_C_CLR) -0.405 26.745 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] + ------------------------------------------------------------------- + required time 26.745 + arrival time 0.145 + ------------------------------------------------------------------- + slack 26.890 + +Slack (MET) : 26.890ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.532ns (logic 0.642ns (25.351%) route 1.890ns (74.649%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.059ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 27.698 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.249 -0.145 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 27.698 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.435 27.263 + clock uncertainty -0.113 27.150 + SLICE_X89Y125 FDCE (Recov_fdce_C_CLR) -0.405 26.745 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] + ------------------------------------------------------------------- + required time 26.745 + arrival time 0.145 + ------------------------------------------------------------------- + slack 26.890 + +Slack (MET) : 26.954ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X91Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.435 27.269 + clock uncertainty -0.113 27.156 + SLICE_X91Y126 FDCE (Recov_fdce_C_CLR) -0.405 26.751 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 26.751 + arrival time 0.203 + ------------------------------------------------------------------- + slack 26.954 + +Slack (MET) : 26.954ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X91Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.435 27.269 + clock uncertainty -0.113 27.156 + SLICE_X91Y126 FDCE (Recov_fdce_C_CLR) -0.405 26.751 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 26.751 + arrival time 0.203 + ------------------------------------------------------------------- + slack 26.954 + +Slack (MET) : 26.973ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.454ns (logic 0.642ns (26.165%) route 1.812ns (73.835%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.170 -0.224 u_Axi_CDC/arFifo/p_0_in + SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y105 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.224 + ------------------------------------------------------------------- + slack 26.973 + +Slack (MET) : 26.973ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.454ns (logic 0.642ns (26.165%) route 1.812ns (73.835%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.170 -0.224 u_Axi_CDC/arFifo/p_0_in + SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y105 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.224 + ------------------------------------------------------------------- + slack 26.973 + +Slack (MET) : 26.973ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.454ns (logic 0.642ns (26.165%) route 1.812ns (73.835%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.170 -0.224 u_Axi_CDC/arFifo/p_0_in + SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y105 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.224 + ------------------------------------------------------------------- + slack 26.973 + +Slack (MET) : 26.973ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.454ns (logic 0.642ns (26.165%) route 1.812ns (73.835%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.170 -0.224 u_Axi_CDC/arFifo/p_0_in + SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y105 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.224 + ------------------------------------------------------------------- + slack 26.973 + +Slack (MET) : 26.973ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.454ns (logic 0.642ns (26.165%) route 1.812ns (73.835%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.170 -0.224 u_Axi_CDC/arFifo/p_0_in + SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.435 27.267 + clock uncertainty -0.113 27.154 + SLICE_X86Y105 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] + ------------------------------------------------------------------- + required time 26.749 + arrival time 0.224 + ------------------------------------------------------------------- + slack 26.973 + +Slack (MET) : 26.998ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.435 27.269 + clock uncertainty -0.113 27.156 + SLICE_X90Y126 FDCE (Recov_fdce_C_CLR) -0.361 26.795 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 26.795 + arrival time 0.203 + ------------------------------------------------------------------- + slack 26.998 + +Slack (MET) : 26.998ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.435 27.269 + clock uncertainty -0.113 27.156 + SLICE_X90Y126 FDCE (Recov_fdce_C_CLR) -0.361 26.795 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 26.795 + arrival time 0.203 + ------------------------------------------------------------------- + slack 26.998 + +Slack (MET) : 26.998ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.435 27.269 + clock uncertainty -0.113 27.156 + SLICE_X90Y126 FDCE (Recov_fdce_C_CLR) -0.361 26.795 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 26.795 + arrival time 0.203 + ------------------------------------------------------------------- + slack 26.998 + +Slack (MET) : 27.040ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.435 27.269 + clock uncertainty -0.113 27.156 + SLICE_X90Y126 FDCE (Recov_fdce_C_CLR) -0.319 26.837 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 26.837 + arrival time 0.203 + ------------------------------------------------------------------- + slack 27.040 + +Slack (MET) : 27.040ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.435 27.269 + clock uncertainty -0.113 27.156 + SLICE_X90Y126 FDCE (Recov_fdce_C_CLR) -0.319 26.837 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 26.837 + arrival time 0.203 + ------------------------------------------------------------------- + slack 27.040 + +Slack (MET) : 27.040ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.475ns (logic 0.642ns (25.943%) route 1.833ns (74.057%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.296ns = ( 27.704 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.191 -0.203 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.532 27.704 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.435 27.269 + clock uncertainty -0.113 27.156 + SLICE_X90Y126 FDCE (Recov_fdce_C_CLR) -0.319 26.837 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 26.837 + arrival time 0.203 + ------------------------------------------------------------------- + slack 27.040 + +Slack (MET) : 27.372ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.132ns (logic 0.642ns (30.109%) route 1.490ns (69.891%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.849 -0.545 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.418 27.301 + clock uncertainty -0.113 27.188 + SLICE_X92Y111 FDCE (Recov_fdce_C_CLR) -0.361 26.827 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 26.827 + arrival time 0.545 + ------------------------------------------------------------------- + slack 27.372 + +Slack (MET) : 27.372ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.132ns (logic 0.642ns (30.109%) route 1.490ns (69.891%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.849 -0.545 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.418 27.301 + clock uncertainty -0.113 27.188 + SLICE_X92Y111 FDCE (Recov_fdce_C_CLR) -0.361 26.827 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 26.827 + arrival time 0.545 + ------------------------------------------------------------------- + slack 27.372 + +Slack (MET) : 27.372ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.132ns (logic 0.642ns (30.109%) route 1.490ns (69.891%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.849 -0.545 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.418 27.301 + clock uncertainty -0.113 27.188 + SLICE_X92Y111 FDCE (Recov_fdce_C_CLR) -0.361 26.827 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 26.827 + arrival time 0.545 + ------------------------------------------------------------------- + slack 27.372 + +Slack (MET) : 27.414ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.132ns (logic 0.642ns (30.109%) route 1.490ns (69.891%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.849 -0.545 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.418 27.301 + clock uncertainty -0.113 27.188 + SLICE_X92Y111 FDCE (Recov_fdce_C_CLR) -0.319 26.869 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 26.869 + arrival time 0.545 + ------------------------------------------------------------------- + slack 27.414 + +Slack (MET) : 27.414ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.132ns (logic 0.642ns (30.109%) route 1.490ns (69.891%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.849 -0.545 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.418 27.301 + clock uncertainty -0.113 27.188 + SLICE_X92Y111 FDCE (Recov_fdce_C_CLR) -0.319 26.869 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 26.869 + arrival time 0.545 + ------------------------------------------------------------------- + slack 27.414 + +Slack (MET) : 27.414ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.132ns (logic 0.642ns (30.109%) route 1.490ns (69.891%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.021ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.849 -0.545 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.418 27.301 + clock uncertainty -0.113 27.188 + SLICE_X92Y111 FDCE (Recov_fdce_C_CLR) -0.319 26.869 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 26.869 + arrival time 0.545 + ------------------------------------------------------------------- + slack 27.414 + +Slack (MET) : 27.482ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.976ns (logic 0.642ns (32.486%) route 1.334ns (67.514%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.023ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.283ns = ( 27.717 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.693 -0.701 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.545 27.717 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.418 27.299 + clock uncertainty -0.113 27.186 + SLICE_X93Y113 FDCE (Recov_fdce_C_CLR) -0.405 26.781 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] + ------------------------------------------------------------------- + required time 26.781 + arrival time 0.701 + ------------------------------------------------------------------- + slack 27.482 + +Slack (MET) : 27.482ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.976ns (logic 0.642ns (32.486%) route 1.334ns (67.514%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.023ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.283ns = ( 27.717 - 30.000 ) + Source Clock Delay (SCD): -2.678ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.693 -0.701 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.000 30.000 r + K21 0.000 30.000 r clk (IN) + net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.545 27.717 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.418 27.299 + clock uncertainty -0.113 27.186 + SLICE_X93Y113 FDCE (Recov_fdce_C_CLR) -0.405 26.781 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] + ------------------------------------------------------------------- + required time 26.781 + arrival time 0.701 + ------------------------------------------------------------------- + slack 27.482 @@ -23590,38 +18095,38 @@ Slack (MET) : 27.338ns (required time - arrival time) --------------------------------------------------------------------------------------------------- Path Group: **async_default** -From Clock: mlkem_clk_clk_pll - To Clock: mlkem_clk_clk_pll +From Clock: mlkem_clk + To Clock: mlkem_clk -Setup : 0 Failing Endpoints, Worst Slack 23.497ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 3.826ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 23.497ns (required time - arrival time) +Slack (MET) : 3.826ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.612ns (logic 0.609ns (3.901%) route 15.003ns (96.099%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.188ns = ( 37.812 - 40.000 ) - Source Clock Delay (SCD): -2.489ns + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.817ns (logic 0.642ns (7.282%) route 8.175ns (92.718%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -23631,59 +18136,59 @@ Slack (MET) : 23.497ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.752 13.124 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X41Y101 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324]/CLR + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.745 6.147 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X96Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.640 37.812 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X41Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324]/C - clock pessimism -0.507 37.305 - clock uncertainty -0.077 37.229 - SLICE_X41Y101 FDCE (Recov_fdce_C_CLR) -0.608 36.621 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.720 10.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X96Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/C + clock pessimism -0.507 10.385 + clock uncertainty -0.093 10.292 + SLICE_X96Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.973 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22] ------------------------------------------------------------------- - required time 36.621 - arrival time -13.124 + required time 9.973 + arrival time -6.147 ------------------------------------------------------------------- - slack 23.497 + slack 3.826 -Slack (MET) : 23.497ns (required time - arrival time) +Slack (MET) : 3.860ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.612ns (logic 0.609ns (3.901%) route 15.003ns (96.099%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.188ns = ( 37.812 - 40.000 ) - Source Clock Delay (SCD): -2.489ns + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.747ns (logic 0.642ns (7.340%) route 8.105ns (92.660%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.061ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.102ns = ( 10.898 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -23693,59 +18198,59 @@ Slack (MET) : 23.497ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.752 13.124 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X41Y101 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931]/CLR + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.675 6.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X104Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.640 37.812 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X41Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931]/C - clock pessimism -0.507 37.305 - clock uncertainty -0.077 37.229 - SLICE_X41Y101 FDCE (Recov_fdce_C_CLR) -0.608 36.621 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.726 10.898 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X104Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/C + clock pessimism -0.507 10.391 + clock uncertainty -0.093 10.298 + SLICE_X104Y85 FDCE (Recov_fdce_C_CLR) -0.361 9.937 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5] ------------------------------------------------------------------- - required time 36.621 - arrival time -13.124 + required time 9.937 + arrival time -6.077 ------------------------------------------------------------------- - slack 23.497 + slack 3.860 -Slack (MET) : 23.954ns (required time - arrival time) +Slack (MET) : 3.902ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.155ns (logic 0.609ns (4.018%) route 14.546ns (95.982%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.188ns = ( 37.812 - 40.000 ) - Source Clock Delay (SCD): -2.489ns + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.747ns (logic 0.642ns (7.340%) route 8.105ns (92.660%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.061ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.102ns = ( 10.898 - 13.000 ) + Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -23755,3249 +18260,59 @@ Slack (MET) : 23.954ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.295 12.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X38Y100 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293]/CLR + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.675 6.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X104Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.640 37.812 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X38Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293]/C - clock pessimism -0.507 37.305 - clock uncertainty -0.077 37.229 - SLICE_X38Y100 FDCE (Recov_fdce_C_CLR) -0.608 36.621 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293] + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.726 10.898 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X104Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/C + clock pessimism -0.507 10.391 + clock uncertainty -0.093 10.298 + SLICE_X104Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26] ------------------------------------------------------------------- - required time 36.621 - arrival time -12.667 + required time 9.979 + arrival time -6.077 ------------------------------------------------------------------- - slack 23.954 + slack 3.902 -Slack (MET) : 24.240ns (required time - arrival time) +Slack (MET) : 4.068ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.267ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.931ns (logic 0.609ns (4.079%) route 14.322ns (95.921%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.071 12.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X45Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X45Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X45Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.442 - ------------------------------------------------------------------- - slack 24.267 - -Slack (MET) : 24.267ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.931ns (logic 0.609ns (4.079%) route 14.322ns (95.921%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.071 12.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X45Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X45Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X45Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.442 - ------------------------------------------------------------------- - slack 24.267 - -Slack (MET) : 24.272ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X49Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X49Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X49Y97 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.272 - -Slack (MET) : 24.272ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X49Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X49Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X49Y97 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.272 - -Slack (MET) : 24.284ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X36Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X36Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X36Y99 FDCE (Recov_fdce_C_CLR) -0.564 36.840 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269] - ------------------------------------------------------------------- - required time 36.840 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.284 - -Slack (MET) : 24.316ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.564 36.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652] - ------------------------------------------------------------------- - required time 36.753 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.316 - -Slack (MET) : 24.316ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.564 36.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715] - ------------------------------------------------------------------- - required time 36.753 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.316 - -Slack (MET) : 24.316ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.564 36.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718] - ------------------------------------------------------------------- - required time 36.753 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.316 - -Slack (MET) : 24.326ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X36Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X36Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X36Y99 FDCE (Recov_fdce_C_CLR) -0.522 36.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268] - ------------------------------------------------------------------- - required time 36.882 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.326 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.358ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.522 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301] - ------------------------------------------------------------------- - required time 36.795 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.358 - -Slack (MET) : 24.358ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.522 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525] - ------------------------------------------------------------------- - required time 36.795 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.358 - -Slack (MET) : 24.358ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.522 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557] - ------------------------------------------------------------------- - required time 36.795 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.358 - -Slack (MET) : 24.441ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X41Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X41Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X41Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.441 - -Slack (MET) : 24.441ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X41Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X41Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X41Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.441 - -Slack (MET) : 24.527ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X40Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X40Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X40Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181] - ------------------------------------------------------------------- - required time 36.879 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.527 - -Slack (MET) : 24.527ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X40Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X40Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X40Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196] - ------------------------------------------------------------------- - required time 36.879 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.527 - -Slack (MET) : 24.527ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X40Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X40Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X40Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197] - ------------------------------------------------------------------- - required time 36.879 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.527 - -Slack (MET) : 24.542ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176] - ------------------------------------------------------------------- - required time 36.708 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.542 - -Slack (MET) : 24.542ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517] - ------------------------------------------------------------------- - required time 36.708 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.542 - -Slack (MET) : 24.542ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570] - ------------------------------------------------------------------- - required time 36.708 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.542 - -Slack (MET) : 24.542ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730] - ------------------------------------------------------------------- - required time 36.708 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.542 - -Slack (MET) : 24.578ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.705ns (logic 0.609ns (4.142%) route 14.096ns (95.858%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.845 12.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X38Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X38Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540]/C - clock pessimism -0.498 37.478 - clock uncertainty -0.077 37.402 - SLICE_X38Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.216 - ------------------------------------------------------------------- - slack 24.578 - -Slack (MET) : 24.578ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.705ns (logic 0.609ns (4.142%) route 14.096ns (95.858%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.845 12.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X38Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X38Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733]/C - clock pessimism -0.498 37.478 - clock uncertainty -0.077 37.402 - SLICE_X38Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.216 - ------------------------------------------------------------------- - slack 24.578 - -Slack (MET) : 24.582ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.700ns (logic 0.609ns (4.143%) route 14.091ns (95.857%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.840 12.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X39Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X39Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053]/C - clock pessimism -0.498 37.478 - clock uncertainty -0.077 37.402 - SLICE_X39Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.212 - ------------------------------------------------------------------- - slack 24.582 - -Slack (MET) : 24.582ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.700ns (logic 0.609ns (4.143%) route 14.091ns (95.857%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.840 12.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X39Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X39Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188]/C - clock pessimism -0.498 37.478 - clock uncertainty -0.077 37.402 - SLICE_X39Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.212 - ------------------------------------------------------------------- - slack 24.582 - -Slack (MET) : 24.628ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X44Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X44Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X44Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.628 - -Slack (MET) : 24.628ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X44Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X44Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X44Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.628 - -Slack (MET) : 24.628ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X44Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X44Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X44Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.628 - -Slack (MET) : 24.654ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.628ns (logic 0.609ns (4.163%) route 14.019ns (95.837%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.768 12.139 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X38Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X38Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X38Y94 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.139 - ------------------------------------------------------------------- - slack 24.654 - -Slack (MET) : 24.658ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.624ns (logic 0.609ns (4.165%) route 14.015ns (95.835%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.764 12.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X39Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X39Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X39Y94 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.135 - ------------------------------------------------------------------- - slack 24.658 - -Slack (MET) : 24.680ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.559ns (logic 0.609ns (4.183%) route 13.950ns (95.817%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.699 12.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X44Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X44Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533]/C - clock pessimism -0.498 37.391 - clock uncertainty -0.077 37.315 - SLICE_X44Y92 FDCE (Recov_fdce_C_CLR) -0.564 36.751 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533] - ------------------------------------------------------------------- - required time 36.751 - arrival time -12.071 - ------------------------------------------------------------------- - slack 24.680 - -Slack (MET) : 24.722ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.559ns (logic 0.609ns (4.183%) route 13.950ns (95.817%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.699 12.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X44Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X44Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532]/C - clock pessimism -0.498 37.391 - clock uncertainty -0.077 37.315 - SLICE_X44Y92 FDCE (Recov_fdce_C_CLR) -0.522 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.071 - ------------------------------------------------------------------- - slack 24.722 - -Slack (MET) : 25.212ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.068ns (logic 0.609ns (4.329%) route 13.459ns (95.671%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.025ns = ( 37.975 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.208 11.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X38Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.803 37.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X38Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204]/C - clock pessimism -0.498 37.476 - clock uncertainty -0.077 37.400 - SLICE_X38Y92 FDCE (Recov_fdce_C_CLR) -0.608 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204] - ------------------------------------------------------------------- - required time 36.792 - arrival time -11.580 - ------------------------------------------------------------------- - slack 25.212 - -Slack (MET) : 25.212ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.068ns (logic 0.609ns (4.329%) route 13.459ns (95.671%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.025ns = ( 37.975 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.208 11.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X38Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.803 37.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X38Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205]/C - clock pessimism -0.498 37.476 - clock uncertainty -0.077 37.400 - SLICE_X38Y92 FDCE (Recov_fdce_C_CLR) -0.608 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205] - ------------------------------------------------------------------- - required time 36.792 - arrival time -11.580 - ------------------------------------------------------------------- - slack 25.212 - -Slack (MET) : 25.217ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.064ns (logic 0.609ns (4.330%) route 13.455ns (95.670%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.025ns = ( 37.975 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.204 11.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X39Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.803 37.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X39Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204]/C - clock pessimism -0.498 37.476 - clock uncertainty -0.077 37.400 - SLICE_X39Y92 FDCE (Recov_fdce_C_CLR) -0.608 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204] - ------------------------------------------------------------------- - required time 36.792 - arrival time -11.575 - ------------------------------------------------------------------- - slack 25.217 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: sys_clk - To Clock: mlkem_clk_clk_pll - -Setup : 0 Failing Endpoints, Worst Slack 9.156ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 9.156ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 9.823ns (logic 0.606ns (6.169%) route 9.217ns (93.831%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.215ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.101ns = ( 37.899 - 40.000 ) - Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.710 27.336 pll_clk.u_rst_mlkem/p_0_in - SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.727 37.899 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C - clock pessimism -0.601 37.298 - clock uncertainty -0.197 37.101 - SLICE_X118Y67 FDCE (Recov_fdce_C_CLR) -0.609 36.492 pll_clk.u_rst_mlkem/delay_reg[0] - ------------------------------------------------------------------- - required time 36.492 - arrival time -27.336 - ------------------------------------------------------------------- - slack 9.156 - -Slack (MET) : 9.156ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 9.823ns (logic 0.606ns (6.169%) route 9.217ns (93.831%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.215ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.101ns = ( 37.899 - 40.000 ) - Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.710 27.336 pll_clk.u_rst_mlkem/p_0_in - SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.727 37.899 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - clock pessimism -0.601 37.298 - clock uncertainty -0.197 37.101 - SLICE_X118Y67 FDCE (Recov_fdce_C_CLR) -0.609 36.492 pll_clk.u_rst_mlkem/delay_reg[1] - ------------------------------------------------------------------- - required time 36.492 - arrival time -27.336 - ------------------------------------------------------------------- - slack 9.156 - -Slack (MET) : 11.865ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 7.189ns (logic 0.606ns (8.429%) route 6.583ns (91.571%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.026ns = ( 37.974 - 40.000 ) - Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 3.076 24.702 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in - SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.802 37.974 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C - clock pessimism -0.601 37.373 - clock uncertainty -0.197 37.176 - SLICE_X25Y79 FDCE (Recov_fdce_C_CLR) -0.609 36.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg - ------------------------------------------------------------------- - required time 36.567 - arrival time -24.702 - ------------------------------------------------------------------- - slack 11.865 - -Slack (MET) : 11.865ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 7.189ns (logic 0.606ns (8.429%) route 6.583ns (91.571%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.026ns = ( 37.974 - 40.000 ) - Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 3.076 24.702 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in - SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.802 37.974 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.601 37.373 - clock uncertainty -0.197 37.176 - SLICE_X25Y79 FDCE (Recov_fdce_C_CLR) -0.609 36.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 36.567 - arrival time -24.702 - ------------------------------------------------------------------- - slack 11.865 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: mlkem_clk_clk_pll - To Clock: sys_clk - -Setup : 0 Failing Endpoints, Worst Slack 11.249ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 11.249ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 8.025ns (logic 0.580ns (7.227%) route 7.445ns (92.773%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.124ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -27007,58 +18322,59 @@ Slack (MET) : 11.249ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.874 -1.158 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.124 -1.034 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 6.571 5.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - clock pessimism -0.601 17.388 - clock uncertainty -0.197 17.191 - SLICE_X13Y87 FDCE (Recov_fdce_C_CLR) -0.405 16.786 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22] ------------------------------------------------------------------- - required time 16.786 - arrival time -5.537 + required time 9.883 + arrival time -5.815 ------------------------------------------------------------------- - slack 11.249 + slack 4.068 -Slack (MET) : 11.249ns (required time - arrival time) +Slack (MET) : 4.068ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 8.025ns (logic 0.580ns (7.227%) route 7.445ns (92.773%)) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.124ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -27068,35 +18384,2826 @@ Slack (MET) : 11.249ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.874 -1.158 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.124 -1.034 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 6.571 5.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.601 17.388 - clock uncertainty -0.197 17.191 - SLICE_X13Y87 FDCE (Recov_fdce_C_CLR) -0.405 16.786 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8] ------------------------------------------------------------------- - required time 16.786 - arrival time -5.537 + required time 9.883 + arrival time -5.815 ------------------------------------------------------------------- - slack 11.249 + slack 4.068 + +Slack (MET) : 4.068ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9] + ------------------------------------------------------------------- + required time 9.883 + arrival time -5.815 + ------------------------------------------------------------------- + slack 4.068 + +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12] + ------------------------------------------------------------------- + required time 9.884 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.115 + +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31] + ------------------------------------------------------------------- + required time 9.884 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.115 + +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3] + ------------------------------------------------------------------- + required time 9.884 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.115 + +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4] + ------------------------------------------------------------------- + required time 9.884 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.115 + +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5] + ------------------------------------------------------------------- + required time 9.884 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.115 + +Slack (MET) : 4.115ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6] + ------------------------------------------------------------------- + required time 9.884 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.115 + +Slack (MET) : 4.154ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X94Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X94Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X94Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6] + ------------------------------------------------------------------- + required time 9.969 + arrival time -5.815 + ------------------------------------------------------------------- + slack 4.154 + +Slack (MET) : 4.154ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X94Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X94Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X94Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8] + ------------------------------------------------------------------- + required time 9.969 + arrival time -5.815 + ------------------------------------------------------------------- + slack 4.154 + +Slack (MET) : 4.159ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X100Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X100Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X100Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.928 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26] + ------------------------------------------------------------------- + required time 9.928 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.159 + +Slack (MET) : 4.201ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X100Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X100Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/C + clock pessimism -0.507 10.382 + clock uncertainty -0.093 10.289 + SLICE_X100Y86 FDCE (Recov_fdce_C_CLR) -0.319 9.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25] + ------------------------------------------------------------------- + required time 9.970 + arrival time -5.769 + ------------------------------------------------------------------- + slack 4.201 + +Slack (MET) : 4.223ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/C + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24] + ------------------------------------------------------------------- + required time 9.886 + arrival time -5.662 + ------------------------------------------------------------------- + slack 4.223 + +Slack (MET) : 4.223ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/C + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27] + ------------------------------------------------------------------- + required time 9.886 + arrival time -5.662 + ------------------------------------------------------------------- + slack 4.223 + +Slack (MET) : 4.223ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/C + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4] + ------------------------------------------------------------------- + required time 9.886 + arrival time -5.662 + ------------------------------------------------------------------- + slack 4.223 + +Slack (MET) : 4.223ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/C + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7] + ------------------------------------------------------------------- + required time 9.886 + arrival time -5.662 + ------------------------------------------------------------------- + slack 4.223 + +Slack (MET) : 4.224ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y98 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][22] + ------------------------------------------------------------------- + required time 9.883 + arrival time -5.659 + ------------------------------------------------------------------- + slack 4.224 + +Slack (MET) : 4.224ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y98 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][6] + ------------------------------------------------------------------- + required time 9.883 + arrival time -5.659 + ------------------------------------------------------------------- + slack 4.224 + +Slack (MET) : 4.224ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X95Y98 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[3][8] + ------------------------------------------------------------------- + required time 9.883 + arrival time -5.659 + ------------------------------------------------------------------- + slack 4.224 + +Slack (MET) : 4.275ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X99Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13]/C + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X99Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][13] + ------------------------------------------------------------------- + required time 9.882 + arrival time -5.607 + ------------------------------------------------------------------- + slack 4.275 + +Slack (MET) : 4.275ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X99Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2]/C + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X99Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][2] + ------------------------------------------------------------------- + required time 9.882 + arrival time -5.607 + ------------------------------------------------------------------- + slack 4.275 + +Slack (MET) : 4.275ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X99Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3]/C + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X99Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[2][3] + ------------------------------------------------------------------- + required time 9.882 + arrival time -5.607 + ------------------------------------------------------------------- + slack 4.275 + +Slack (MET) : 4.305ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.172ns (logic 0.642ns (7.856%) route 7.530ns (92.144%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.025ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 10.723 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.101 5.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X95Y101 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.551 10.723 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/C + clock pessimism -0.418 10.305 + clock uncertainty -0.093 10.212 + SLICE_X95Y101 FDCE (Recov_fdce_C_CLR) -0.405 9.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2] + ------------------------------------------------------------------- + required time 9.807 + arrival time -5.503 + ------------------------------------------------------------------- + slack 4.305 + +Slack (MET) : 4.309ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X102Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24]/C + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][24] + ------------------------------------------------------------------- + required time 9.972 + arrival time -5.662 + ------------------------------------------------------------------- + slack 4.309 + +Slack (MET) : 4.309ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X102Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26]/C + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][26] + ------------------------------------------------------------------- + required time 9.972 + arrival time -5.662 + ------------------------------------------------------------------- + slack 4.309 + +Slack (MET) : 4.309ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X102Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5]/C + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][5] + ------------------------------------------------------------------- + required time 9.972 + arrival time -5.662 + ------------------------------------------------------------------- + slack 4.309 + +Slack (MET) : 4.309ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X102Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X102Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7]/C + clock pessimism -0.507 10.384 + clock uncertainty -0.093 10.291 + SLICE_X102Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.972 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][7] + ------------------------------------------------------------------- + required time 9.972 + arrival time -5.662 + ------------------------------------------------------------------- + slack 4.309 + +Slack (MET) : 4.310ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.329ns (logic 0.642ns (7.708%) route 7.687ns (92.292%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.257 5.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X94Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X94Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6]/C + clock pessimism -0.507 10.381 + clock uncertainty -0.093 10.288 + SLICE_X94Y98 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][6] + ------------------------------------------------------------------- + required time 9.969 + arrival time -5.659 + ------------------------------------------------------------------- + slack 4.310 + +Slack (MET) : 4.319ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X98Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19]/C + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.361 9.926 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][19] + ------------------------------------------------------------------- + required time 9.926 + arrival time -5.607 + ------------------------------------------------------------------- + slack 4.319 + +Slack (MET) : 4.319ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X98Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2]/C + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.361 9.926 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][2] + ------------------------------------------------------------------- + required time 9.926 + arrival time -5.607 + ------------------------------------------------------------------- + slack 4.319 + +Slack (MET) : 4.361ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X98Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12]/C + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.319 9.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][12] + ------------------------------------------------------------------- + required time 9.968 + arrival time -5.607 + ------------------------------------------------------------------- + slack 4.361 + +Slack (MET) : 4.361ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.277ns (logic 0.642ns (7.757%) route 7.635ns (92.243%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.113ns = ( 10.887 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.205 5.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 10.887 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X98Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29]/C + clock pessimism -0.507 10.380 + clock uncertainty -0.093 10.287 + SLICE_X98Y87 FDCE (Recov_fdce_C_CLR) -0.319 9.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][29] + ------------------------------------------------------------------- + required time 9.968 + arrival time -5.607 + ------------------------------------------------------------------- + slack 4.361 + +Slack (MET) : 4.382ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.173ns (logic 0.642ns (7.855%) route 7.531ns (92.145%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.101 5.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.718 10.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X103Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25]/C + clock pessimism -0.507 10.383 + clock uncertainty -0.093 10.290 + SLICE_X103Y84 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][25] + ------------------------------------------------------------------- + required time 9.885 + arrival time -5.503 + ------------------------------------------------------------------- + slack 4.382 + +Slack (MET) : 4.382ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.173ns (logic 0.642ns (7.855%) route 7.531ns (92.145%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.101 5.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X103Y84 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.718 10.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X103Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6]/C + clock pessimism -0.507 10.383 + clock uncertainty -0.093 10.290 + SLICE_X103Y84 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][6] + ------------------------------------------------------------------- + required time 9.885 + arrival time -5.503 + ------------------------------------------------------------------- + slack 4.382 + +Slack (MET) : 4.406ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X99Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25]/C + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][25] + ------------------------------------------------------------------- + required time 9.881 + arrival time -5.475 + ------------------------------------------------------------------- + slack 4.406 + +Slack (MET) : 4.406ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X99Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28]/C + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][28] + ------------------------------------------------------------------- + required time 9.881 + arrival time -5.475 + ------------------------------------------------------------------- + slack 4.406 + +Slack (MET) : 4.406ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X99Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2]/C + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][2] + ------------------------------------------------------------------- + required time 9.881 + arrival time -5.475 + ------------------------------------------------------------------- + slack 4.406 + +Slack (MET) : 4.406ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X99Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X99Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3]/C + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X99Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[0][3] + ------------------------------------------------------------------- + required time 9.881 + arrival time -5.475 + ------------------------------------------------------------------- + slack 4.406 + +Slack (MET) : 4.420ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.718 10.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12]/C + clock pessimism -0.507 10.383 + clock uncertainty -0.093 10.290 + SLICE_X101Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][12] + ------------------------------------------------------------------- + required time 9.885 + arrival time -5.465 + ------------------------------------------------------------------- + slack 4.420 + +Slack (MET) : 4.420ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.718 10.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20]/C + clock pessimism -0.507 10.383 + clock uncertainty -0.093 10.290 + SLICE_X101Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][20] + ------------------------------------------------------------------- + required time 9.885 + arrival time -5.465 + ------------------------------------------------------------------- + slack 4.420 + +Slack (MET) : 4.420ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.134ns (logic 0.642ns (7.893%) route 7.492ns (92.107%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.053ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 10.890 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.062 5.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X101Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.718 10.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X101Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3]/C + clock pessimism -0.507 10.383 + clock uncertainty -0.093 10.290 + SLICE_X101Y87 FDCE (Recov_fdce_C_CLR) -0.405 9.885 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[7][3] + ------------------------------------------------------------------- + required time 9.885 + arrival time -5.465 + ------------------------------------------------------------------- + slack 4.420 + +Slack (MET) : 4.430ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X97Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2]/C + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][2] + ------------------------------------------------------------------- + required time 9.881 + arrival time -5.450 + ------------------------------------------------------------------- + slack 4.430 + +Slack (MET) : 4.430ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X97Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]/C + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31] + ------------------------------------------------------------------- + required time 9.881 + arrival time -5.450 + ------------------------------------------------------------------- + slack 4.430 + +Slack (MET) : 4.430ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X97Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7]/C + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][7] + ------------------------------------------------------------------- + required time 9.881 + arrival time -5.450 + ------------------------------------------------------------------- + slack 4.430 + +Slack (MET) : 4.430ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.120ns (logic 0.642ns (7.906%) route 7.478ns (92.094%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.048 5.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X97Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X97Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8]/C + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X97Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][8] + ------------------------------------------------------------------- + required time 9.881 + arrival time -5.450 + ------------------------------------------------------------------- + slack 4.430 + +Slack (MET) : 4.450ns (required time - arrival time) + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 8.145ns (logic 0.642ns (7.883%) route 7.503ns (92.117%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.114ns = ( 10.886 - 13.000 ) + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.172ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 5.073 5.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 + SLICE_X98Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 13.000 13.000 r + K21 0.000 13.000 r clk (IN) + net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.714 10.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X98Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3]/C + clock pessimism -0.507 10.379 + clock uncertainty -0.093 10.286 + SLICE_X98Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.925 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[6][3] + ------------------------------------------------------------------- + required time 9.925 + arrival time -5.475 + ------------------------------------------------------------------- + slack 4.450 @@ -27107,30 +21214,30 @@ Path Group: **async_default** From Clock: sys_clk To Clock: sys_clk -Setup : 0 Failing Endpoints, Worst Slack 4.581ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 6.335ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 4.581ns (required time - arrival time) +Slack (MET) : 6.335ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.588ns (logic 0.606ns (4.154%) route 13.982ns (95.846%)) + Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.151ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.132ns = ( 17.868 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.243ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27144,14 +21251,14 @@ Slack (MET) : 4.581ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 10.475 12.101 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X85Y50 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27163,34 +21270,34 @@ Slack (MET) : 4.581ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.696 17.868 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X85Y50 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/C - clock pessimism -0.507 17.361 - clock uncertainty -0.071 17.290 - SLICE_X85Y50 FDCE (Recov_fdce_C_CLR) -0.609 16.681 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2] + net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C + clock pessimism -0.514 17.184 + clock uncertainty -0.102 17.081 + SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[1] ------------------------------------------------------------------- - required time 16.681 - arrival time -12.101 + required time 16.558 + arrival time -10.223 ------------------------------------------------------------------- - slack 4.581 + slack 6.335 -Slack (MET) : 5.171ns (required time - arrival time) +Slack (MET) : 6.335ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.003ns (logic 0.606ns (4.328%) route 13.397ns (95.672%)) + Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.243ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27204,14 +21311,14 @@ Slack (MET) : 5.171ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 9.890 11.515 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X77Y52 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27223,34 +21330,34 @@ Slack (MET) : 5.171ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.701 17.873 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X77Y52 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/C - clock pessimism -0.507 17.366 - clock uncertainty -0.071 17.295 - SLICE_X77Y52 FDCE (Recov_fdce_C_CLR) -0.609 16.686 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0] + net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + clock pessimism -0.514 17.184 + clock uncertainty -0.102 17.081 + SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[2] ------------------------------------------------------------------- - required time 16.686 - arrival time -11.515 + required time 16.558 + arrival time -10.223 ------------------------------------------------------------------- - slack 5.171 + slack 6.335 -Slack (MET) : 5.624ns (required time - arrival time) +Slack (MET) : 6.335ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.646ns (logic 0.606ns (4.441%) route 13.040ns (95.559%)) + Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.243ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27264,14 +21371,14 @@ Slack (MET) : 5.624ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 9.533 11.158 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X90Y57 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27283,34 +21390,34 @@ Slack (MET) : 5.624ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.711 17.883 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X90Y57 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/C - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X90Y57 FDCE (Recov_fdce_C_CLR) -0.523 16.782 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2] + net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + clock pessimism -0.514 17.184 + clock uncertainty -0.102 17.081 + SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[5] ------------------------------------------------------------------- - required time 16.782 - arrival time -11.158 + required time 16.558 + arrival time -10.223 ------------------------------------------------------------------- - slack 5.624 + slack 6.335 -Slack (MET) : 6.450ns (required time - arrival time) +Slack (MET) : 6.335ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) + Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.243ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27324,14 +21431,14 @@ Slack (MET) : 6.450ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27343,34 +21450,34 @@ Slack (MET) : 6.450ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.989 18.160 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X29Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/C - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2] + net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + clock pessimism -0.514 17.184 + clock uncertainty -0.102 17.081 + SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[6] ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 + required time 16.558 + arrival time -10.223 ------------------------------------------------------------------- - slack 6.450 + slack 6.335 -Slack (MET) : 6.450ns (required time - arrival time) +Slack (MET) : 6.478ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) + Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.242ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27384,14 +21491,14 @@ Slack (MET) : 6.450ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27403,34 +21510,34 @@ Slack (MET) : 6.450ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.989 18.160 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X29Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/C - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3] + net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + clock pessimism -0.514 17.185 + clock uncertainty -0.102 17.082 + SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[0] ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 + required time 16.559 + arrival time -10.081 ------------------------------------------------------------------- - slack 6.450 + slack 6.478 -Slack (MET) : 6.450ns (required time - arrival time) +Slack (MET) : 6.478ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) + Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.242ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27444,14 +21551,14 @@ Slack (MET) : 6.450ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27463,34 +21570,34 @@ Slack (MET) : 6.450ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.989 18.160 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X29Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/C - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4] + net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + clock pessimism -0.514 17.185 + clock uncertainty -0.102 17.082 + SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[3] ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 + required time 16.559 + arrival time -10.081 ------------------------------------------------------------------- - slack 6.450 + slack 6.478 -Slack (MET) : 6.650ns (required time - arrival time) +Slack (MET) : 6.478ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) + Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.242ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27504,14 +21611,14 @@ Slack (MET) : 6.650ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27523,34 +21630,34 @@ Slack (MET) : 6.650ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X50Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12] + net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C + clock pessimism -0.514 17.185 + clock uncertainty -0.102 17.082 + SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[4] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.047 + required time 16.559 + arrival time -10.081 ------------------------------------------------------------------- - slack 6.650 + slack 6.478 -Slack (MET) : 6.650ns (required time - arrival time) +Slack (MET) : 6.478ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR + Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) + Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.242ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27564,14 +21671,14 @@ Slack (MET) : 6.650ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27583,34 +21690,34 @@ Slack (MET) : 6.650ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X50Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2] + net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C + clock pessimism -0.514 17.185 + clock uncertainty -0.102 17.082 + SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[7] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.047 + required time 16.559 + arrival time -10.081 ------------------------------------------------------------------- - slack 6.650 + slack 6.478 -Slack (MET) : 6.654ns (required time - arrival time) +Slack (MET) : 6.900ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR + Destination: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) + Data Path Delay: 12.246ns (logic 0.668ns (5.455%) route 11.578ns (94.545%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 17.719 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27624,14 +21731,14 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.466 9.673 u_confreg/u_digitaltube_controller/p_0_in + SLICE_X63Y141 FDCE f u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27643,34 +21750,34 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12] + net (fo=9971, routed) 1.547 17.719 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X63Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C + clock pessimism -0.435 17.284 + clock uncertainty -0.102 17.182 + SLICE_X63Y141 FDCE (Recov_fdce_C_CLR) -0.609 16.573 u_confreg/u_digitaltube_controller/dpy0_reg_reg[0] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 16.573 + arrival time -9.673 ------------------------------------------------------------------- - slack 6.654 + slack 6.900 -Slack (MET) : 6.654ns (required time - arrival time) +Slack (MET) : 6.930ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) + Data Path Delay: 12.290ns (logic 0.668ns (5.435%) route 11.622ns (94.565%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.155ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27684,14 +21791,14 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.509 9.716 u_confreg/u_int_ctrl/p_0_in + SLICE_X70Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27703,34 +21810,34 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13] + net (fo=9971, routed) 1.534 17.706 u_confreg/u_int_ctrl/sys_clk + SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C + clock pessimism -0.435 17.271 + clock uncertainty -0.102 17.169 + SLICE_X70Y133 FDCE (Recov_fdce_C_CLR) -0.523 16.646 u_confreg/u_int_ctrl/int_in_sync_d1_reg[1] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 16.646 + arrival time -9.716 ------------------------------------------------------------------- - slack 6.654 + slack 6.930 -Slack (MET) : 6.654ns (required time - arrival time) +Slack (MET) : 6.930ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR + Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) + Data Path Delay: 12.290ns (logic 0.668ns (5.435%) route 11.622ns (94.565%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.155ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27744,14 +21851,14 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 8.509 9.716 u_confreg/u_int_ctrl/p_0_in + SLICE_X70Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27763,34 +21870,34 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14] + net (fo=9971, routed) 1.534 17.706 u_confreg/u_int_ctrl/sys_clk + SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[1]/C + clock pessimism -0.435 17.271 + clock uncertainty -0.102 17.169 + SLICE_X70Y133 FDCE (Recov_fdce_C_CLR) -0.523 16.646 u_confreg/u_int_ctrl/int_in_sync_d2_reg[1] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 16.646 + arrival time -9.716 ------------------------------------------------------------------- - slack 6.654 + slack 6.930 -Slack (MET) : 6.654ns (required time - arrival time) +Slack (MET) : 7.490ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) + Data Path Delay: 11.649ns (logic 0.668ns (5.734%) route 10.981ns (94.266%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.149ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.288ns = ( 17.712 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27804,14 +21911,14 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.868 9.076 u_confreg/u_int_ctrl/p_0_in + SLICE_X65Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27823,34 +21930,34 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15] + net (fo=9971, routed) 1.540 17.712 u_confreg/u_int_ctrl/sys_clk + SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C + clock pessimism -0.435 17.277 + clock uncertainty -0.102 17.175 + SLICE_X65Y133 FDCE (Recov_fdce_C_CLR) -0.609 16.566 u_confreg/u_int_ctrl/int_in_sync_d1_reg[2] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 16.566 + arrival time -9.076 ------------------------------------------------------------------- - slack 6.654 + slack 7.490 -Slack (MET) : 6.814ns (required time - arrival time) +Slack (MET) : 7.490ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR + Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) + Data Path Delay: 11.649ns (logic 0.668ns (5.734%) route 10.981ns (94.266%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.149ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.288ns = ( 17.712 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27864,14 +21971,14 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.868 9.076 u_confreg/u_int_ctrl/p_0_in + SLICE_X65Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27883,34 +21990,34 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11] + net (fo=9971, routed) 1.540 17.712 u_confreg/u_int_ctrl/sys_clk + SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[2]/C + clock pessimism -0.435 17.277 + clock uncertainty -0.102 17.175 + SLICE_X65Y133 FDCE (Recov_fdce_C_CLR) -0.609 16.566 u_confreg/u_int_ctrl/int_in_sync_d2_reg[2] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 + required time 16.566 + arrival time -9.076 ------------------------------------------------------------------- - slack 6.814 + slack 7.490 -Slack (MET) : 6.814ns (required time - arrival time) +Slack (MET) : 7.742ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[23]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) + Data Path Delay: 11.496ns (logic 0.668ns (5.811%) route 10.828ns (94.189%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.137ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27924,14 +22031,14 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.715 8.922 u_confreg/u_int_ctrl/p_0_in + SLICE_X46Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27943,34 +22050,34 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12] + net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk + SLICE_X46Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[23]/C + clock pessimism -0.435 17.289 + clock uncertainty -0.102 17.187 + SLICE_X46Y140 FDCE (Recov_fdce_C_CLR) -0.523 16.664 u_confreg/u_int_ctrl/edge_int_state_reg[23] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 + required time 16.664 + arrival time -8.922 ------------------------------------------------------------------- - slack 6.814 + slack 7.742 -Slack (MET) : 6.814ns (required time - arrival time) +Slack (MET) : 7.801ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[21]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) + Data Path Delay: 11.350ns (logic 0.668ns (5.885%) route 10.682ns (94.115%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.137ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -27984,14 +22091,14 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.569 8.777 u_confreg/u_int_ctrl/p_0_in + SLICE_X47Y139 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28003,34 +22110,34 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19] + net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk + SLICE_X47Y139 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[21]/C + clock pessimism -0.435 17.289 + clock uncertainty -0.102 17.187 + SLICE_X47Y139 FDCE (Recov_fdce_C_CLR) -0.609 16.578 u_confreg/u_int_ctrl/edge_int_state_reg[21] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 + required time 16.578 + arrival time -8.777 ------------------------------------------------------------------- - slack 6.814 + slack 7.801 -Slack (MET) : 6.814ns (required time - arrival time) +Slack (MET) : 7.821ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[29]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) + Data Path Delay: 11.414ns (logic 0.668ns (5.852%) route 10.746ns (94.148%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.139ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28044,14 +22151,14 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.634 8.841 u_confreg/u_int_ctrl/p_0_in + SLICE_X56Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28063,34 +22170,34 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1] + net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk + SLICE_X56Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[29]/C + clock pessimism -0.435 17.287 + clock uncertainty -0.102 17.185 + SLICE_X56Y140 FDCE (Recov_fdce_C_CLR) -0.523 16.662 u_confreg/u_int_ctrl/edge_int_state_reg[29] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 + required time 16.662 + arrival time -8.841 ------------------------------------------------------------------- - slack 6.814 + slack 7.821 -Slack (MET) : 6.881ns (required time - arrival time) +Slack (MET) : 7.851ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[30]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) + Data Path Delay: 11.298ns (logic 0.668ns (5.912%) route 10.630ns (94.088%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.139ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28104,14 +22211,14 @@ Slack (MET) : 6.881ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.517 8.725 u_confreg/u_int_ctrl/p_0_in + SLICE_X55Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28123,34 +22230,34 @@ Slack (MET) : 6.881ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X19Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5] + net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk + SLICE_X55Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[30]/C + clock pessimism -0.435 17.287 + clock uncertainty -0.102 17.185 + SLICE_X55Y140 FDCE (Recov_fdce_C_CLR) -0.609 16.576 u_confreg/u_int_ctrl/edge_int_state_reg[30] ------------------------------------------------------------------- - required time 16.983 - arrival time -10.102 + required time 16.576 + arrival time -8.725 ------------------------------------------------------------------- - slack 6.881 + slack 7.851 -Slack (MET) : 6.881ns (required time - arrival time) +Slack (MET) : 7.963ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[20]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) + Data Path Delay: 11.189ns (logic 0.668ns (5.970%) route 10.521ns (94.030%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.137ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28164,14 +22271,14 @@ Slack (MET) : 6.881ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.408 8.616 u_confreg/u_int_ctrl/p_0_in + SLICE_X49Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28183,34 +22290,34 @@ Slack (MET) : 6.881ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X19Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg + net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk + SLICE_X49Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[20]/C + clock pessimism -0.435 17.289 + clock uncertainty -0.102 17.187 + SLICE_X49Y140 FDCE (Recov_fdce_C_CLR) -0.609 16.578 u_confreg/u_int_ctrl/edge_int_state_reg[20] ------------------------------------------------------------------- - required time 16.983 - arrival time -10.102 + required time 16.578 + arrival time -8.616 ------------------------------------------------------------------- - slack 6.881 + slack 7.963 -Slack (MET) : 6.947ns (required time - arrival time) +Slack (MET) : 8.025ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) + Data Path Delay: 11.122ns (logic 0.668ns (6.006%) route 10.454ns (93.994%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28224,14 +22331,14 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.342 8.549 u_confreg/u_int_ctrl/p_0_in + SLICE_X58Y137 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28243,34 +22350,34 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4] + net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk + SLICE_X58Y137 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[5]/C + clock pessimism -0.435 17.285 + clock uncertainty -0.102 17.183 + SLICE_X58Y137 FDCE (Recov_fdce_C_CLR) -0.609 16.574 u_confreg/u_int_ctrl/edge_int_state_reg[5] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 + required time 16.574 + arrival time -8.549 ------------------------------------------------------------------- - slack 6.947 + slack 8.025 -Slack (MET) : 6.947ns (required time - arrival time) +Slack (MET) : 8.025ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR + Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) + Data Path Delay: 11.122ns (logic 0.668ns (6.006%) route 10.454ns (93.994%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28284,14 +22391,14 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.342 8.549 u_confreg/u_int_ctrl/p_0_in + SLICE_X58Y137 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28303,34 +22410,34 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5] + net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk + SLICE_X58Y137 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/C + clock pessimism -0.435 17.285 + clock uncertainty -0.102 17.183 + SLICE_X58Y137 FDCE (Recov_fdce_C_CLR) -0.609 16.574 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 + required time 16.574 + arrival time -8.549 ------------------------------------------------------------------- - slack 6.947 + slack 8.025 -Slack (MET) : 6.947ns (required time - arrival time) +Slack (MET) : 8.046ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[31]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) + Data Path Delay: 11.103ns (logic 0.668ns (6.016%) route 10.435ns (93.984%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.140ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns = ( 17.721 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28344,14 +22451,14 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.322 8.529 u_confreg/u_int_ctrl/p_0_in + SLICE_X57Y138 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28363,34 +22470,34 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6] + net (fo=9971, routed) 1.549 17.721 u_confreg/u_int_ctrl/sys_clk + SLICE_X57Y138 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[31]/C + clock pessimism -0.435 17.286 + clock uncertainty -0.102 17.184 + SLICE_X57Y138 FDCE (Recov_fdce_C_CLR) -0.609 16.575 u_confreg/u_int_ctrl/edge_int_state_reg[31] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 + required time 16.575 + arrival time -8.529 ------------------------------------------------------------------- - slack 6.947 + slack 8.046 -Slack (MET) : 6.947ns (required time - arrival time) +Slack (MET) : 8.087ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[22]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) + Data Path Delay: 11.063ns (logic 0.668ns (6.038%) route 10.395ns (93.962%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.138ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 17.723 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28404,14 +22511,14 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.282 8.490 u_confreg/u_int_ctrl/p_0_in + SLICE_X50Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28423,34 +22530,34 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7] + net (fo=9971, routed) 1.551 17.723 u_confreg/u_int_ctrl/sys_clk + SLICE_X50Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[22]/C + clock pessimism -0.435 17.288 + clock uncertainty -0.102 17.186 + SLICE_X50Y140 FDCE (Recov_fdce_C_CLR) -0.609 16.577 u_confreg/u_int_ctrl/edge_int_state_reg[22] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 + required time 16.577 + arrival time -8.490 ------------------------------------------------------------------- - slack 6.947 + slack 8.087 -Slack (MET) : 6.955ns (required time - arrival time) +Slack (MET) : 8.111ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) + Data Path Delay: 11.122ns (logic 0.668ns (6.006%) route 10.454ns (93.994%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 17.719 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28464,14 +22571,14 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.341 8.548 u_confreg/u_int_ctrl/p_0_in + SLICE_X60Y136 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28483,34 +22590,34 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14] + net (fo=9971, routed) 1.547 17.719 u_confreg/u_int_ctrl/sys_clk + SLICE_X60Y136 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[5]/C + clock pessimism -0.435 17.284 + clock uncertainty -0.102 17.182 + SLICE_X60Y136 FDCE (Recov_fdce_C_CLR) -0.523 16.659 u_confreg/u_int_ctrl/int_in_sync_d1_reg[5] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 + required time 16.659 + arrival time -8.548 ------------------------------------------------------------------- - slack 6.955 + slack 8.111 -Slack (MET) : 6.955ns (required time - arrival time) +Slack (MET) : 8.111ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR + Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) + Data Path Delay: 11.122ns (logic 0.668ns (6.006%) route 10.454ns (93.994%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns = ( 17.719 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28524,14 +22631,14 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.341 8.548 u_confreg/u_int_ctrl/p_0_in + SLICE_X60Y136 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28543,34 +22650,34 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15] + net (fo=9971, routed) 1.547 17.719 u_confreg/u_int_ctrl/sys_clk + SLICE_X60Y136 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C + clock pessimism -0.435 17.284 + clock uncertainty -0.102 17.182 + SLICE_X60Y136 FDCE (Recov_fdce_C_CLR) -0.523 16.659 u_confreg/u_int_ctrl/int_in_sync_d2_reg[5] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 + required time 16.659 + arrival time -8.548 ------------------------------------------------------------------- - slack 6.955 + slack 8.111 -Slack (MET) : 6.955ns (required time - arrival time) +Slack (MET) : 8.197ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[27]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) + Data Path Delay: 11.039ns (logic 0.668ns (6.051%) route 10.371ns (93.949%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.139ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28584,14 +22691,14 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.258 8.465 u_confreg/u_int_ctrl/p_0_in + SLICE_X46Y137 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28603,34 +22710,34 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5] + net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk + SLICE_X46Y137 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[27]/C + clock pessimism -0.435 17.287 + clock uncertainty -0.102 17.185 + SLICE_X46Y137 FDCE (Recov_fdce_C_CLR) -0.523 16.662 u_confreg/u_int_ctrl/edge_int_state_reg[27] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 + required time 16.662 + arrival time -8.465 ------------------------------------------------------------------- - slack 6.955 + slack 8.197 -Slack (MET) : 6.955ns (required time - arrival time) +Slack (MET) : 8.207ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[28]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) + Data Path Delay: 10.943ns (logic 0.668ns (6.104%) route 10.275ns (93.896%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.138ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 17.723 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28644,14 +22751,14 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.163 8.370 u_confreg/u_int_ctrl/p_0_in + SLICE_X53Y139 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28663,34 +22770,34 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6] + net (fo=9971, routed) 1.551 17.723 u_confreg/u_int_ctrl/sys_clk + SLICE_X53Y139 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[28]/C + clock pessimism -0.435 17.288 + clock uncertainty -0.102 17.186 + SLICE_X53Y139 FDCE (Recov_fdce_C_CLR) -0.609 16.577 u_confreg/u_int_ctrl/edge_int_state_reg[28] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 + required time 16.577 + arrival time -8.370 ------------------------------------------------------------------- - slack 6.955 + slack 8.207 -Slack (MET) : 6.955ns (required time - arrival time) +Slack (MET) : 8.214ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[15]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) + Data Path Delay: 11.024ns (logic 0.668ns (6.060%) route 10.356ns (93.940%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.137ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28704,14 +22811,14 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.243 8.450 u_confreg/u_int_ctrl/p_0_in + SLICE_X48Y139 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28723,34 +22830,34 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7] + net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk + SLICE_X48Y139 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[15]/C + clock pessimism -0.435 17.289 + clock uncertainty -0.102 17.187 + SLICE_X48Y139 FDCE (Recov_fdce_C_CLR) -0.523 16.664 u_confreg/u_int_ctrl/edge_int_state_reg[15] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 + required time 16.664 + arrival time -8.450 ------------------------------------------------------------------- - slack 6.955 + slack 8.214 -Slack (MET) : 6.955ns (required time - arrival time) +Slack (MET) : 8.244ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) + Data Path Delay: 10.947ns (logic 0.668ns (6.102%) route 10.279ns (93.898%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28764,14 +22871,14 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.166 8.374 u_confreg/u_int_ctrl/p_0_in + SLICE_X56Y137 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28783,34 +22890,34 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8] + net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk + SLICE_X56Y137 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[4]/C + clock pessimism -0.435 17.285 + clock uncertainty -0.102 17.183 + SLICE_X56Y137 FDCE (Recov_fdce_C_CLR) -0.565 16.618 u_confreg/u_int_ctrl/int_in_sync_d1_reg[4] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 + required time 16.618 + arrival time -8.374 ------------------------------------------------------------------- - slack 6.955 + slack 8.244 -Slack (MET) : 6.967ns (required time - arrival time) +Slack (MET) : 8.256ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) + Data Path Delay: 10.851ns (logic 0.668ns (6.156%) route 10.183ns (93.844%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28824,14 +22931,14 @@ Slack (MET) : 6.967ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.070 8.278 u_Axi_CDC/bFifo/popToPushGray_buffercc/p_0_in_1 + SLICE_X94Y122 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28843,34 +22950,34 @@ Slack (MET) : 6.967ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X18Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7] + net (fo=9971, routed) 1.536 17.708 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.507 17.201 + clock uncertainty -0.102 17.099 + SLICE_X94Y122 FDCE (Recov_fdce_C_CLR) -0.565 16.534 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 + required time 16.534 + arrival time -8.278 ------------------------------------------------------------------- - slack 6.967 + slack 8.256 -Slack (MET) : 6.967ns (required time - arrival time) +Slack (MET) : 8.256ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) + Data Path Delay: 10.851ns (logic 0.668ns (6.156%) route 10.183ns (93.844%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28884,14 +22991,14 @@ Slack (MET) : 6.967ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.070 8.278 u_Axi_CDC/bFifo/popToPushGray_buffercc/p_0_in_1 + SLICE_X94Y122 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28903,34 +23010,34 @@ Slack (MET) : 6.967ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X18Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8] + net (fo=9971, routed) 1.536 17.708 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.507 17.201 + clock uncertainty -0.102 17.099 + SLICE_X94Y122 FDCE (Recov_fdce_C_CLR) -0.565 16.534 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 + required time 16.534 + arrival time -8.278 ------------------------------------------------------------------- - slack 6.967 + slack 8.256 -Slack (MET) : 6.967ns (required time - arrival time) +Slack (MET) : 8.256ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) + Data Path Delay: 10.851ns (logic 0.668ns (6.156%) route 10.183ns (93.844%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -28944,14 +23051,14 @@ Slack (MET) : 6.967ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.070 8.278 u_Axi_CDC/bFifo/popToPushGray_buffercc/p_0_in_1 + SLICE_X94Y122 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28963,34 +23070,34 @@ Slack (MET) : 6.967ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X18Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9] + net (fo=9971, routed) 1.536 17.708 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.507 17.201 + clock uncertainty -0.102 17.099 + SLICE_X94Y122 FDCE (Recov_fdce_C_CLR) -0.565 16.534 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 + required time 16.534 + arrival time -8.278 ------------------------------------------------------------------- - slack 6.967 + slack 8.256 -Slack (MET) : 6.996ns (required time - arrival time) +Slack (MET) : 8.257ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[24]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) + Data Path Delay: 10.893ns (logic 0.668ns (6.132%) route 10.225ns (93.868%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.138ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns = ( 17.723 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29004,14 +23111,14 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.112 8.320 u_confreg/u_int_ctrl/p_0_in + SLICE_X51Y139 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29023,34 +23130,34 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0] + net (fo=9971, routed) 1.551 17.723 u_confreg/u_int_ctrl/sys_clk + SLICE_X51Y139 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[24]/C + clock pessimism -0.435 17.288 + clock uncertainty -0.102 17.186 + SLICE_X51Y139 FDCE (Recov_fdce_C_CLR) -0.609 16.577 u_confreg/u_int_ctrl/edge_int_state_reg[24] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 + required time 16.577 + arrival time -8.320 ------------------------------------------------------------------- - slack 6.996 + slack 8.257 -Slack (MET) : 6.996ns (required time - arrival time) +Slack (MET) : 8.271ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR + Destination: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) + Data Path Delay: 10.839ns (logic 0.668ns (6.163%) route 10.171ns (93.837%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns = ( 17.710 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29064,14 +23171,14 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.058 8.265 u_Axi_CDC/bFifo/p_0_in_1 + SLICE_X94Y121 FDCE f u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29083,34 +23190,34 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10] + net (fo=9971, routed) 1.538 17.710 u_Axi_CDC/bFifo/sys_clk + SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.507 17.203 + clock uncertainty -0.102 17.101 + SLICE_X94Y121 FDCE (Recov_fdce_C_CLR) -0.565 16.536 u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 + required time 16.536 + arrival time -8.265 ------------------------------------------------------------------- - slack 6.996 + slack 8.271 -Slack (MET) : 6.996ns (required time - arrival time) +Slack (MET) : 8.271ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR + Destination: u_Axi_CDC/bFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) + Data Path Delay: 10.839ns (logic 0.668ns (6.163%) route 10.171ns (93.837%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns = ( 17.710 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29124,14 +23231,14 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.058 8.265 u_Axi_CDC/bFifo/p_0_in_1 + SLICE_X94Y121 FDCE f u_Axi_CDC/bFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29143,34 +23250,34 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3] + net (fo=9971, routed) 1.538 17.710 u_Axi_CDC/bFifo/sys_clk + SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.507 17.203 + clock uncertainty -0.102 17.101 + SLICE_X94Y121 FDCE (Recov_fdce_C_CLR) -0.565 16.536 u_Axi_CDC/bFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 + required time 16.536 + arrival time -8.265 ------------------------------------------------------------------- - slack 6.996 + slack 8.271 -Slack (MET) : 6.996ns (required time - arrival time) +Slack (MET) : 8.286ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) + Data Path Delay: 10.947ns (logic 0.668ns (6.102%) route 10.279ns (93.898%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29184,14 +23291,14 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.166 8.374 u_confreg/u_int_ctrl/p_0_in + SLICE_X56Y137 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29203,34 +23310,34 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4] + net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk + SLICE_X56Y137 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[4]/C + clock pessimism -0.435 17.285 + clock uncertainty -0.102 17.183 + SLICE_X56Y137 FDCE (Recov_fdce_C_CLR) -0.523 16.660 u_confreg/u_int_ctrl/edge_int_state_reg[4] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 + required time 16.660 + arrival time -8.374 ------------------------------------------------------------------- - slack 6.996 + slack 8.286 -Slack (MET) : 6.996ns (required time - arrival time) +Slack (MET) : 8.286ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR + Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) + Data Path Delay: 10.947ns (logic 0.668ns (6.102%) route 10.279ns (93.898%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29244,14 +23351,14 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.166 8.374 u_confreg/u_int_ctrl/p_0_in + SLICE_X56Y137 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29263,34 +23370,34 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9] + net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk + SLICE_X56Y137 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[4]/C + clock pessimism -0.435 17.285 + clock uncertainty -0.102 17.183 + SLICE_X56Y137 FDCE (Recov_fdce_C_CLR) -0.523 16.660 u_confreg/u_int_ctrl/int_in_sync_d2_reg[4] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 + required time 16.660 + arrival time -8.374 ------------------------------------------------------------------- - slack 6.996 + slack 8.286 -Slack (MET) : 7.098ns (required time - arrival time) +Slack (MET) : 8.286ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR + Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) + Data Path Delay: 10.947ns (logic 0.668ns (6.102%) route 10.279ns (93.898%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29304,14 +23411,14 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.166 8.374 u_confreg/u_int_ctrl/p_0_in + SLICE_X56Y137 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29323,34 +23430,34 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10] + net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk + SLICE_X56Y137 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[4]/C + clock pessimism -0.435 17.285 + clock uncertainty -0.102 17.183 + SLICE_X56Y137 FDCE (Recov_fdce_C_CLR) -0.523 16.660 u_confreg/u_int_ctrl/int_in_sync_d3_reg[4] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 + required time 16.660 + arrival time -8.374 ------------------------------------------------------------------- - slack 7.098 + slack 8.286 -Slack (MET) : 7.098ns (required time - arrival time) +Slack (MET) : 8.298ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) + Data Path Delay: 10.851ns (logic 0.668ns (6.156%) route 10.183ns (93.844%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29364,14 +23471,14 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.070 8.278 u_Axi_CDC/bFifo/popToPushGray_buffercc/p_0_in_1 + SLICE_X94Y122 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29383,34 +23490,34 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11] + net (fo=9971, routed) 1.536 17.708 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.507 17.201 + clock uncertainty -0.102 17.099 + SLICE_X94Y122 FDCE (Recov_fdce_C_CLR) -0.523 16.576 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 + required time 16.576 + arrival time -8.278 ------------------------------------------------------------------- - slack 7.098 + slack 8.298 -Slack (MET) : 7.098ns (required time - arrival time) +Slack (MET) : 8.298ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) + Data Path Delay: 10.851ns (logic 0.668ns (6.156%) route 10.183ns (93.844%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29424,14 +23531,14 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.070 8.278 u_Axi_CDC/bFifo/popToPushGray_buffercc/p_0_in_1 + SLICE_X94Y122 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29443,34 +23550,34 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8] + net (fo=9971, routed) 1.536 17.708 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.507 17.201 + clock uncertainty -0.102 17.099 + SLICE_X94Y122 FDCE (Recov_fdce_C_CLR) -0.523 16.576 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 + required time 16.576 + arrival time -8.278 ------------------------------------------------------------------- - slack 7.098 + slack 8.298 -Slack (MET) : 7.098ns (required time - arrival time) +Slack (MET) : 8.298ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) + Data Path Delay: 10.851ns (logic 0.668ns (6.156%) route 10.183ns (93.844%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29484,14 +23591,14 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.070 8.278 u_Axi_CDC/bFifo/popToPushGray_buffercc/p_0_in_1 + SLICE_X94Y122 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29503,34 +23610,34 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9] + net (fo=9971, routed) 1.536 17.708 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.507 17.201 + clock uncertainty -0.102 17.099 + SLICE_X94Y122 FDCE (Recov_fdce_C_CLR) -0.523 16.576 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 + required time 16.576 + arrival time -8.278 ------------------------------------------------------------------- - slack 7.098 + slack 8.298 -Slack (MET) : 7.115ns (required time - arrival time) +Slack (MET) : 8.313ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR + Destination: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) + Data Path Delay: 10.839ns (logic 0.668ns (6.163%) route 10.171ns (93.837%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns = ( 17.710 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29544,14 +23651,14 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.058 8.265 u_Axi_CDC/bFifo/p_0_in_1 + SLICE_X94Y121 FDCE f u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29563,34 +23670,34 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13] + net (fo=9971, routed) 1.538 17.710 u_Axi_CDC/bFifo/sys_clk + SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.507 17.203 + clock uncertainty -0.102 17.101 + SLICE_X94Y121 FDCE (Recov_fdce_C_CLR) -0.523 16.578 u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 + required time 16.578 + arrival time -8.265 ------------------------------------------------------------------- - slack 7.115 + slack 8.313 -Slack (MET) : 7.115ns (required time - arrival time) +Slack (MET) : 8.313ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR + Destination: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) + Data Path Delay: 10.839ns (logic 0.668ns (6.163%) route 10.171ns (93.837%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns = ( 17.710 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29604,14 +23711,14 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.058 8.265 u_Axi_CDC/bFifo/p_0_in_1 + SLICE_X94Y121 FDCE f u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29623,34 +23730,34 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16] + net (fo=9971, routed) 1.538 17.710 u_Axi_CDC/bFifo/sys_clk + SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.507 17.203 + clock uncertainty -0.102 17.101 + SLICE_X94Y121 FDCE (Recov_fdce_C_CLR) -0.523 16.578 u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 + required time 16.578 + arrival time -8.265 ------------------------------------------------------------------- - slack 7.115 + slack 8.313 -Slack (MET) : 7.115ns (required time - arrival time) +Slack (MET) : 8.313ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR + Destination: u_Axi_CDC/bFifo/pushCC_pushPtr_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) + Data Path Delay: 10.839ns (logic 0.668ns (6.163%) route 10.171ns (93.837%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns = ( 17.710 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29664,14 +23771,14 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.058 8.265 u_Axi_CDC/bFifo/p_0_in_1 + SLICE_X94Y121 FDCE f u_Axi_CDC/bFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29683,34 +23790,34 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21] + net (fo=9971, routed) 1.538 17.710 u_Axi_CDC/bFifo/sys_clk + SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.507 17.203 + clock uncertainty -0.102 17.101 + SLICE_X94Y121 FDCE (Recov_fdce_C_CLR) -0.523 16.578 u_Axi_CDC/bFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 + required time 16.578 + arrival time -8.265 ------------------------------------------------------------------- - slack 7.115 + slack 8.313 -Slack (MET) : 7.115ns (required time - arrival time) +Slack (MET) : 8.408ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR + Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) + Data Path Delay: 10.716ns (logic 0.668ns (6.234%) route 10.048ns (93.766%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29724,14 +23831,14 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.935 8.142 u_fft_mlkem_axi_slave/p_0_in + SLICE_X96Y110 FDCE f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29743,34 +23850,34 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22] + net (fo=9971, routed) 1.552 17.724 u_fft_mlkem_axi_slave/sys_clk + SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C + clock pessimism -0.507 17.217 + clock uncertainty -0.102 17.115 + SLICE_X96Y110 FDCE (Recov_fdce_C_CLR) -0.565 16.550 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 + required time 16.550 + arrival time -8.142 ------------------------------------------------------------------- - slack 7.115 + slack 8.408 -Slack (MET) : 7.115ns (required time - arrival time) +Slack (MET) : 8.448ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[25]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) + Data Path Delay: 10.788ns (logic 0.668ns (6.192%) route 10.120ns (93.808%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.139ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29784,14 +23891,14 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.007 8.214 u_confreg/u_int_ctrl/p_0_in + SLICE_X52Y138 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29803,34 +23910,34 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23] + net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk + SLICE_X52Y138 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[25]/C + clock pessimism -0.435 17.287 + clock uncertainty -0.102 17.185 + SLICE_X52Y138 FDCE (Recov_fdce_C_CLR) -0.523 16.662 u_confreg/u_int_ctrl/edge_int_state_reg[25] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 + required time 16.662 + arrival time -8.214 ------------------------------------------------------------------- - slack 7.115 + slack 8.448 -Slack (MET) : 7.136ns (required time - arrival time) +Slack (MET) : 8.450ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR + Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) + Data Path Delay: 10.716ns (logic 0.668ns (6.234%) route 10.048ns (93.766%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: -0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29844,14 +23951,14 @@ Slack (MET) : 7.136ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.935 8.142 u_fft_mlkem_axi_slave/p_0_in + SLICE_X96Y110 FDCE f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29863,34 +23970,34 @@ Slack (MET) : 7.136ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.711 17.883 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/C - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17] + net (fo=9971, routed) 1.552 17.724 u_fft_mlkem_axi_slave/sys_clk + SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C + clock pessimism -0.507 17.217 + clock uncertainty -0.102 17.115 + SLICE_X96Y110 FDCE (Recov_fdce_C_CLR) -0.523 16.592 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.561 + required time 16.592 + arrival time -8.142 ------------------------------------------------------------------- - slack 7.136 + slack 8.450 -Slack (MET) : 7.136ns (required time - arrival time) +Slack (MET) : 8.457ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[26]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) + Data Path Delay: 10.692ns (logic 0.668ns (6.247%) route 10.024ns (93.753%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.139ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29904,14 +24011,14 @@ Slack (MET) : 7.136ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.912 8.119 u_confreg/u_int_ctrl/p_0_in + SLICE_X49Y137 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29923,34 +24030,34 @@ Slack (MET) : 7.136ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.711 17.883 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/C - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18] + net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk + SLICE_X49Y137 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[26]/C + clock pessimism -0.435 17.287 + clock uncertainty -0.102 17.185 + SLICE_X49Y137 FDCE (Recov_fdce_C_CLR) -0.609 16.576 u_confreg/u_int_ctrl/edge_int_state_reg[26] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.561 + required time 16.576 + arrival time -8.119 ------------------------------------------------------------------- - slack 7.136 + slack 8.457 -Slack (MET) : 7.143ns (required time - arrival time) +Slack (MET) : 8.490ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.414ns (logic 0.606ns (4.882%) route 11.808ns (95.118%)) + Data Path Delay: 10.655ns (logic 0.668ns (6.269%) route 9.987ns (93.731%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.282ns = ( 17.718 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -29964,14 +24071,14 @@ Slack (MET) : 7.143ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.301 9.926 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.875 8.082 u_confreg/u_int_ctrl/p_0_in + SLICE_X58Y134 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29983,34 +24090,34 @@ Slack (MET) : 7.143ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X18Y1 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6] + net (fo=9971, routed) 1.546 17.718 u_confreg/u_int_ctrl/sys_clk + SLICE_X58Y134 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[1]/C + clock pessimism -0.435 17.283 + clock uncertainty -0.102 17.181 + SLICE_X58Y134 FDCE (Recov_fdce_C_CLR) -0.609 16.572 u_confreg/u_int_ctrl/edge_int_state_reg[1] ------------------------------------------------------------------- - required time 17.069 - arrival time -9.926 + required time 16.572 + arrival time -8.082 ------------------------------------------------------------------- - slack 7.143 + slack 8.490 -Slack (MET) : 7.222ns (required time - arrival time) +Slack (MET) : 8.490ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) + Data Path Delay: 10.655ns (logic 0.668ns (6.269%) route 9.987ns (93.731%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.282ns = ( 17.718 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -30024,14 +24131,14 @@ Slack (MET) : 7.222ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.875 8.082 u_confreg/u_int_ctrl/p_0_in + SLICE_X58Y134 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -30043,34 +24150,34 @@ Slack (MET) : 7.222ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.714 17.886 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y62 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/C - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0] + net (fo=9971, routed) 1.546 17.718 u_confreg/u_int_ctrl/sys_clk + SLICE_X58Y134 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[2]/C + clock pessimism -0.435 17.283 + clock uncertainty -0.102 17.181 + SLICE_X58Y134 FDCE (Recov_fdce_C_CLR) -0.609 16.572 u_confreg/u_int_ctrl/edge_int_state_reg[2] ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 + required time 16.572 + arrival time -8.082 ------------------------------------------------------------------- - slack 7.222 + slack 8.490 -Slack (MET) : 7.222ns (required time - arrival time) +Slack (MET) : 8.490ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR + Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) + Data Path Delay: 10.655ns (logic 0.668ns (6.269%) route 9.987ns (93.731%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.282ns = ( 17.718 - 20.000 ) + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): -0.435ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -30084,14 +24191,14 @@ Slack (MET) : 7.222ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.875 8.082 u_confreg/u_int_ctrl/p_0_in + SLICE_X58Y134 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -30103,16 +24210,16 @@ Slack (MET) : 7.222ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.714 17.886 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y62 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/C - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1] + net (fo=9971, routed) 1.546 17.718 u_confreg/u_int_ctrl/sys_clk + SLICE_X58Y134 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[1]/C + clock pessimism -0.435 17.283 + clock uncertainty -0.102 17.181 + SLICE_X58Y134 FDCE (Recov_fdce_C_CLR) -0.609 16.572 u_confreg/u_int_ctrl/int_in_sync_d3_reg[1] ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 + required time 16.572 + arrival time -8.082 ------------------------------------------------------------------- - slack 7.222 + slack 8.490 @@ -30130,126 +24237,22 @@ Min Delay 0 Endpoints Max Delay Paths -------------------------------------------------------------------------------------- -Slack: inf - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 9.445ns (logic 0.606ns (6.416%) route 8.839ns (93.584%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.470ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.332 6.958 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 - SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - -Slack: inf - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 9.445ns (logic 0.606ns (6.416%) route 8.839ns (93.584%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.470ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.332 6.958 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 - SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_cpu/delay_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 9.183ns (logic 0.606ns (6.599%) route 8.577ns (93.401%)) + Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.738ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.290ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -30264,14 +24267,14 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.070 6.696 pll_clk.u_rst_cpu/p_0_in_0 - SLICE_X0Y48 FDCE f pll_clk.u_rst_cpu/delay_reg[0]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.617 7.824 pll_clk.u_rst_cpu/p_0_in_0 + SLICE_X92Y115 FDCE f pll_clk.u_rst_cpu/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -30283,25 +24286,25 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[0]/C + net (fo=6484, routed) 1.544 -2.284 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[0]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_cpu/delay_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 9.183ns (logic 0.606ns (6.599%) route 8.577ns (93.401%)) + Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.738ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.290ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -30316,14 +24319,14 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.070 6.696 pll_clk.u_rst_cpu/p_0_in_0 - SLICE_X0Y48 FDCE f pll_clk.u_rst_cpu/delay_reg[1]/CLR + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.617 7.824 pll_clk.u_rst_cpu/p_0_in_0 + SLICE_X92Y115 FDCE f pll_clk.u_rst_cpu/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -30335,25 +24338,25 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + net (fo=6484, routed) 1.544 -2.284 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C Slack: inf - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C + Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[5]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 4.254ns (logic 0.419ns (9.850%) route 3.835ns (90.150%)) - Logic Levels: 0 - Clock Path Skew: 0.544ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.939ns - Source Clock Delay (SCD): -2.483ns + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.290ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -30368,12 +24371,14 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.859 -2.483 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.419 -2.064 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/Q - net (fo=1, routed) 3.835 1.771 u_cpu/u_csr/interrupt[3] - SLICE_X50Y37 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.617 7.824 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 + SLICE_X92Y115 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -30385,25 +24390,25 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.890 -1.939 u_cpu/u_csr/cpu_clk - SLICE_X50Y37 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C + net (fo=6484, routed) 1.544 -2.284 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.608ns (logic 0.595ns (37.010%) route 1.013ns (62.990%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.352ns + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.290ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns + Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -30412,253 +24417,50 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.243 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 1.013 1.256 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.617 7.824 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 + SLICE_X92Y115 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.565ns (logic 0.612ns (39.107%) route 0.953ns (60.893%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.262 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 0.953 1.215 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] - SLICE_X15Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.566ns (logic 0.612ns (39.088%) route 0.954ns (60.912%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.260 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 0.954 1.214 u_Axi_CDC/rFifo/_zz_ram_port10__2[18] - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.491ns (logic 0.482ns (32.335%) route 1.009ns (67.665%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 1.009 1.138 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.465ns (logic 0.612ns (41.773%) route 0.853ns (58.227%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.260 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 0.853 1.113 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.544 -2.284 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.455ns (logic 0.612ns (42.062%) route 0.843ns (57.938%)) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.208ns (logic 1.344ns (25.806%) route 3.864ns (74.194%)) Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns + Clock Path Skew: 0.107ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -30667,1323 +24469,49 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.262 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 0.843 1.105 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 1.344 -1.053 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 3.864 2.811 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.417ns (logic 0.480ns (33.882%) route 0.937ns (66.118%)) - Logic Levels: 0 - Clock Path Skew: -0.145ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.127 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.937 1.063 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.406ns (logic 0.595ns (42.317%) route 0.811ns (57.683%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.245 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 0.811 1.056 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.401ns (logic 0.491ns (35.055%) route 0.910ns (64.945%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.141 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 0.910 1.050 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.394ns (logic 0.480ns (34.421%) route 0.914ns (65.579%)) - Logic Levels: 0 - Clock Path Skew: -0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 0.914 1.044 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.361ns (logic 0.480ns (35.268%) route 0.881ns (64.732%)) - Logic Levels: 0 - Clock Path Skew: -0.145ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.497ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.128 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.881 1.009 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] - SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.354ns (logic 0.485ns (35.824%) route 0.869ns (64.176%)) - Logic Levels: 0 - Clock Path Skew: -0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.135 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O - net (fo=1, routed) 0.869 1.004 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.323ns (logic 0.612ns (46.260%) route 0.711ns (53.740%)) - Logic Levels: 0 - Clock Path Skew: -0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.494ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.259 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.711 0.970 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.317ns (logic 0.595ns (45.169%) route 0.722ns (54.831%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.245 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O - net (fo=1, routed) 0.722 0.967 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.310ns (logic 0.595ns (45.409%) route 0.715ns (54.591%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.243 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 0.715 0.958 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.304ns (logic 0.491ns (37.657%) route 0.813ns (62.343%)) - Logic Levels: 0 - Clock Path Skew: -0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.141 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.813 0.954 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.294ns (logic 0.612ns (47.295%) route 0.682ns (52.705%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.566ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.259 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 0.682 0.941 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] - SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.696 -0.566 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.256ns (logic 0.482ns (38.384%) route 0.774ns (61.616%)) - Logic Levels: 0 - Clock Path Skew: -0.143ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.129 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.774 0.903 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.248ns (logic 0.595ns (47.682%) route 0.653ns (52.318%)) - Logic Levels: 0 - Clock Path Skew: -0.143ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.242 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 0.653 0.895 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.241ns (logic 0.491ns (39.556%) route 0.750ns (60.444%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.139 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 0.750 0.889 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.241ns (logic 0.485ns (39.089%) route 0.756ns (60.911%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.133 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 0.756 0.889 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.233ns (logic 0.482ns (39.088%) route 0.751ns (60.912%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.494ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 0.751 0.883 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.235ns (logic 0.491ns (39.769%) route 0.744ns (60.231%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.139 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 0.744 0.882 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.232ns (logic 0.595ns (48.288%) route 0.637ns (51.712%)) - Logic Levels: 0 - Clock Path Skew: -0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.494ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.242 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 0.637 0.879 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.225ns (logic 0.482ns (39.361%) route 0.743ns (60.639%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 0.743 0.872 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.222ns (logic 0.482ns (39.449%) route 0.740ns (60.551%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 0.740 0.872 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.215ns (logic 0.480ns (39.516%) route 0.735ns (60.484%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.128 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 0.735 0.863 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.194ns (logic 0.480ns (40.215%) route 0.714ns (59.785%)) - Logic Levels: 0 - Clock Path Skew: -0.217ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.567ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 0.714 0.843 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] - SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.695 -0.567 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C - -Slack: inf - Source: u_confreg/int_out_or_q2_reg/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[2]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.180ns (logic 0.175ns (14.825%) route 1.005ns (85.175%)) - Logic Levels: 0 - Clock Path Skew: -0.172ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.509ns - Source Clock Delay (SCD): -0.337ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.971 -0.337 u_confreg/sys_clk - SLICE_X11Y58 FDRE r u_confreg/int_out_or_q2_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X11Y58 FDRE (Prop_fdre_C_Q) 0.175 -0.162 r u_confreg/int_out_or_q2_reg/Q - net (fo=1, routed) 1.005 0.843 u_cpu/u_csr/interrupt[0] - SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk - SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.135ns (logic 0.491ns (43.278%) route 0.644ns (56.722%)) - Logic Levels: 0 - Clock Path Skew: -0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.494ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O - net (fo=1, routed) 0.644 0.781 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.130ns (logic 0.485ns (42.936%) route 0.645ns (57.064%)) - Logic Levels: 0 - Clock Path Skew: -0.143ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 0.645 0.776 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.122ns (logic 0.485ns (43.231%) route 0.637ns (56.769%)) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.118ns (logic 1.336ns (26.105%) route 3.782ns (73.895%)) Logic Levels: 0 - Clock Path Skew: -0.216ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.566ns - Source Clock Delay (SCD): -0.350ns + Clock Path Skew: 0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -31992,49 +24520,49 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.135 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 0.637 0.772 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] - SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.336 -1.062 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O + net (fo=1, routed) 3.782 2.720 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.696 -0.566 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.111ns (logic 0.491ns (44.191%) route 0.620ns (55.809%)) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.096ns (logic 1.317ns (25.844%) route 3.779ns (74.156%)) Logic Levels: 0 - Clock Path Skew: -0.214ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.567ns - Source Clock Delay (SCD): -0.353ns + Clock Path Skew: 0.104ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -32043,49 +24571,457 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 0.620 0.758 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] - SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 1.317 -1.080 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O + net (fo=1, routed) 3.779 2.699 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.695 -0.567 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.064ns (logic 1.314ns (25.947%) route 3.750ns (74.053%)) + Logic Levels: 0 + Clock Path Skew: 0.106ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.314 -1.084 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O + net (fo=1, routed) 3.750 2.667 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.040ns (logic 1.309ns (25.973%) route 3.731ns (74.027%)) + Logic Levels: 0 + Clock Path Skew: 0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.309 -1.089 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 3.731 2.642 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.035ns (logic 1.314ns (26.100%) route 3.721ns (73.900%)) + Logic Levels: 0 + Clock Path Skew: 0.107ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.397ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 1.314 -1.083 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O + net (fo=1, routed) 3.721 2.638 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.971ns (logic 1.344ns (27.035%) route 3.627ns (72.965%)) + Logic Levels: 0 + Clock Path Skew: 0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.344 -1.054 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 3.627 2.574 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.947ns (logic 1.344ns (27.169%) route 3.603ns (72.831%)) + Logic Levels: 0 + Clock Path Skew: 0.106ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.344 -1.054 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 3.603 2.549 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.937ns (logic 1.317ns (26.677%) route 3.620ns (73.323%)) + Logic Levels: 0 + Clock Path Skew: 0.106ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.317 -1.081 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O + net (fo=1, routed) 3.620 2.539 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.925ns (logic 1.309ns (26.579%) route 3.616ns (73.421%)) + Logic Levels: 0 + Clock Path Skew: 0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.309 -1.089 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 3.616 2.527 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.852ns (logic 1.317ns (27.146%) route 3.535ns (72.854%)) + Logic Levels: 0 + Clock Path Skew: 0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.317 -1.081 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O + net (fo=1, routed) 3.535 2.454 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] + SLICE_X93Y111 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y111 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.097ns (logic 0.485ns (44.212%) route 0.612ns (55.788%)) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.709ns (logic 1.336ns (28.372%) route 3.373ns (71.628%)) Logic Levels: 0 - Clock Path Skew: -0.214ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.566ns - Source Clock Delay (SCD): -0.352ns + Clock Path Skew: 0.119ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -32094,49 +25030,916 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.133 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O - net (fo=1, routed) 0.612 0.745 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] - SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.336 -1.076 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O + net (fo=1, routed) 3.373 2.297 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.696 -0.566 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.686ns (logic 1.314ns (28.042%) route 3.372ns (71.958%)) + Logic Levels: 0 + Clock Path Skew: 0.119ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.314 -1.098 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O + net (fo=1, routed) 3.372 2.274 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.616ns (logic 1.336ns (28.941%) route 3.280ns (71.059%)) + Logic Levels: 0 + Clock Path Skew: 0.104ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.397ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 1.336 -1.061 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O + net (fo=1, routed) 3.280 2.220 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.560ns (logic 1.343ns (29.450%) route 3.217ns (70.550%)) + Logic Levels: 0 + Clock Path Skew: 0.106ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.343 -1.055 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O + net (fo=1, routed) 3.217 2.163 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.469ns (logic 1.309ns (29.293%) route 3.160ns (70.707%)) + Logic Levels: 0 + Clock Path Skew: 0.105ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns + Source Clock Delay (SCD): -2.397ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 1.309 -1.088 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 3.160 2.072 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.451ns (logic 1.344ns (30.195%) route 3.107ns (69.805%)) + Logic Levels: 0 + Clock Path Skew: 0.119ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.344 -1.068 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/O + net (fo=1, routed) 3.107 2.040 u_Axi_CDC/rFifo/_zz_ram_port10__2[18] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.433ns (logic 1.343ns (30.296%) route 3.090ns (69.704%)) + Logic Levels: 0 + Clock Path Skew: 0.105ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns + Source Clock Delay (SCD): -2.397ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 1.343 -1.054 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O + net (fo=1, routed) 3.090 2.036 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.432ns (logic 1.309ns (29.538%) route 3.123ns (70.462%)) + Logic Levels: 0 + Clock Path Skew: 0.119ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.309 -1.103 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O + net (fo=1, routed) 3.123 2.020 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.415ns (logic 1.309ns (29.648%) route 3.106ns (70.352%)) + Logic Levels: 0 + Clock Path Skew: 0.120ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.309 -1.103 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 3.106 2.004 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.328ns (logic 1.336ns (30.870%) route 2.992ns (69.130%)) + Logic Levels: 0 + Clock Path Skew: 0.119ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.336 -1.076 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O + net (fo=1, routed) 2.992 1.916 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.304ns (logic 1.344ns (31.229%) route 2.960ns (68.771%)) + Logic Levels: 0 + Clock Path Skew: 0.119ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.344 -1.068 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 2.960 1.892 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.300ns (logic 1.317ns (30.629%) route 2.983ns (69.371%)) + Logic Levels: 0 + Clock Path Skew: 0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.289ns + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.317 -1.095 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O + net (fo=1, routed) 2.983 1.888 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.539 -2.289 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.288ns (logic 1.317ns (30.712%) route 2.971ns (69.288%)) + Logic Levels: 0 + Clock Path Skew: 0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.289ns + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.317 -1.095 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O + net (fo=1, routed) 2.971 1.877 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.539 -2.289 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.352ns (logic 1.343ns (30.862%) route 3.009ns (69.138%)) + Logic Levels: 0 + Clock Path Skew: 0.202ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.495ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.847 -2.495 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X46Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y95 RAMD32 (Prop_ramd32_CLK_O) + 1.343 -1.152 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O + net (fo=1, routed) 3.009 1.857 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.253ns (logic 1.336ns (31.411%) route 2.917ns (68.589%)) + Logic Levels: 0 + Clock Path Skew: 0.109ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.289ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.336 -1.062 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O + net (fo=1, routed) 2.917 1.856 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.539 -2.289 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.251ns (logic 1.314ns (30.911%) route 2.937ns (69.089%)) + Logic Levels: 0 + Clock Path Skew: 0.105ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.314 -1.084 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O + net (fo=1, routed) 2.937 1.853 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.252ns (logic 1.343ns (31.587%) route 2.909ns (68.413%)) + Logic Levels: 0 + Clock Path Skew: 0.122ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.343 -1.069 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O + net (fo=1, routed) 2.909 1.840 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 4.172ns (logic 1.343ns (32.194%) route 2.829ns (67.806%)) + Logic Levels: 0 + Clock Path Skew: 0.119ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.343 -1.069 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O + net (fo=1, routed) 2.829 1.760 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.089ns (logic 0.482ns (44.271%) route 0.607ns (55.729%)) + Data Path Delay: 2.079ns (logic 0.612ns (29.443%) route 1.467ns (70.557%)) Logic Levels: 0 - Clock Path Skew: -0.219ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.569ns - Source Clock Delay (SCD): -0.350ns + Clock Path Skew: -0.311ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.691ns + Source Clock Delay (SCD): -0.380ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -32151,13 +25954,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X16Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + net (fo=9971, routed) 0.928 -0.380 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X46Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O - net (fo=1, routed) 0.607 0.739 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] - SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D + SLICE_X46Y95 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.232 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O + net (fo=1, routed) 1.467 1.698 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -32169,25 +25972,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.693 -0.569 u_Axi_CDC/rFifo/cpu_clk - SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C + net (fo=6484, routed) 0.572 -0.691 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_matmul_axi_slave/done_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[4]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.975ns (logic 0.204ns (20.919%) route 0.771ns (79.081%)) + Data Path Delay: 2.040ns (logic 0.175ns (8.577%) route 1.865ns (91.423%)) Logic Levels: 0 - Clock Path Skew: -0.115ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.508ns - Source Clock Delay (SCD): -0.393ns + Clock Path Skew: -0.304ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.682ns + Source Clock Delay (SCD): -0.378ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -32202,12 +26005,12 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.915 -0.393 u_matmul_axi_slave/sys_clk - SLICE_X46Y72 FDRE r u_matmul_axi_slave/done_reg/C + net (fo=9971, routed) 0.930 -0.378 u_matmul_axi_slave/sys_clk + SLICE_X45Y98 FDRE r u_matmul_axi_slave/done_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X46Y72 FDRE (Prop_fdre_C_Q) 0.204 -0.189 r u_matmul_axi_slave/done_reg/Q - net (fo=12, routed) 0.771 0.582 u_cpu/u_csr/interrupt[2] - SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D + SLICE_X45Y98 FDRE (Prop_fdre_C_Q) 0.175 -0.203 r u_matmul_axi_slave/done_reg/Q + net (fo=10, routed) 1.865 1.662 u_cpu/u_csr/interrupt[2] + SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -32219,25 +26022,329 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.755 -0.508 u_cpu/u_csr/cpu_clk - SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C + net (fo=6484, routed) 0.581 -0.682 u_cpu/u_csr/cpu_clk + SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.978ns (logic 0.595ns (30.082%) route 1.383ns (69.918%)) + Logic Levels: 0 + Clock Path Skew: -0.315ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.695ns + Source Clock Delay (SCD): -0.380ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.928 -0.380 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X46Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y95 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.215 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 1.383 1.598 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.568 -0.695 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 3.967ns (logic 1.343ns (33.856%) route 2.624ns (66.144%)) + Logic Levels: 0 + Clock Path Skew: 0.105ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns + Source Clock Delay (SCD): -2.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.343 -1.055 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O + net (fo=1, routed) 2.624 1.569 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.776ns (logic 0.480ns (27.033%) route 1.296ns (72.967%)) + Logic Levels: 0 + Clock Path Skew: -0.341ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.690ns + Source Clock Delay (SCD): -0.349ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.959 -0.349 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.131 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O + net (fo=1, routed) 1.296 1.426 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.573 -0.690 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.724ns (logic 0.482ns (27.964%) route 1.242ns (72.036%)) + Logic Levels: 0 + Clock Path Skew: -0.306ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.691ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X62Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X62Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.097 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O + net (fo=1, routed) 1.242 1.338 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.572 -0.691 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cpu/u_csr/csr_estat_reg[5]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.886ns (logic 0.184ns (20.776%) route 0.702ns (79.224%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.682ns + Source Clock Delay (SCD): -0.456ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.852 -0.456 u_fft_mlkem_axi_slave/sys_clk + SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X96Y110 FDCE (Prop_fdce_C_Q) 0.184 -0.272 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/Q + net (fo=1, routed) 0.702 0.429 u_cpu/u_csr/interrupt[3] + SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.581 -0.682 u_cpu/u_csr/cpu_clk + SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.644ns (logic 0.204ns (31.675%) route 0.440ns (68.325%)) + Logic Levels: 0 + Clock Path Skew: -0.295ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.679ns + Source Clock Delay (SCD): -0.384ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.924 -0.384 u_Axi_CDC/rFifo/sys_clk + SLICE_X62Y94 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y94 FDCE (Prop_fdce_C_Q) 0.204 -0.180 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.440 0.260 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.584 -0.679 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_cdma_matmul_bridge/seq_done_flag_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[3]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.752ns (logic 0.231ns (30.703%) route 0.521ns (69.297%)) + Data Path Delay: 0.671ns (logic 0.231ns (34.431%) route 0.440ns (65.569%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.223ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.610ns - Source Clock Delay (SCD): -0.387ns + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.694ns + Source Clock Delay (SCD): -0.463ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -32252,14 +26359,14 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.921 -0.387 u_cdma_matmul_bridge/sys_clk - SLICE_X61Y63 FDRE r u_cdma_matmul_bridge/seq_done_flag_reg/C + net (fo=9971, routed) 0.845 -0.463 u_cdma_matmul_bridge/sys_clk + SLICE_X71Y113 FDRE r u_cdma_matmul_bridge/seq_done_flag_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y63 FDRE (Prop_fdre_C_Q) 0.175 -0.212 r u_cdma_matmul_bridge/seq_done_flag_reg/Q - net (fo=3, routed) 0.521 0.309 u_snix_axil_cdma_mux_8ch/cdma_matmul_seq_irq - SLICE_X57Y58 LUT5 (Prop_lut5_I4_O) 0.056 0.365 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O - net (fo=1, routed) 0.000 0.365 u_cpu/u_csr/interrupt[1] - SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D + SLICE_X71Y113 FDRE (Prop_fdre_C_Q) 0.175 -0.288 r u_cdma_matmul_bridge/seq_done_flag_reg/Q + net (fo=3, routed) 0.440 0.152 u_snix_axil_cdma_mux_8ch/cdma_matmul_seq_irq + SLICE_X75Y119 LUT5 (Prop_lut5_I4_O) 0.056 0.208 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O + net (fo=1, routed) 0.000 0.208 u_cpu/u_csr/interrupt[1] + SLICE_X75Y119 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -32271,325 +26378,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.652 -0.610 u_cpu/u_csr/cpu_clk - SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.576ns (logic 0.160ns (27.764%) route 0.416ns (72.236%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.160 -0.071 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.416 0.345 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.539 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.577ns (logic 0.175ns (30.321%) route 0.402ns (69.679%)) - Logic Levels: 0 - Clock Path Skew: -0.227ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.347ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.175 -0.172 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.402 0.230 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.688 -0.574 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.550ns (logic 0.160ns (29.072%) route 0.390ns (70.928%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.346ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.962 -0.346 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.160 -0.186 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.390 0.204 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.549ns (logic 0.175ns (31.853%) route 0.374ns (68.147%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.346ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.962 -0.346 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.175 -0.171 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.374 0.203 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.482ns (logic 0.175ns (36.304%) route 0.307ns (63.696%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.346ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.962 -0.346 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.175 -0.171 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.307 0.136 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.363ns (logic 0.175ns (48.223%) route 0.188ns (51.777%)) - Logic Levels: 0 - Clock Path Skew: -0.234ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.465ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.175 -0.056 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.188 0.132 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + net (fo=6484, routed) 0.569 -0.694 u_cpu/u_csr/cpu_clk + SLICE_X75Y119 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.446ns (logic 0.160ns (35.900%) route 0.286ns (64.100%)) + Data Path Delay: 0.573ns (logic 0.184ns (32.112%) route 0.389ns (67.888%)) Logic Levels: 0 - Clock Path Skew: -0.232ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.553ns - Source Clock Delay (SCD): -0.321ns + Clock Path Skew: -0.295ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.679ns + Source Clock Delay (SCD): -0.384ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -32604,12 +26411,12 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.987 -0.321 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C + net (fo=9971, routed) 0.924 -0.384 u_Axi_CDC/rFifo/sys_clk + SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.160 -0.161 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=4, routed) 0.286 0.125 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.184 -0.200 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=4, routed) 0.389 0.189 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -32621,25 +26428,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.709 -0.553 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + net (fo=6484, routed) 0.584 -0.679 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.316ns (logic 0.175ns (55.416%) route 0.141ns (44.584%)) + Data Path Delay: 0.514ns (logic 0.204ns (39.659%) route 0.310ns (60.341%)) Logic Levels: 0 - Clock Path Skew: -0.234ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.465ns - Source Clock Delay (SCD): -0.231ns + Clock Path Skew: -0.295ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.679ns + Source Clock Delay (SCD): -0.384ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -32654,12 +26461,12 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + net (fo=9971, routed) 0.924 -0.384 u_Axi_CDC/rFifo/sys_clk + SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.175 -0.056 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.141 0.085 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.204 -0.180 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.310 0.130 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -32671,8 +26478,2928 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + net (fo=6484, routed) 0.584 -0.679 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.506ns (logic 0.204ns (40.341%) route 0.302ns (59.659%)) + Logic Levels: 0 + Clock Path Skew: -0.295ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.679ns + Source Clock Delay (SCD): -0.384ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.924 -0.384 u_Axi_CDC/rFifo/sys_clk + SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.204 -0.180 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=2, routed) 0.302 0.122 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.584 -0.679 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.514ns (logic 0.175ns (34.048%) route 0.339ns (65.952%)) + Logic Levels: 0 + Clock Path Skew: -0.297ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.695ns + Source Clock Delay (SCD): -0.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.910 -0.398 u_Axi_CDC/arFifo/sys_clk + SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.175 -0.223 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.339 0.116 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.568 -0.695 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_confreg/int_out_or_q2_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cpu/u_csr/csr_estat_reg[2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.557ns (logic 0.175ns (31.425%) route 0.382ns (68.575%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.694ns + Source Clock Delay (SCD): -0.470ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.838 -0.470 u_confreg/sys_clk + SLICE_X78Y141 FDRE r u_confreg/int_out_or_q2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y141 FDRE (Prop_fdre_C_Q) 0.175 -0.295 r u_confreg/int_out_or_q2_reg/Q + net (fo=1, routed) 0.382 0.087 u_cpu/u_csr/interrupt[0] + SLICE_X84Y149 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.569 -0.694 u_cpu/u_csr/cpu_clk + SLICE_X84Y149 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.475ns (logic 0.175ns (36.825%) route 0.300ns (63.175%)) + Logic Levels: 0 + Clock Path Skew: -0.297ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.695ns + Source Clock Delay (SCD): -0.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.910 -0.398 u_Axi_CDC/arFifo/sys_clk + SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.175 -0.223 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.300 0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.568 -0.695 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.465ns (logic 0.160ns (34.376%) route 0.305ns (65.624%)) + Logic Levels: 0 + Clock Path Skew: -0.297ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.695ns + Source Clock Delay (SCD): -0.398ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.910 -0.398 u_Axi_CDC/arFifo/sys_clk + SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.160 -0.238 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.305 0.067 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.568 -0.695 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.505ns (logic 0.184ns (36.469%) route 0.321ns (63.531%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.691ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.840 -0.468 u_Axi_CDC/bFifo/sys_clk + SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.184 -0.284 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.321 0.036 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.572 -0.691 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: sys_clk + To Clock: mlkem_clk + +Max Delay 112 Endpoints +Min Delay 0 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 10.980ns (logic 0.668ns (6.084%) route 10.312ns (93.916%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.301ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.273ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 7.199 8.406 pll_clk.u_rst_mlkem/p_0_in + SLICE_X96Y101 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.555 -2.273 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X96Y101 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 10.561ns (logic 0.668ns (6.325%) route 9.893ns (93.675%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.297ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 6.780 7.987 pll_clk.u_rst_mlkem/p_0_in + SLICE_X92Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.551 -2.277 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.643ns (logic 0.668ns (10.055%) route 5.975ns (89.945%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.294ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 2.863 4.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in + SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.548 -2.280 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C + +Slack: inf + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR + (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.643ns (logic 0.668ns (10.055%) route 5.975ns (89.945%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.294ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns + Source Clock Delay (SCD): -2.574ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] + SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O + net (fo=4121, routed) 2.863 4.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in + SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.548 -2.280 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.143ns (logic 0.612ns (53.534%) route 0.531ns (46.466%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/O + net (fo=1, routed) 0.531 0.756 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[36] + SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.059ns (logic 0.612ns (57.810%) route 0.447ns (42.190%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK + SLICE_X44Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.447 0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] + SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.002ns (logic 0.595ns (59.409%) route 0.407ns (40.591%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.407 0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7] + SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.994ns (logic 0.612ns (61.564%) route 0.382ns (38.436%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y97 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O + net (fo=1, routed) 0.382 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48] + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.982ns (logic 0.612ns (62.344%) route 0.370ns (37.656%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.384ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O + net (fo=1, routed) 0.370 0.597 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0] + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.966ns (logic 0.612ns (63.335%) route 0.354ns (36.665%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.611ns + Source Clock Delay (SCD): -0.380ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/WCLK + SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.232 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O + net (fo=1, routed) 0.354 0.586 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36] + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.963ns (logic 0.491ns (50.975%) route 0.472ns (49.025%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.384ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.107 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O + net (fo=1, routed) 0.472 0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2] + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.957ns (logic 0.595ns (62.185%) route 0.362ns (37.815%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.362 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13] + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.957ns (logic 0.482ns (50.382%) route 0.475ns (49.618%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O + net (fo=1, routed) 0.475 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15] + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.954ns (logic 0.482ns (50.537%) route 0.472ns (49.463%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.095 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/O + net (fo=1, routed) 0.472 0.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[9] + SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.940ns (logic 0.595ns (63.287%) route 0.345ns (36.713%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK + SLICE_X44Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.345 0.551 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1] + SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.935ns (logic 0.612ns (65.444%) route 0.323ns (34.556%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O + net (fo=1, routed) 0.323 0.550 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12] + SLICE_X67Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X67Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.927ns (logic 0.595ns (64.162%) route 0.332ns (35.838%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK + SLICE_X44Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 0.332 0.539 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] + SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.925ns (logic 0.595ns (64.303%) route 0.330ns (35.697%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.615ns + Source Clock Delay (SCD): -0.391ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK + SLICE_X46Y79 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.204 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 0.330 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[7] + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.919ns (logic 0.595ns (64.745%) route 0.324ns (35.255%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X64Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.324 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[7] + SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.908ns (logic 0.612ns (67.424%) route 0.296ns (32.576%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X70Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y98 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O + net (fo=1, routed) 0.296 0.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42] + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.911ns (logic 0.612ns (67.168%) route 0.299ns (32.832%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.615ns + Source Clock Delay (SCD): -0.391ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK + SLICE_X46Y79 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 0.299 0.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6] + SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.889ns (logic 0.482ns (54.189%) route 0.407ns (45.811%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X52Y84 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/O + net (fo=1, routed) 0.407 0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[3] + SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.866ns (logic 0.595ns (68.739%) route 0.271ns (31.261%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK + SLICE_X52Y85 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y85 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.271 0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[13] + SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.858ns (logic 0.480ns (55.963%) route 0.378ns (44.037%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/O + net (fo=1, routed) 0.378 0.471 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[11] + SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.849ns (logic 0.612ns (72.044%) route 0.237ns (27.956%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X64Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/O + net (fo=1, routed) 0.237 0.464 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[6] + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.850ns (logic 0.612ns (72.015%) route 0.238ns (27.985%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/O + net (fo=1, routed) 0.238 0.463 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[6] + SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.849ns (logic 0.480ns (56.510%) route 0.369ns (43.490%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK + SLICE_X44Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/O + net (fo=1, routed) 0.369 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[5] + SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.847ns (logic 0.612ns (72.292%) route 0.235ns (27.708%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK + SLICE_X44Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 0.235 0.457 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[0] + SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.831ns (logic 0.595ns (71.594%) route 0.236ns (28.406%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X52Y84 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/O + net (fo=1, routed) 0.236 0.445 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[1] + SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.826ns (logic 0.595ns (72.067%) route 0.231ns (27.933%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/O + net (fo=1, routed) 0.231 0.438 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[37] + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.823ns (logic 0.485ns (58.931%) route 0.338ns (41.069%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK + SLICE_X44Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/O + net (fo=1, routed) 0.338 0.434 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[4] + SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.816ns (logic 0.485ns (59.415%) route 0.331ns (40.585%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X52Y84 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/O + net (fo=1, routed) 0.331 0.430 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[4] + SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.815ns (logic 0.612ns (75.104%) route 0.203ns (24.896%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.612ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK + SLICE_X52Y85 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y85 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/O + net (fo=1, routed) 0.203 0.430 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[12] + SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.818ns (logic 0.485ns (59.283%) route 0.333ns (40.717%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/O + net (fo=1, routed) 0.333 0.429 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[22] + SLICE_X49Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.803ns (logic 0.612ns (76.218%) route 0.191ns (23.782%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/WCLK + SLICE_X46Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y82 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/O + net (fo=1, routed) 0.191 0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[36] + SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.794ns (logic 0.595ns (74.965%) route 0.199ns (25.035%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.611ns + Source Clock Delay (SCD): -0.381ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK + SLICE_X56Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X56Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/O + net (fo=1, routed) 0.199 0.413 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[49] + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.800ns (logic 0.595ns (74.332%) route 0.205ns (25.668%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.615ns + Source Clock Delay (SCD): -0.390ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK + SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.205 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 0.205 0.410 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[13] + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.794ns (logic 0.491ns (61.813%) route 0.303ns (38.187%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.106 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O + net (fo=1, routed) 0.303 0.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.791ns (logic 0.595ns (75.204%) route 0.196ns (24.796%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.615ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y97 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/O + net (fo=1, routed) 0.196 0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[49] + SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.789ns (logic 0.482ns (61.059%) route 0.307ns (38.941%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.611ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK + SLICE_X52Y85 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y85 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/O + net (fo=1, routed) 0.307 0.404 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[15] + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.783ns (logic 0.595ns (75.959%) route 0.188ns (24.041%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.384ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.211 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/O + net (fo=1, routed) 0.188 0.399 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[1] + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.785ns (logic 0.595ns (75.763%) route 0.190ns (24.237%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK + SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 0.190 0.397 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[31] + SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.777ns (logic 0.491ns (63.166%) route 0.286ns (36.834%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.611ns + Source Clock Delay (SCD): -0.381ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X56Y92 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X56Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.110 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/O + net (fo=1, routed) 0.286 0.396 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[32] + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.787ns (logic 0.485ns (61.631%) route 0.302ns (38.369%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.391ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK + SLICE_X46Y79 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/O + net (fo=1, routed) 0.302 0.396 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[10] + SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.781ns (logic 0.485ns (62.110%) route 0.296ns (37.890%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.390ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK + SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.095 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/O + net (fo=1, routed) 0.296 0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[16] + SLICE_X50Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X50Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.778ns (logic 0.595ns (76.434%) route 0.183ns (23.566%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.615ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/O + net (fo=1, routed) 0.183 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[19] + SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.767ns (logic 0.485ns (63.268%) route 0.282ns (36.732%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X64Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.100 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/O + net (fo=1, routed) 0.282 0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[10] + SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.758ns (logic 0.491ns (64.744%) route 0.267ns (35.256%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.612ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X52Y84 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/O + net (fo=1, routed) 0.267 0.372 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[2] + SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.759ns (logic 0.485ns (63.921%) route 0.274ns (36.079%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.098 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/O + net (fo=1, routed) 0.274 0.372 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[10] + SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X54Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.751ns (logic 0.612ns (81.523%) route 0.139ns (18.477%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.611ns + Source Clock Delay (SCD): -0.381ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK + SLICE_X56Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X56Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.231 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/O + net (fo=1, routed) 0.139 0.370 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[48] + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/C @@ -32691,21 +29418,21 @@ Min Delay 0 Endpoints Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.565ns (logic 0.595ns (38.011%) route 0.970ns (61.989%)) + Data Path Delay: 1.425ns (logic 0.485ns (34.039%) route 0.940ns (65.961%)) Logic Levels: 0 - Clock Path Skew: -0.312ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.232ns + Clock Path Skew: -0.207ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.674ns + Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -32720,13 +29447,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.363 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 0.970 1.333 u_Axi_CDC/wFifo/_zz_ram_port10__0[1] - SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D + SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.018 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/O + net (fo=1, routed) 0.940 0.958 u_Axi_CDC/awFifo/_zz_ram_port10[22] + SLICE_X52Y101 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -32738,25 +29465,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/C + net (fo=9971, routed) 0.589 -0.674 u_Axi_CDC/awFifo/sys_clk + SLICE_X52Y101 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/C Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.442ns (logic 0.612ns (42.441%) route 0.830ns (57.559%)) + Data Path Delay: 1.308ns (logic 0.482ns (36.863%) route 0.826ns (63.137%)) Logic Levels: 0 - Clock Path Skew: -0.317ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.548ns - Source Clock Delay (SCD): -0.231ns + Clock Path Skew: -0.204ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.681ns + Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -32771,13 +29498,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/WCLK - SLICE_X6Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK + net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X6Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.381 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/O - net (fo=1, routed) 0.830 1.211 u_Axi_CDC/wFifo/_zz_ram_port10__0[36] - SLICE_X4Y69 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D + SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.005 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/O + net (fo=1, routed) 0.826 0.830 u_Axi_CDC/arFifo/_zz_ram_port10__1[9] + SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -32789,25 +29516,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.714 -0.548 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y69 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/C + net (fo=9971, routed) 0.582 -0.681 u_Axi_CDC/arFifo/sys_clk + SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/C Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.394ns (logic 0.485ns (34.784%) route 0.909ns (65.216%)) + Data Path Delay: 1.238ns (logic 0.485ns (39.176%) route 0.753ns (60.824%)) Logic Levels: 0 - Clock Path Skew: -0.312ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.232ns + Clock Path Skew: -0.204ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.681ns + Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -32822,13 +29549,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK + net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 0.909 1.162 u_Axi_CDC/wFifo/_zz_ram_port10__0[16] - SLICE_X6Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D + SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.008 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/O + net (fo=1, routed) 0.753 0.761 u_Axi_CDC/arFifo/_zz_ram_port10__1[10] + SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -32840,894 +29567,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X6Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.251ns (logic 0.480ns (38.383%) route 0.771ns (61.617%)) - Logic Levels: 0 - Clock Path Skew: -0.315ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.251 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.771 1.021 u_Axi_CDC/wFifo/_zz_ram_port10__0[23] - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/C - -Slack: inf - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Recovery (Max at Fast Process Corner) - Data Path Delay: 1.198ns (logic 0.231ns (19.278%) route 0.967ns (80.722%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.312ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.541ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.175 -0.054 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.272 0.218 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.056 0.274 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.695 0.969 u_Axi_CDC/awFifo/bufferCC_12/p_0_in - SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - -Slack: inf - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Recovery (Max at Fast Process Corner) - Data Path Delay: 1.198ns (logic 0.231ns (19.278%) route 0.967ns (80.722%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.312ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.541ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.175 -0.054 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.272 0.218 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.056 0.274 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.695 0.969 u_Axi_CDC/awFifo/bufferCC_12/p_0_in - SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.183ns (logic 0.485ns (41.003%) route 0.698ns (58.997%)) - Logic Levels: 0 - Clock Path Skew: -0.316ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.545ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.256 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 0.698 0.954 u_Axi_CDC/wFifo/_zz_ram_port10__0[22] - SLICE_X4Y66 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.717 -0.545 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y66 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.172ns (logic 0.595ns (50.766%) route 0.577ns (49.234%)) - Logic Levels: 0 - Clock Path Skew: -0.313ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.364 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 0.577 0.941 u_Axi_CDC/wFifo/_zz_ram_port10__0[31] - SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.160ns (logic 0.485ns (41.821%) route 0.675ns (58.179%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.256 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/O - net (fo=1, routed) 0.675 0.931 u_Axi_CDC/wFifo/_zz_ram_port10__0[10] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.146ns (logic 0.612ns (53.398%) route 0.534ns (46.602%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.540ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.381 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.534 0.915 u_Axi_CDC/wFifo/_zz_ram_port10__0[30] - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.722 -0.540 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.116ns (logic 0.595ns (53.305%) route 0.521ns (46.695%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.540ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.363 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 0.521 0.884 u_Axi_CDC/wFifo/_zz_ram_port10__0[13] - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.722 -0.540 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.107ns (logic 0.480ns (43.345%) route 0.627ns (56.655%)) - Logic Levels: 0 - Clock Path Skew: -0.315ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.251 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 0.627 0.878 u_Axi_CDC/wFifo/_zz_ram_port10__0[29] - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.202ns (logic 0.612ns (50.922%) route 0.590ns (49.078%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK - SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.260 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/O - net (fo=1, routed) 0.590 0.850 u_Axi_CDC/arFifo/_zz_ram_port10__1[18] - SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/arFifo/sys_clk - SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.188ns (logic 0.595ns (50.069%) route 0.593ns (49.931%)) - Logic Levels: 0 - Clock Path Skew: -0.233ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.341ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK - SLICE_X22Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y58 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.254 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/O - net (fo=1, routed) 0.593 0.847 u_Axi_CDC/awFifo/_zz_ram_port10[19] - SLICE_X22Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk - SLICE_X22Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.021ns (logic 0.595ns (58.252%) route 0.426ns (41.748%)) - Logic Levels: 0 - Clock Path Skew: -0.315ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.366 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/O - net (fo=1, routed) 0.426 0.792 u_Axi_CDC/wFifo/_zz_ram_port10__0[7] - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.128ns (logic 0.480ns (42.561%) route 0.648ns (57.439%)) - Logic Levels: 0 - Clock Path Skew: -0.219ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.571ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK - SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.128 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/O - net (fo=1, routed) 0.648 0.776 u_Axi_CDC/arFifo/_zz_ram_port10__1[23] - SLICE_X14Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.691 -0.571 u_Axi_CDC/arFifo/sys_clk - SLICE_X14Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.005ns (logic 0.480ns (47.778%) route 0.525ns (52.222%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.249 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.525 0.773 u_Axi_CDC/wFifo/_zz_ram_port10__0[35] - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.002ns (logic 0.482ns (48.095%) route 0.520ns (51.905%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.520 0.773 u_Axi_CDC/wFifo/_zz_ram_port10__0[21] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.001ns (logic 0.480ns (47.953%) route 0.521ns (52.047%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.248 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.521 0.769 u_Axi_CDC/wFifo/_zz_ram_port10__0[17] - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.109ns (logic 0.612ns (55.196%) route 0.497ns (44.804%)) - Logic Levels: 0 - Clock Path Skew: -0.233ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.573ns - Source Clock Delay (SCD): -0.340ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.968 -0.340 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK - SLICE_X20Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y60 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.272 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/O - net (fo=1, routed) 0.497 0.769 u_Axi_CDC/arFifo/_zz_ram_port10__1[24] - SLICE_X12Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/arFifo/sys_clk - SLICE_X12Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/C + net (fo=9971, routed) 0.582 -0.681 u_Axi_CDC/arFifo/sys_clk + SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.116ns (logic 0.485ns (43.457%) route 0.631ns (56.543%)) + Data Path Delay: 1.212ns (logic 0.485ns (40.001%) route 0.727ns (59.999%)) Logic Levels: 0 - Clock Path Skew: -0.224ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.576ns - Source Clock Delay (SCD): -0.352ns + Clock Path Skew: -0.150ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.608ns + Source Clock Delay (SCD): -0.458ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -33742,13 +29600,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK - SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK + SLICE_X70Y105 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.133 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/O - net (fo=1, routed) 0.631 0.764 u_Axi_CDC/arFifo/_zz_ram_port10__1[22] - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D + SLICE_X70Y105 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.027 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/O + net (fo=1, routed) 0.727 0.754 u_Axi_CDC/arFifo/_zz_ram_port10__1[22] + SLICE_X47Y95 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -33760,688 +29618,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.987ns (logic 0.612ns (62.028%) route 0.375ns (37.972%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.383 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 0.375 0.757 u_Axi_CDC/wFifo/_zz_ram_port10__0[6] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.973ns (logic 0.612ns (62.874%) route 0.361ns (37.126%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.380 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 0.361 0.741 u_Axi_CDC/wFifo/_zz_ram_port10__0[12] - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.966ns (logic 0.491ns (50.838%) route 0.475ns (49.162%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.259 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 0.475 0.734 u_Axi_CDC/wFifo/_zz_ram_port10__0[14] - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.960ns (logic 0.595ns (62.000%) route 0.365ns (38.000%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.366 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 0.365 0.730 u_Axi_CDC/wFifo/_zz_ram_port10__0[25] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.949ns (logic 0.485ns (51.100%) route 0.464ns (48.900%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.254 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.464 0.718 u_Axi_CDC/wFifo/_zz_ram_port10__0[34] - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.047ns (logic 0.595ns (56.827%) route 0.452ns (43.173%)) - Logic Levels: 0 - Clock Path Skew: -0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.571ns - Source Clock Delay (SCD): -0.340ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.968 -0.340 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK - SLICE_X20Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y60 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.255 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/O - net (fo=1, routed) 0.452 0.707 u_Axi_CDC/arFifo/_zz_ram_port10__1[25] - SLICE_X18Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.691 -0.571 u_Axi_CDC/arFifo/sys_clk - SLICE_X18Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.928ns (logic 0.482ns (51.961%) route 0.446ns (48.039%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.536ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 0.446 0.698 u_Axi_CDC/wFifo/_zz_ram_port10__0[9] - SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.040ns (logic 0.485ns (46.647%) route 0.555ns (53.353%)) - Logic Levels: 0 - Clock Path Skew: -0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.576ns - Source Clock Delay (SCD): -0.345ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y67 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.140 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/O - net (fo=1, routed) 0.555 0.695 u_Axi_CDC/arFifo/_zz_ram_port10__1[46] - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.920ns (logic 0.612ns (66.545%) route 0.308ns (33.455%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.380 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 0.308 0.687 u_Axi_CDC/wFifo/_zz_ram_port10__0[0] - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.025ns (logic 0.612ns (59.711%) route 0.413ns (40.289%)) - Logic Levels: 0 - Clock Path Skew: -0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.573ns - Source Clock Delay (SCD): -0.342ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X22Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y60 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.270 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/O - net (fo=1, routed) 0.413 0.683 u_Axi_CDC/arFifo/_zz_ram_port10__1[12] - SLICE_X21Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/arFifo/sys_clk - SLICE_X21Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.021ns (logic 0.612ns (59.936%) route 0.409ns (40.064%)) - Logic Levels: 0 - Clock Path Skew: -0.233ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.341ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK - SLICE_X22Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y58 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/O - net (fo=1, routed) 0.409 0.680 u_Axi_CDC/awFifo/_zz_ram_port10[18] - SLICE_X22Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk - SLICE_X22Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.026ns (logic 0.482ns (46.999%) route 0.544ns (53.001%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK - SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.130 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/O - net (fo=1, routed) 0.544 0.673 u_Axi_CDC/arFifo/_zz_ram_port10__1[21] - SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/arFifo/sys_clk - SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.019ns (logic 0.595ns (58.363%) route 0.424ns (41.637%)) - Logic Levels: 0 - Clock Path Skew: -0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.576ns - Source Clock Delay (SCD): -0.348ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y67 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.247 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/O - net (fo=1, routed) 0.424 0.671 u_Axi_CDC/awFifo/_zz_ram_port10[31] - SLICE_X23Y67 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y67 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/C + net (fo=9971, routed) 0.654 -0.608 u_Axi_CDC/arFifo/sys_clk + SLICE_X47Y95 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.898ns (logic 0.612ns (68.152%) route 0.286ns (31.848%)) + Data Path Delay: 1.193ns (logic 0.612ns (51.321%) route 0.581ns (48.679%)) Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.537ns - Source Clock Delay (SCD): -0.229ns + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.702ns + Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -34456,13 +29651,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK + net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X88Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.383 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 0.286 0.669 u_Axi_CDC/wFifo/_zz_ram_port10__0[18] - SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D + SLICE_X88Y128 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.138 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/O + net (fo=1, routed) 0.581 0.718 u_Axi_CDC/wFifo/_zz_ram_port10__0[18] + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -34474,25 +29669,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_Axi_CDC/wFifo/sys_clk - SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/C + net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/C Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D + Source: u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.896ns (logic 0.595ns (66.419%) route 0.301ns (33.581%)) + Data Path Delay: 1.185ns (logic 0.612ns (51.630%) route 0.573ns (48.370%)) Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.702ns + Source Clock Delay (SCD): -0.475ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -34507,13 +29702,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + net (fo=6484, routed) 0.833 -0.475 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/WCLK + SLICE_X90Y125 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.366 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 0.301 0.667 u_Axi_CDC/wFifo/_zz_ram_port10__0[19] - SLICE_X3Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D + SLICE_X90Y125 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.137 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/O + net (fo=1, routed) 0.573 0.710 u_Axi_CDC/wFifo/_zz_ram_port10__0[36] + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -34525,229 +29720,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X3Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C + net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/C Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.012ns (logic 0.485ns (47.912%) route 0.527ns (52.088%)) - Logic Levels: 0 - Clock Path Skew: -0.264ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.612ns - Source Clock Delay (SCD): -0.348ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.137 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 0.527 0.664 u_Axi_CDC/arFifo/_zz_ram_port10__1[4] - SLICE_X46Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.650 -0.612 u_Axi_CDC/arFifo/sys_clk - SLICE_X46Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.892ns (logic 0.480ns (53.815%) route 0.412ns (46.185%)) - Logic Levels: 0 - Clock Path Skew: -0.306ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.248 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 0.412 0.660 u_Axi_CDC/wFifo/_zz_ram_port10__0[5] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.880ns (logic 0.612ns (69.559%) route 0.268ns (30.441%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.536ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.383 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 0.268 0.651 u_Axi_CDC/wFifo/_zz_ram_port10__0[24] - SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.879ns (logic 0.482ns (54.834%) route 0.397ns (45.166%)) - Logic Levels: 0 - Clock Path Skew: -0.315ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 0.397 0.650 u_Axi_CDC/wFifo/_zz_ram_port10__0[27] - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.990ns (logic 0.612ns (61.797%) route 0.378ns (38.203%)) + Data Path Delay: 1.173ns (logic 0.612ns (52.170%) route 0.561ns (47.830%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.341ns + Destination Clock Delay (DCD): -0.700ns + Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -34762,13 +29753,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK - SLICE_X22Y59 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X22Y59 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/O - net (fo=1, routed) 0.378 0.649 u_Axi_CDC/awFifo/_zz_ram_port10[12] - SLICE_X24Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D + SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.145 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/O + net (fo=1, routed) 0.561 0.706 u_Axi_CDC/awFifo/_zz_ram_port10[18] + SLICE_X82Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -34780,25 +29771,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk - SLICE_X24Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/C + net (fo=9971, routed) 0.563 -0.700 u_Axi_CDC/awFifo/sys_clk + SLICE_X82Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.981ns (logic 0.612ns (62.415%) route 0.369ns (37.585%)) + Data Path Delay: 1.116ns (logic 0.482ns (43.203%) route 0.634ns (56.797%)) Logic Levels: 0 - Clock Path Skew: -0.229ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.570ns - Source Clock Delay (SCD): -0.341ns + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.695ns + Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -34813,13 +29804,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK - SLICE_X22Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X22Y57 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/O - net (fo=1, routed) 0.369 0.639 u_Axi_CDC/awFifo/_zz_ram_port10[24] - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D + SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.015 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/O + net (fo=1, routed) 0.634 0.648 u_Axi_CDC/awFifo/_zz_ram_port10[21] + SLICE_X81Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -34831,127 +29822,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_Axi_CDC/awFifo/sys_clk - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.866ns (logic 0.485ns (56.026%) route 0.381ns (43.974%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.256 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 0.381 0.636 u_Axi_CDC/wFifo/_zz_ram_port10__0[28] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.867ns (logic 0.491ns (56.612%) route 0.376ns (43.388%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.540ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.259 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 0.376 0.635 u_Axi_CDC/wFifo/_zz_ram_port10__0[2] - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.722 -0.540 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/C + net (fo=9971, routed) 0.568 -0.695 u_Axi_CDC/awFifo/sys_clk + SLICE_X81Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.955ns (logic 0.612ns (64.074%) route 0.343ns (35.926%)) + Data Path Delay: 1.100ns (logic 0.612ns (55.644%) route 0.488ns (44.356%)) Logic Levels: 0 - Clock Path Skew: -0.230ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.338ns + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.698ns + Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -34966,13 +29855,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y57 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.274 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/O - net (fo=1, routed) 0.343 0.617 u_Axi_CDC/awFifo/_zz_ram_port10[6] - SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D + SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.145 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/O + net (fo=1, routed) 0.488 0.633 u_Axi_CDC/awFifo/_zz_ram_port10[6] + SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -34984,25 +29873,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/C + net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk + SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D + Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.947ns (logic 0.595ns (62.805%) route 0.352ns (37.195%)) + Data Path Delay: 1.080ns (logic 0.612ns (56.690%) route 0.468ns (43.310%)) Logic Levels: 0 - Clock Path Skew: -0.232ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.573ns - Source Clock Delay (SCD): -0.341ns + Clock Path Skew: -0.233ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.698ns + Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -35017,13 +29906,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK + net (fo=6484, routed) 0.843 -0.465 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X90Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.254 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/O - net (fo=1, routed) 0.352 0.606 u_Axi_CDC/awFifo/_zz_ram_port10[43] - SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D + SLICE_X90Y115 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.147 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/O + net (fo=1, routed) 0.468 0.614 u_Axi_CDC/awFifo/_zz_ram_port10[0] + SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -35035,25 +29924,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/awFifo/sys_clk - SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/C + net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk + SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/C Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D + Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.953ns (logic 0.612ns (64.216%) route 0.341ns (35.784%)) + Data Path Delay: 1.075ns (logic 0.485ns (45.122%) route 0.590ns (54.878%)) Logic Levels: 0 - Clock Path Skew: -0.229ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.577ns - Source Clock Delay (SCD): -0.348ns + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.702ns + Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -35068,13 +29957,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK + SLICE_X90Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.264 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/O - net (fo=1, routed) 0.341 0.605 u_Axi_CDC/arFifo/_zz_ram_port10__1[0] - SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D + SLICE_X90Y128 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.014 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/O + net (fo=1, routed) 0.590 0.604 u_Axi_CDC/wFifo/_zz_ram_port10__0[16] + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -35086,25 +29975,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.685 -0.577 u_Axi_CDC/arFifo/sys_clk - SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/C + net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/C Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D + Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.833ns (logic 0.491ns (58.937%) route 0.342ns (41.063%)) + Data Path Delay: 1.070ns (logic 0.612ns (57.190%) route 0.458ns (42.810%)) Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.537ns - Source Clock Delay (SCD): -0.229ns + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.696ns + Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -35119,13 +30008,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK + SLICE_X84Y109 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.262 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.342 0.604 u_Axi_CDC/wFifo/_zz_ram_port10__0[8] - SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D + SLICE_X84Y109 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.141 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/O + net (fo=1, routed) 0.458 0.599 u_Axi_CDC/arFifo/_zz_ram_port10__1[24] + SLICE_X80Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -35137,25 +30026,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_Axi_CDC/wFifo/sys_clk - SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/C + net (fo=9971, routed) 0.567 -0.696 u_Axi_CDC/arFifo/sys_clk + SLICE_X80Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D + Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.937ns (logic 0.595ns (63.501%) route 0.342ns (36.499%)) + Data Path Delay: 1.061ns (logic 0.491ns (46.270%) route 0.570ns (53.730%)) Logic Levels: 0 - Clock Path Skew: -0.230ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.338ns + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.698ns + Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -35170,13 +30059,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y57 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.257 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/O - net (fo=1, routed) 0.342 0.599 u_Axi_CDC/awFifo/_zz_ram_port10[7] - SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D + SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.024 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/O + net (fo=1, routed) 0.570 0.594 u_Axi_CDC/awFifo/_zz_ram_port10[8] + SLICE_X82Y111 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -35188,25 +30077,76 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/C + net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk + SLICE_X82Y111 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.048ns (logic 0.595ns (56.753%) route 0.453ns (43.247%)) + Logic Levels: 0 + Clock Path Skew: -0.222ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.699ns + Source Clock Delay (SCD): -0.477ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.118 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.453 0.571 u_Axi_CDC/arFifo/_zz_ram_port10__1[7] + SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/arFifo/sys_clk + SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.914ns (logic 0.612ns (66.980%) route 0.302ns (33.020%)) + Data Path Delay: 1.024ns (logic 0.612ns (59.777%) route 0.412ns (40.223%)) Logic Levels: 0 - Clock Path Skew: -0.232ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.573ns - Source Clock Delay (SCD): -0.341ns + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.680ns + Source Clock Delay (SCD): -0.455ns Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -35221,13 +30161,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK + net (fo=6484, routed) 0.853 -0.455 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/O - net (fo=1, routed) 0.302 0.573 u_Axi_CDC/awFifo/_zz_ram_port10[42] - SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D + SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.157 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/O + net (fo=1, routed) 0.412 0.569 u_Axi_CDC/awFifo/_zz_ram_port10[42] + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -35239,8 +30179,4406 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/awFifo/sys_clk - SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/C + net (fo=9971, routed) 0.583 -0.680 u_Axi_CDC/awFifo/sys_clk + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.025ns (logic 0.595ns (58.034%) route 0.430ns (41.966%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.703ns + Source Clock Delay (SCD): -0.472ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.836 -0.472 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK + SLICE_X88Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y130 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.123 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.430 0.553 u_Axi_CDC/wFifo/_zz_ram_port10__0[1] + SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk + SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.009ns (logic 0.612ns (60.640%) route 0.397ns (39.360%)) + Logic Levels: 0 + Clock Path Skew: -0.157ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.615ns + Source Clock Delay (SCD): -0.458ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK + SLICE_X70Y105 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y105 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.154 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/O + net (fo=1, routed) 0.397 0.551 u_Axi_CDC/arFifo/_zz_ram_port10__1[18] + SLICE_X66Y97 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.647 -0.615 u_Axi_CDC/arFifo/sys_clk + SLICE_X66Y97 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.006ns (logic 0.491ns (48.819%) route 0.515ns (51.181%)) + Logic Levels: 0 + Clock Path Skew: -0.222ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.699ns + Source Clock Delay (SCD): -0.477ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.014 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/O + net (fo=1, routed) 0.515 0.529 u_Axi_CDC/arFifo/_zz_ram_port10__1[8] + SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/arFifo/sys_clk + SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.992ns (logic 0.612ns (61.686%) route 0.380ns (38.314%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.703ns + Source Clock Delay (SCD): -0.472ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.836 -0.472 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK + SLICE_X88Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y130 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.140 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 0.380 0.520 u_Axi_CDC/wFifo/_zz_ram_port10__0[0] + SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk + SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.990ns (logic 0.595ns (60.095%) route 0.395ns (39.905%)) + Logic Levels: 0 + Clock Path Skew: -0.234ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.705ns + Source Clock Delay (SCD): -0.471ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK + SLICE_X88Y131 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y131 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.124 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 0.395 0.519 u_Axi_CDC/wFifo/_zz_ram_port10__0[7] + SLICE_X82Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk + SLICE_X82Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.992ns (logic 0.480ns (48.370%) route 0.512ns (51.630%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.702ns + Source Clock Delay (SCD): -0.474ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X88Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y128 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.006 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/O + net (fo=1, routed) 0.512 0.518 u_Axi_CDC/wFifo/_zz_ram_port10__0[23] + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk + SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.974ns (logic 0.612ns (62.847%) route 0.362ns (37.153%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.683ns + Source Clock Delay (SCD): -0.458ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X72Y104 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X72Y104 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.154 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/O + net (fo=1, routed) 0.362 0.516 u_Axi_CDC/arFifo/_zz_ram_port10__1[42] + SLICE_X71Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.580 -0.683 u_Axi_CDC/arFifo/sys_clk + SLICE_X71Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.981ns (logic 0.595ns (60.677%) route 0.386ns (39.323%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.699ns + Source Clock Delay (SCD): -0.467ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.128 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/O + net (fo=1, routed) 0.386 0.513 u_Axi_CDC/awFifo/_zz_ram_port10[19] + SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/awFifo/sys_clk + SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.972ns (logic 0.482ns (49.575%) route 0.490ns (50.425%)) + Logic Levels: 0 + Clock Path Skew: -0.233ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.698ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.843 -0.465 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X90Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y115 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.017 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/O + net (fo=1, routed) 0.490 0.507 u_Axi_CDC/awFifo/_zz_ram_port10[3] + SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk + SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.973ns (logic 0.485ns (49.868%) route 0.488ns (50.132%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.698ns + Source Clock Delay (SCD): -0.467ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.018 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/O + net (fo=1, routed) 0.488 0.505 u_Axi_CDC/awFifo/_zz_ram_port10[10] + SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk + SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[10]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.968ns (logic 0.480ns (49.581%) route 0.488ns (50.419%)) + Logic Levels: 0 + Clock Path Skew: -0.233ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.700ns + Source Clock Delay (SCD): -0.467ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.013 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC_D1/O + net (fo=1, routed) 0.488 0.501 u_Axi_CDC/awFifo/_zz_ram_port10[11] + SLICE_X82Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.563 -0.700 u_Axi_CDC/awFifo/sys_clk + SLICE_X82Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[11]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.957ns (logic 0.595ns (62.152%) route 0.362ns (37.848%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.691ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.843 -0.465 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X90Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y115 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.130 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/O + net (fo=1, routed) 0.362 0.492 u_Axi_CDC/awFifo/_zz_ram_port10[1] + SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.572 -0.691 u_Axi_CDC/awFifo/sys_clk + SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.877ns (logic 0.612ns (69.814%) route 0.265ns (30.186%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.921 -0.387 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X70Y99 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y99 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.225 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/O + net (fo=1, routed) 0.265 0.489 u_Axi_CDC/arFifo/_zz_ram_port10__1[48] + SLICE_X71Y99 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.646 -0.616 u_Axi_CDC/arFifo/sys_clk + SLICE_X71Y99 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.966ns (logic 0.612ns (63.379%) route 0.354ns (36.621%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.699ns + Source Clock Delay (SCD): -0.476ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.832 -0.476 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK + SLICE_X84Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y115 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.136 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/O + net (fo=1, routed) 0.354 0.489 u_Axi_CDC/awFifo/_zz_ram_port10[12] + SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/awFifo/sys_clk + SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.961ns (logic 0.612ns (63.711%) route 0.349ns (36.289%)) + Logic Levels: 0 + Clock Path Skew: -0.234ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.705ns + Source Clock Delay (SCD): -0.471ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK + SLICE_X90Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y128 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.141 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 0.349 0.489 u_Axi_CDC/wFifo/_zz_ram_port10__0[12] + SLICE_X83Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk + SLICE_X83Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.938ns (logic 0.612ns (65.272%) route 0.326ns (34.728%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.677ns + Source Clock Delay (SCD): -0.451ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.857 -0.451 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X60Y100 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X60Y100 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.161 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/O + net (fo=1, routed) 0.326 0.486 u_Axi_CDC/awFifo/_zz_ram_port10[30] + SLICE_X59Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.586 -0.677 u_Axi_CDC/awFifo/sys_clk + SLICE_X59Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.957ns (logic 0.480ns (50.151%) route 0.477ns (49.849%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.696ns + Source Clock Delay (SCD): -0.471ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK + SLICE_X84Y109 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y109 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.009 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/O + net (fo=1, routed) 0.477 0.486 u_Axi_CDC/arFifo/_zz_ram_port10__1[29] + SLICE_X80Y107 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.567 -0.696 u_Axi_CDC/arFifo/sys_clk + SLICE_X80Y107 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.954ns (logic 0.612ns (64.150%) route 0.342ns (35.850%)) + Logic Levels: 0 + Clock Path Skew: -0.234ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.703ns + Source Clock Delay (SCD): -0.469ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK + SLICE_X90Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y130 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.143 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.342 0.485 u_Axi_CDC/wFifo/_zz_ram_port10__0[24] + SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk + SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.934ns (logic 0.595ns (63.705%) route 0.339ns (36.295%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.680ns + Source Clock Delay (SCD): -0.455ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.853 -0.455 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.140 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/O + net (fo=1, routed) 0.339 0.479 u_Axi_CDC/awFifo/_zz_ram_port10[43] + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.583 -0.680 u_Axi_CDC/awFifo/sys_clk + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.957ns (logic 0.612ns (63.965%) route 0.345ns (36.035%)) + Logic Levels: 0 + Clock Path Skew: -0.218ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.697ns + Source Clock Delay (SCD): -0.479ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.829 -0.479 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X84Y118 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y118 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.133 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/O + net (fo=1, routed) 0.345 0.478 u_Axi_CDC/arFifo/_zz_ram_port10__1[0] + SLICE_X85Y110 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.566 -0.697 u_Axi_CDC/arFifo/sys_clk + SLICE_X85Y110 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[26]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.939ns (logic 0.491ns (52.288%) route 0.448ns (47.712%)) + Logic Levels: 0 + Clock Path Skew: -0.236ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.705ns + Source Clock Delay (SCD): -0.469ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK + SLICE_X90Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y130 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.022 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/O + net (fo=1, routed) 0.448 0.470 u_Axi_CDC/wFifo/_zz_ram_port10__0[26] + SLICE_X82Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk + SLICE_X82Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[26]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.918ns (logic 0.595ns (64.781%) route 0.323ns (35.219%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.677ns + Source Clock Delay (SCD): -0.451ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.857 -0.451 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X60Y100 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X60Y100 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.144 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/O + net (fo=1, routed) 0.323 0.467 u_Axi_CDC/awFifo/_zz_ram_port10[31] + SLICE_X59Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.586 -0.677 u_Axi_CDC/awFifo/sys_clk + SLICE_X59Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.935ns (logic 0.595ns (63.627%) route 0.340ns (36.373%)) + Logic Levels: 0 + Clock Path Skew: -0.234ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.705ns + Source Clock Delay (SCD): -0.471ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK + SLICE_X90Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y128 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.124 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 0.340 0.464 u_Axi_CDC/wFifo/_zz_ram_port10__0[13] + SLICE_X85Y128 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk + SLICE_X85Y128 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.850ns (logic 0.595ns (69.961%) route 0.255ns (30.039%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.921 -0.387 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X70Y99 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y99 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.208 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/O + net (fo=1, routed) 0.255 0.463 u_Axi_CDC/arFifo/_zz_ram_port10__1[49] + SLICE_X71Y98 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.646 -0.616 u_Axi_CDC/arFifo/sys_clk + SLICE_X71Y98 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.909ns (logic 0.480ns (52.817%) route 0.429ns (47.183%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.677ns + Source Clock Delay (SCD): -0.451ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.857 -0.451 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X60Y100 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X60Y100 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.029 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/O + net (fo=1, routed) 0.429 0.458 u_Axi_CDC/awFifo/_zz_ram_port10[35] + SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.586 -0.677 u_Axi_CDC/awFifo/sys_clk + SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.900ns (logic 0.491ns (54.536%) route 0.409ns (45.464%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.683ns + Source Clock Delay (SCD): -0.458ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X70Y103 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y103 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.033 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/O + net (fo=1, routed) 0.409 0.442 u_Axi_CDC/arFifo/_zz_ram_port10__1[32] + SLICE_X71Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.580 -0.683 u_Axi_CDC/arFifo/sys_clk + SLICE_X71Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.916ns (logic 0.491ns (53.631%) route 0.425ns (46.369%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.700ns + Source Clock Delay (SCD): -0.476ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.832 -0.476 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK + SLICE_X84Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y115 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.015 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/O + net (fo=1, routed) 0.425 0.439 u_Axi_CDC/awFifo/_zz_ram_port10[14] + SLICE_X82Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.563 -0.700 u_Axi_CDC/awFifo/sys_clk + SLICE_X82Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[14]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[40]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.896ns (logic 0.485ns (54.133%) route 0.411ns (45.867%)) + Logic Levels: 0 + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.457ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.851 -0.457 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y100 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y100 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.028 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/O + net (fo=1, routed) 0.411 0.439 u_Axi_CDC/arFifo/_zz_ram_port10__1[40] + SLICE_X71Y99 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[40]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.646 -0.616 u_Axi_CDC/arFifo/sys_clk + SLICE_X71Y99 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[40]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.826ns (logic 0.485ns (58.744%) route 0.341ns (41.256%)) + Logic Levels: 0 + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.616ns + Source Clock Delay (SCD): -0.387ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.921 -0.387 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X70Y99 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y99 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.098 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/O + net (fo=1, routed) 0.341 0.438 u_Axi_CDC/arFifo/_zz_ram_port10__1[52] + SLICE_X71Y98 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.646 -0.616 u_Axi_CDC/arFifo/sys_clk + SLICE_X71Y98 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.908ns (logic 0.612ns (67.416%) route 0.296ns (32.584%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.702ns + Source Clock Delay (SCD): -0.471ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK + SLICE_X88Y131 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y131 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.141 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 0.296 0.437 u_Axi_CDC/wFifo/_zz_ram_port10__0[6] + SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk + SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.905ns (logic 0.491ns (54.225%) route 0.414ns (45.775%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.696ns + Source Clock Delay (SCD): -0.471ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK + SLICE_X84Y109 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y109 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.020 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/O + net (fo=1, routed) 0.414 0.434 u_Axi_CDC/arFifo/_zz_ram_port10__1[26] + SLICE_X80Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.567 -0.696 u_Axi_CDC/arFifo/sys_clk + SLICE_X80Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/C + +Slack: inf + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Fast Process Corner) + Data Path Delay: 0.896ns (logic 0.260ns (29.032%) route 0.636ns (70.968%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.693ns + Source Clock Delay (SCD): -0.462ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.846 -0.462 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.204 -0.258 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.241 -0.017 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.056 0.039 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.394 0.433 u_Axi_CDC/awFifo/bufferCC_12/p_0_in + SLICE_X92Y123 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C + +Slack: inf + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Fast Process Corner) + Data Path Delay: 0.896ns (logic 0.260ns (29.032%) route 0.636ns (70.968%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.693ns + Source Clock Delay (SCD): -0.462ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.846 -0.462 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.204 -0.258 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.241 -0.017 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.056 0.039 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.394 0.433 u_Axi_CDC/awFifo/bufferCC_12/p_0_in + SLICE_X92Y123 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.887ns (logic 0.612ns (68.980%) route 0.275ns (31.020%)) + Logic Levels: 0 + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.683ns + Source Clock Delay (SCD): -0.458ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X70Y103 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y103 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.154 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/O + net (fo=1, routed) 0.275 0.429 u_Axi_CDC/arFifo/_zz_ram_port10__1[30] + SLICE_X68Y103 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.580 -0.683 u_Axi_CDC/arFifo/sys_clk + SLICE_X68Y103 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.801ns (logic 0.612ns (76.427%) route 0.189ns (23.573%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.608ns + Source Clock Delay (SCD): -0.381ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.927 -0.381 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK + SLICE_X60Y98 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X60Y98 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.231 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/O + net (fo=1, routed) 0.189 0.420 u_Axi_CDC/awFifo/_zz_ram_port10[48] + SLICE_X57Y98 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.654 -0.608 u_Axi_CDC/awFifo/sys_clk + SLICE_X57Y98 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: mlkem_clk + To Clock: sys_clk + +Max Delay 61 Endpoints +Min Delay 0 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 5.746ns (logic 0.642ns (11.174%) route 5.104ns (88.826%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.546ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.123ns + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 2.674 3.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1 + SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.705 -2.123 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C + +Slack: inf + Source: pll_clk.u_rst_mlkem/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 5.746ns (logic 0.642ns (11.174%) route 5.104ns (88.826%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.546ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.123ns + Source Clock Delay (SCD): -2.670ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk + SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q + net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] + SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O + net (fo=1066, routed) 2.674 3.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1 + SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.705 -2.123 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.364ns (logic 0.612ns (44.884%) route 0.752ns (55.116%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O + net (fo=1, routed) 0.752 0.977 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.284ns (logic 0.612ns (47.657%) route 0.672ns (52.343%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 0.672 0.895 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.195ns (logic 0.595ns (49.811%) route 0.600ns (50.189%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 0.600 0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.183ns (logic 0.595ns (50.304%) route 0.588ns (49.696%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 0.588 0.797 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.169ns (logic 0.612ns (52.356%) route 0.557ns (47.644%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.612ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O + net (fo=1, routed) 0.557 0.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.167ns (logic 0.612ns (52.454%) route 0.555ns (47.546%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 0.555 0.779 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.166ns (logic 0.480ns (41.172%) route 0.686ns (58.828%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.092 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O + net (fo=1, routed) 0.686 0.778 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.160ns (logic 0.612ns (52.737%) route 0.548ns (47.263%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.548 0.771 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.139ns (logic 0.612ns (53.734%) route 0.527ns (46.266%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 0.527 0.750 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.128ns (logic 0.595ns (52.742%) route 0.533ns (47.258%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 0.533 0.739 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.122ns (logic 0.595ns (53.042%) route 0.527ns (46.958%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O + net (fo=1, routed) 0.527 0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.103ns (logic 0.482ns (43.685%) route 0.621ns (56.315%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O + net (fo=1, routed) 0.621 0.714 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.093ns (logic 0.485ns (44.377%) route 0.608ns (55.623%)) + Logic Levels: 0 + Clock Path Skew: -0.222ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O + net (fo=1, routed) 0.608 0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10] + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.073ns (logic 0.595ns (55.460%) route 0.478ns (44.540%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.478 0.684 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.071ns (logic 0.595ns (55.545%) route 0.476ns (44.455%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 0.476 0.682 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.064ns (logic 0.485ns (45.566%) route 0.579ns (54.434%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O + net (fo=1, routed) 0.579 0.675 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.051ns (logic 0.485ns (46.153%) route 0.566ns (53.847%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O + net (fo=1, routed) 0.566 0.662 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.028ns (logic 0.485ns (47.163%) route 0.543ns (52.837%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O + net (fo=1, routed) 0.543 0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.026ns (logic 0.482ns (46.972%) route 0.544ns (53.028%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O + net (fo=1, routed) 0.544 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.007ns (logic 0.491ns (48.781%) route 0.516ns (51.219%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.103 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O + net (fo=1, routed) 0.516 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.001ns (logic 0.485ns (48.445%) route 0.516ns (51.555%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O + net (fo=1, routed) 0.516 0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.998ns (logic 0.480ns (48.113%) route 0.518ns (51.887%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O + net (fo=1, routed) 0.518 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.998ns (logic 0.491ns (49.223%) route 0.507ns (50.777%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O + net (fo=1, routed) 0.507 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.994ns (logic 0.482ns (48.479%) route 0.512ns (51.521%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O + net (fo=1, routed) 0.512 0.605 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27] + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.990ns (logic 0.480ns (48.485%) route 0.510ns (51.515%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O + net (fo=1, routed) 0.510 0.601 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.988ns (logic 0.491ns (49.720%) route 0.497ns (50.280%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.612ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/O + net (fo=1, routed) 0.497 0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[14] + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.982ns (logic 0.482ns (49.063%) route 0.500ns (50.937%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O + net (fo=1, routed) 0.500 0.594 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.976ns (logic 0.491ns (50.291%) route 0.485ns (49.709%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.612ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O + net (fo=1, routed) 0.485 0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.973ns (logic 0.480ns (49.328%) route 0.493ns (50.672%)) + Logic Levels: 0 + Clock Path Skew: -0.223ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.612ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O + net (fo=1, routed) 0.493 0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.967ns (logic 0.491ns (50.782%) route 0.476ns (49.218%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O + net (fo=1, routed) 0.476 0.578 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.954ns (logic 0.482ns (50.541%) route 0.472ns (49.459%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O + net (fo=1, routed) 0.472 0.564 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.937ns (logic 0.480ns (51.206%) route 0.457ns (48.794%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.610ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O + net (fo=1, routed) 0.457 0.548 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.858ns (logic 0.595ns (69.330%) route 0.263ns (30.670%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O + net (fo=1, routed) 0.263 0.472 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] + SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.855ns (logic 0.612ns (71.580%) route 0.243ns (28.420%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O + net (fo=1, routed) 0.243 0.469 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] + SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.817ns (logic 0.480ns (58.732%) route 0.337ns (41.268%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O + net (fo=1, routed) 0.337 0.431 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.790ns (logic 0.482ns (60.993%) route 0.308ns (39.007%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O + net (fo=1, routed) 0.308 0.404 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] + SLICE_X65Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X65Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.750ns (logic 0.485ns (64.709%) route 0.265ns (35.291%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O + net (fo=1, routed) 0.265 0.363 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.695ns (logic 0.491ns (70.608%) route 0.204ns (29.392%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O + net (fo=1, routed) 0.204 0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.694ns (logic 0.491ns (70.730%) route 0.203ns (29.270%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.614ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O + net (fo=1, routed) 0.203 0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] + SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.686ns (logic 0.482ns (70.214%) route 0.204ns (29.786%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.613ns + Source Clock Delay (SCD): -0.386ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O + net (fo=1, routed) 0.204 0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.554ns (logic 0.485ns (87.546%) route 0.069ns (12.454%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.609ns + Source Clock Delay (SCD): -0.381ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK + SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y90 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.104 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O + net (fo=1, routed) 0.069 0.173 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] + SLICE_X53Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk + SLICE_X53Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.489ns (logic 0.175ns (35.822%) route 0.314ns (64.178%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.617ns + Source Clock Delay (SCD): -0.389ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.175 -0.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.314 0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.475ns (logic 0.175ns (36.832%) route 0.300ns (63.168%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.612ns + Source Clock Delay (SCD): -0.385ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.175 -0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.300 0.090 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[1] + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.544ns (logic 0.175ns (32.186%) route 0.369ns (67.814%)) + Logic Levels: 0 + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.682ns + Source Clock Delay (SCD): -0.455ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.853 -0.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X93Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X93Y102 FDCE (Prop_fdce_C_Q) 0.175 -0.280 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q + net (fo=2, routed) 0.369 0.089 u_fft_mlkem_axi_slave/mlkem_intr_m + SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.581 -0.682 u_fft_mlkem_axi_slave/sys_clk + SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.458ns (logic 0.175ns (38.242%) route 0.283ns (61.758%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.611ns + Source Clock Delay (SCD): -0.381ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk + SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.175 -0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.283 0.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.438ns (logic 0.204ns (46.570%) route 0.234ns (53.430%)) + Logic Levels: 0 + Clock Path Skew: -0.233ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.621ns + Source Clock Delay (SCD): -0.388ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X72Y96 FDCE (Prop_fdce_C_Q) 0.204 -0.184 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.234 0.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.422ns (logic 0.160ns (37.932%) route 0.262ns (62.068%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.618ns + Source Clock Delay (SCD): -0.390ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.160 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.262 0.032 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.410ns (logic 0.175ns (42.699%) route 0.235ns (57.301%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.618ns + Source Clock Delay (SCD): -0.390ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.175 -0.215 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.235 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[3] + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C @@ -35266,10 +34604,10 @@ Slack: inf Path Type: Max at Fast Process Corner Data Path Delay: 1.519ns (logic 0.029ns (1.909%) route 1.490ns (98.091%)) Logic Levels: 1 (BUFG=1) - Clock Uncertainty: 0.169ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.225ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.075ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.110ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -35304,6 +34642,174 @@ Min Delay 0 Endpoints Max Delay Paths -------------------------------------------------------------------------------------- +Slack: inf + Source: u_axi_dvi/DVI_SQU_DIR_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[0] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 15.825ns (logic 6.208ns (39.226%) route 9.618ns (60.774%)) + Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_axi_dvi/sys_clk + SLICE_X42Y81 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.989 r u_axi_dvi/DVI_SQU_DIR_reg[0]/Q + net (fo=5, routed) 1.348 -0.641 u_axi_dvi/DVI_SQU_DIR_reg_n_0_[0] + SLICE_X42Y84 LUT2 (Prop_lut2_I0_O) 0.124 -0.517 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/O + net (fo=1, routed) 0.000 -0.517 u_axi_dvi/video_red_OBUF[2]_inst_i_264_n_0 + SLICE_X42Y84 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 -0.004 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/CO[3] + net (fo=1, routed) 0.000 -0.004 u_axi_dvi/video_red_OBUF[2]_inst_i_225_n_0 + SLICE_X42Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 0.113 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CO[3] + net (fo=1, routed) 0.000 0.113 u_axi_dvi/video_red_OBUF[2]_inst_i_165_n_0 + SLICE_X42Y86 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 0.436 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/O[1] + net (fo=1, routed) 1.222 1.658 u_axi_dvi/video_red_OBUF[2]_inst_i_96_n_6 + SLICE_X42Y82 LUT2 (Prop_lut2_I1_O) 0.306 1.964 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/O + net (fo=1, routed) 0.000 1.964 u_axi_dvi/video_red_OBUF[2]_inst_i_38_n_0 + SLICE_X42Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 2.497 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/CO[3] + net (fo=1, routed) 0.000 2.497 u_axi_dvi/video_red_OBUF[2]_inst_i_7_n_0 + SLICE_X42Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 2.614 f u_axi_dvi/video_red_OBUF[2]_inst_i_2/CO[3] + net (fo=1, routed) 1.354 3.969 u_axi_dvi/video_red_OBUF[2]_inst_i_2_n_0 + SLICE_X41Y85 LUT5 (Prop_lut5_I0_O) 0.124 4.093 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 5.693 9.786 video_red_OBUF[0] + K23 OBUF (Prop_obuf_I_O) 3.533 13.319 r video_red_OBUF[0]_inst/O + net (fo=0) 0.000 13.319 video_red[0] + K23 r video_red[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/DVI_SQU_DIR_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[1] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 15.712ns (logic 6.235ns (39.686%) route 9.476ns (60.314%)) + Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_axi_dvi/sys_clk + SLICE_X42Y81 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.989 r u_axi_dvi/DVI_SQU_DIR_reg[0]/Q + net (fo=5, routed) 1.348 -0.641 u_axi_dvi/DVI_SQU_DIR_reg_n_0_[0] + SLICE_X42Y84 LUT2 (Prop_lut2_I0_O) 0.124 -0.517 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/O + net (fo=1, routed) 0.000 -0.517 u_axi_dvi/video_red_OBUF[2]_inst_i_264_n_0 + SLICE_X42Y84 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 -0.004 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/CO[3] + net (fo=1, routed) 0.000 -0.004 u_axi_dvi/video_red_OBUF[2]_inst_i_225_n_0 + SLICE_X42Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 0.113 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CO[3] + net (fo=1, routed) 0.000 0.113 u_axi_dvi/video_red_OBUF[2]_inst_i_165_n_0 + SLICE_X42Y86 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 0.436 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/O[1] + net (fo=1, routed) 1.222 1.658 u_axi_dvi/video_red_OBUF[2]_inst_i_96_n_6 + SLICE_X42Y82 LUT2 (Prop_lut2_I1_O) 0.306 1.964 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/O + net (fo=1, routed) 0.000 1.964 u_axi_dvi/video_red_OBUF[2]_inst_i_38_n_0 + SLICE_X42Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 2.497 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/CO[3] + net (fo=1, routed) 0.000 2.497 u_axi_dvi/video_red_OBUF[2]_inst_i_7_n_0 + SLICE_X42Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 2.614 f u_axi_dvi/video_red_OBUF[2]_inst_i_2/CO[3] + net (fo=1, routed) 1.354 3.969 u_axi_dvi/video_red_OBUF[2]_inst_i_2_n_0 + SLICE_X41Y85 LUT5 (Prop_lut5_I0_O) 0.124 4.093 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 5.552 9.645 video_red_OBUF[0] + F24 OBUF (Prop_obuf_I_O) 3.560 13.205 r video_red_OBUF[1]_inst/O + net (fo=0) 0.000 13.205 video_red[1] + F24 r video_red[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/DVI_SQU_DIR_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 15.445ns (logic 6.262ns (40.541%) route 9.183ns (59.459%)) + Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_axi_dvi/sys_clk + SLICE_X42Y81 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.989 r u_axi_dvi/DVI_SQU_DIR_reg[0]/Q + net (fo=5, routed) 1.348 -0.641 u_axi_dvi/DVI_SQU_DIR_reg_n_0_[0] + SLICE_X42Y84 LUT2 (Prop_lut2_I0_O) 0.124 -0.517 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/O + net (fo=1, routed) 0.000 -0.517 u_axi_dvi/video_red_OBUF[2]_inst_i_264_n_0 + SLICE_X42Y84 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 -0.004 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/CO[3] + net (fo=1, routed) 0.000 -0.004 u_axi_dvi/video_red_OBUF[2]_inst_i_225_n_0 + SLICE_X42Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 0.113 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CO[3] + net (fo=1, routed) 0.000 0.113 u_axi_dvi/video_red_OBUF[2]_inst_i_165_n_0 + SLICE_X42Y86 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 0.436 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/O[1] + net (fo=1, routed) 1.222 1.658 u_axi_dvi/video_red_OBUF[2]_inst_i_96_n_6 + SLICE_X42Y82 LUT2 (Prop_lut2_I1_O) 0.306 1.964 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/O + net (fo=1, routed) 0.000 1.964 u_axi_dvi/video_red_OBUF[2]_inst_i_38_n_0 + SLICE_X42Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 2.497 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/CO[3] + net (fo=1, routed) 0.000 2.497 u_axi_dvi/video_red_OBUF[2]_inst_i_7_n_0 + SLICE_X42Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 2.614 f u_axi_dvi/video_red_OBUF[2]_inst_i_2/CO[3] + net (fo=1, routed) 1.354 3.969 u_axi_dvi/video_red_OBUF[2]_inst_i_2_n_0 + SLICE_X41Y85 LUT5 (Prop_lut5_I0_O) 0.124 4.093 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 5.259 9.352 video_red_OBUF[0] + E26 OBUF (Prop_obuf_I_O) 3.587 12.938 r video_red_OBUF[2]_inst/O + net (fo=0) 0.000 12.938 video_red[2] + E26 r video_red[2] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -35313,10 +34819,10 @@ Slack: inf Path Type: Max at Slow Process Corner Data Path Delay: 8.589ns (logic 3.629ns (42.252%) route 4.960ns (57.748%)) Logic Levels: 2 (BUFG=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -35330,190 +34836,25 @@ Slack: inf -8.991 3.725 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 5.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 5.658 f pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 3.123 8.781 video_clk_OBUF + net (fo=9971, routed) 3.123 8.781 video_clk_OBUF H22 OBUF (Prop_obuf_I_O) 3.533 12.314 f video_clk_OBUF_inst/O net (fo=0) 0.000 12.314 video_clk H22 f video_clk (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_axi_dvi/DVI_RECT_L_W_reg[22]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[0] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 14.637ns (logic 5.878ns (40.155%) route 8.759ns (59.845%)) - Logic Levels: 9 (CARRY4=4 LUT2=2 LUT4=1 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.941 -2.401 u_axi_dvi/sys_clk - SLICE_X11Y83 FDRE r u_axi_dvi/DVI_RECT_L_W_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X11Y83 FDRE (Prop_fdre_C_Q) 0.456 -1.945 r u_axi_dvi/DVI_RECT_L_W_reg[22]/Q - net (fo=3, routed) 1.109 -0.836 u_axi_dvi/p_0_in6_in[6] - SLICE_X10Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.712 r u_axi_dvi/video_red_OBUF[2]_inst_i_271/O - net (fo=1, routed) 0.000 -0.712 u_axi_dvi/video_red_OBUF[2]_inst_i_271_n_0 - SLICE_X10Y83 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.380 -0.332 r u_axi_dvi/video_red_OBUF[2]_inst_i_239/CO[3] - net (fo=1, routed) 0.000 -0.332 u_axi_dvi/video_red_OBUF[2]_inst_i_239_n_0 - SLICE_X10Y84 CARRY4 (Prop_carry4_CI_O[3]) - 0.315 -0.017 r u_axi_dvi/video_red_OBUF[2]_inst_i_200/O[3] - net (fo=1, routed) 0.864 0.847 u_axi_dvi/video_red_OBUF[2]_inst_i_200_n_4 - SLICE_X11Y84 LUT2 (Prop_lut2_I1_O) 0.307 1.154 r u_axi_dvi/video_red_OBUF[2]_inst_i_132/O - net (fo=1, routed) 0.000 1.154 u_axi_dvi/video_red_OBUF[2]_inst_i_132_n_0 - SLICE_X11Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.401 1.555 r u_axi_dvi/video_red_OBUF[2]_inst_i_67/CO[3] - net (fo=1, routed) 0.000 1.555 u_axi_dvi/video_red_OBUF[2]_inst_i_67_n_0 - SLICE_X11Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.669 f u_axi_dvi/video_red_OBUF[2]_inst_i_31/CO[3] - net (fo=1, routed) 1.273 2.942 u_axi_dvi/video_red_OBUF[2]_inst_i_31_n_0 - SLICE_X16Y85 LUT4 (Prop_lut4_I0_O) 0.124 3.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O - net (fo=1, routed) 0.670 3.736 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I4_O) 0.124 3.860 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 4.844 8.704 video_red_OBUF[0] - K23 OBUF (Prop_obuf_I_O) 3.533 12.236 r video_red_OBUF[0]_inst/O - net (fo=0) 0.000 12.236 video_red[0] - K23 r video_red[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/DVI_RECT_L_W_reg[22]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[1] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 14.524ns (logic 5.905ns (40.660%) route 8.618ns (59.340%)) - Logic Levels: 9 (CARRY4=4 LUT2=2 LUT4=1 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.941 -2.401 u_axi_dvi/sys_clk - SLICE_X11Y83 FDRE r u_axi_dvi/DVI_RECT_L_W_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X11Y83 FDRE (Prop_fdre_C_Q) 0.456 -1.945 r u_axi_dvi/DVI_RECT_L_W_reg[22]/Q - net (fo=3, routed) 1.109 -0.836 u_axi_dvi/p_0_in6_in[6] - SLICE_X10Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.712 r u_axi_dvi/video_red_OBUF[2]_inst_i_271/O - net (fo=1, routed) 0.000 -0.712 u_axi_dvi/video_red_OBUF[2]_inst_i_271_n_0 - SLICE_X10Y83 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.380 -0.332 r u_axi_dvi/video_red_OBUF[2]_inst_i_239/CO[3] - net (fo=1, routed) 0.000 -0.332 u_axi_dvi/video_red_OBUF[2]_inst_i_239_n_0 - SLICE_X10Y84 CARRY4 (Prop_carry4_CI_O[3]) - 0.315 -0.017 r u_axi_dvi/video_red_OBUF[2]_inst_i_200/O[3] - net (fo=1, routed) 0.864 0.847 u_axi_dvi/video_red_OBUF[2]_inst_i_200_n_4 - SLICE_X11Y84 LUT2 (Prop_lut2_I1_O) 0.307 1.154 r u_axi_dvi/video_red_OBUF[2]_inst_i_132/O - net (fo=1, routed) 0.000 1.154 u_axi_dvi/video_red_OBUF[2]_inst_i_132_n_0 - SLICE_X11Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.401 1.555 r u_axi_dvi/video_red_OBUF[2]_inst_i_67/CO[3] - net (fo=1, routed) 0.000 1.555 u_axi_dvi/video_red_OBUF[2]_inst_i_67_n_0 - SLICE_X11Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.669 f u_axi_dvi/video_red_OBUF[2]_inst_i_31/CO[3] - net (fo=1, routed) 1.273 2.942 u_axi_dvi/video_red_OBUF[2]_inst_i_31_n_0 - SLICE_X16Y85 LUT4 (Prop_lut4_I0_O) 0.124 3.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O - net (fo=1, routed) 0.670 3.736 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I4_O) 0.124 3.860 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 4.703 8.563 video_red_OBUF[0] - F24 OBUF (Prop_obuf_I_O) 3.560 12.123 r video_red_OBUF[1]_inst/O - net (fo=0) 0.000 12.123 video_red[1] - F24 r video_red[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/DVI_RECT_L_W_reg[22]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[2] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 14.257ns (logic 5.932ns (41.605%) route 8.325ns (58.395%)) - Logic Levels: 9 (CARRY4=4 LUT2=2 LUT4=1 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.941 -2.401 u_axi_dvi/sys_clk - SLICE_X11Y83 FDRE r u_axi_dvi/DVI_RECT_L_W_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X11Y83 FDRE (Prop_fdre_C_Q) 0.456 -1.945 r u_axi_dvi/DVI_RECT_L_W_reg[22]/Q - net (fo=3, routed) 1.109 -0.836 u_axi_dvi/p_0_in6_in[6] - SLICE_X10Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.712 r u_axi_dvi/video_red_OBUF[2]_inst_i_271/O - net (fo=1, routed) 0.000 -0.712 u_axi_dvi/video_red_OBUF[2]_inst_i_271_n_0 - SLICE_X10Y83 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.380 -0.332 r u_axi_dvi/video_red_OBUF[2]_inst_i_239/CO[3] - net (fo=1, routed) 0.000 -0.332 u_axi_dvi/video_red_OBUF[2]_inst_i_239_n_0 - SLICE_X10Y84 CARRY4 (Prop_carry4_CI_O[3]) - 0.315 -0.017 r u_axi_dvi/video_red_OBUF[2]_inst_i_200/O[3] - net (fo=1, routed) 0.864 0.847 u_axi_dvi/video_red_OBUF[2]_inst_i_200_n_4 - SLICE_X11Y84 LUT2 (Prop_lut2_I1_O) 0.307 1.154 r u_axi_dvi/video_red_OBUF[2]_inst_i_132/O - net (fo=1, routed) 0.000 1.154 u_axi_dvi/video_red_OBUF[2]_inst_i_132_n_0 - SLICE_X11Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.401 1.555 r u_axi_dvi/video_red_OBUF[2]_inst_i_67/CO[3] - net (fo=1, routed) 0.000 1.555 u_axi_dvi/video_red_OBUF[2]_inst_i_67_n_0 - SLICE_X11Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.669 f u_axi_dvi/video_red_OBUF[2]_inst_i_31/CO[3] - net (fo=1, routed) 1.273 2.942 u_axi_dvi/video_red_OBUF[2]_inst_i_31_n_0 - SLICE_X16Y85 LUT4 (Prop_lut4_I0_O) 0.124 3.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O - net (fo=1, routed) 0.670 3.736 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I4_O) 0.124 3.860 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 4.410 8.270 video_red_OBUF[0] - E26 OBUF (Prop_obuf_I_O) 3.587 11.856 r video_red_OBUF[2]_inst/O - net (fo=0) 0.000 11.856 video_red[2] - E26 r video_red[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/vdata_reg[3]/C + Source: u_axi_dvi/vdata_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_vsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 12.474ns (logic 4.441ns (35.600%) route 8.033ns (64.400%)) + Data Path Delay: 12.805ns (logic 4.379ns (34.194%) route 8.427ns (65.806%)) Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -35526,19 +34867,19 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_axi_dvi/sys_clk - SLICE_X18Y79 FDRE r u_axi_dvi/vdata_reg[3]/C + net (fo=9971, routed) 1.838 -2.504 u_axi_dvi/sys_clk + SLICE_X47Y82 FDRE r u_axi_dvi/vdata_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X18Y79 FDRE (Prop_fdre_C_Q) 0.518 -1.890 r u_axi_dvi/vdata_reg[3]/Q - net (fo=11, routed) 1.619 -0.271 u_axi_dvi/vdata_reg_n_0_[3] - SLICE_X18Y86 LUT2 (Prop_lut2_I0_O) 0.124 -0.147 f u_axi_dvi/vdata[11]_i_4/O - net (fo=3, routed) 0.682 0.535 u_axi_dvi/vdata[11]_i_4_n_0 - SLICE_X18Y86 LUT6 (Prop_lut6_I5_O) 0.124 0.659 r u_axi_dvi/video_vsync_OBUF_inst_i_2/O - net (fo=1, routed) 0.789 1.448 u_axi_dvi/video_vsync_OBUF_inst_i_2_n_0 - SLICE_X17Y86 LUT4 (Prop_lut4_I0_O) 0.124 1.572 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O - net (fo=1, routed) 4.943 6.515 video_vsync_OBUF - H24 OBUF (Prop_obuf_I_O) 3.551 10.066 r video_vsync_OBUF_inst/O - net (fo=0) 0.000 10.066 video_vsync + SLICE_X47Y82 FDRE (Prop_fdre_C_Q) 0.456 -2.048 f u_axi_dvi/vdata_reg[6]/Q + net (fo=13, routed) 1.558 -0.490 u_axi_dvi/vdata_reg_n_0_[6] + SLICE_X49Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.366 f u_axi_dvi/video_vsync_OBUF_inst_i_5/O + net (fo=1, routed) 0.667 0.301 u_axi_dvi/video_vsync_OBUF_inst_i_5_n_0 + SLICE_X49Y83 LUT6 (Prop_lut6_I5_O) 0.124 0.425 r u_axi_dvi/video_vsync_OBUF_inst_i_3/O + net (fo=1, routed) 0.298 0.723 u_axi_dvi/video_vsync_OBUF_inst_i_3_n_0 + SLICE_X49Y81 LUT4 (Prop_lut4_I2_O) 0.124 0.847 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O + net (fo=1, routed) 5.904 6.751 video_vsync_OBUF + H24 OBUF (Prop_obuf_I_O) 3.551 10.302 r video_vsync_OBUF_inst/O + net (fo=0) 0.000 10.302 video_vsync H24 r video_vsync (OUT) ------------------------------------------------------------------- ------------------- @@ -35549,12 +34890,12 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 12.135ns (logic 4.451ns (36.677%) route 7.684ns (63.323%)) + Data Path Delay: 12.756ns (logic 4.389ns (34.405%) route 8.367ns (65.595%)) Logic Levels: 4 (LUT2=1 LUT6=2 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -35567,35 +34908,35 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_axi_dvi/sys_clk - SLICE_X18Y79 FDRE r u_axi_dvi/vdata_reg[3]/C + net (fo=9971, routed) 1.836 -2.506 u_axi_dvi/sys_clk + SLICE_X47Y81 FDRE r u_axi_dvi/vdata_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X18Y79 FDRE (Prop_fdre_C_Q) 0.518 -1.890 f u_axi_dvi/vdata_reg[3]/Q - net (fo=11, routed) 1.619 -0.271 u_axi_dvi/vdata_reg_n_0_[3] - SLICE_X18Y86 LUT2 (Prop_lut2_I0_O) 0.124 -0.147 r u_axi_dvi/vdata[11]_i_4/O - net (fo=3, routed) 0.305 0.158 u_axi_dvi/vdata[11]_i_4_n_0 - SLICE_X17Y86 LUT6 (Prop_lut6_I2_O) 0.124 0.282 r u_axi_dvi/video_de_OBUF_inst_i_2/O - net (fo=1, routed) 1.030 1.313 u_axi_dvi/video_de_OBUF_inst_i_2_n_0 - SLICE_X14Y86 LUT6 (Prop_lut6_I0_O) 0.124 1.437 r u_axi_dvi/video_de_OBUF_inst_i_1/O - net (fo=1, routed) 4.730 6.166 video_de_OBUF - G24 OBUF (Prop_obuf_I_O) 3.561 9.727 r video_de_OBUF_inst/O - net (fo=0) 0.000 9.727 video_de + SLICE_X47Y81 FDRE (Prop_fdre_C_Q) 0.456 -2.050 f u_axi_dvi/vdata_reg[3]/Q + net (fo=11, routed) 1.027 -1.023 u_axi_dvi/vdata_reg_n_0_[3] + SLICE_X48Y83 LUT2 (Prop_lut2_I0_O) 0.124 -0.899 r u_axi_dvi/vdata[11]_i_4/O + net (fo=3, routed) 0.717 -0.182 u_axi_dvi/vdata[11]_i_4_n_0 + SLICE_X49Y83 LUT6 (Prop_lut6_I2_O) 0.124 -0.058 r u_axi_dvi/video_de_OBUF_inst_i_2/O + net (fo=1, routed) 0.863 0.805 u_axi_dvi/video_de_OBUF_inst_i_2_n_0 + SLICE_X46Y83 LUT6 (Prop_lut6_I0_O) 0.124 0.929 r u_axi_dvi/video_de_OBUF_inst_i_1/O + net (fo=1, routed) 5.761 6.690 video_de_OBUF + G24 OBUF (Prop_obuf_I_O) 3.561 10.251 r video_de_OBUF_inst/O + net (fo=0) 0.000 10.251 video_de G24 r video_de (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_axi_dvi/hdata_reg[3]/C + Source: u_axi_dvi/hdata_reg[4]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_hsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 11.932ns (logic 4.311ns (36.128%) route 7.621ns (63.872%)) + Data Path Delay: 11.845ns (logic 4.311ns (36.394%) route 7.534ns (63.606%)) Logic Levels: 3 (LUT5=2 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -35608,969 +34949,20 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.936 -2.406 u_axi_dvi/sys_clk - SLICE_X12Y81 FDRE r u_axi_dvi/hdata_reg[3]/C + net (fo=9971, routed) 1.840 -2.502 u_axi_dvi/sys_clk + SLICE_X46Y84 FDRE r u_axi_dvi/hdata_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X12Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.888 r u_axi_dvi/hdata_reg[3]/Q - net (fo=11, routed) 1.940 0.053 u_axi_dvi/hdata_reg_n_0_[3] - SLICE_X8Y82 LUT5 (Prop_lut5_I2_O) 0.124 0.177 f u_axi_dvi/video_hsync_OBUF_inst_i_2/O - net (fo=1, routed) 0.953 1.130 u_axi_dvi/video_hsync_OBUF_inst_i_2_n_0 - SLICE_X9Y86 LUT5 (Prop_lut5_I4_O) 0.124 1.254 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O - net (fo=1, routed) 4.728 5.982 video_hsync_OBUF - J24 OBUF (Prop_obuf_I_O) 3.545 9.527 r video_hsync_OBUF_inst/O - net (fo=0) 0.000 9.527 video_hsync + SLICE_X46Y84 FDRE (Prop_fdre_C_Q) 0.518 -1.984 r u_axi_dvi/hdata_reg[4]/Q + net (fo=11, routed) 1.550 -0.433 u_axi_dvi/hdata_reg_n_0_[4] + SLICE_X41Y85 LUT5 (Prop_lut5_I4_O) 0.124 -0.309 f u_axi_dvi/video_hsync_OBUF_inst_i_2/O + net (fo=1, routed) 0.291 -0.018 u_axi_dvi/video_hsync_OBUF_inst_i_2_n_0 + SLICE_X41Y86 LUT5 (Prop_lut5_I4_O) 0.124 0.106 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O + net (fo=1, routed) 5.693 5.799 video_hsync_OBUF + J24 OBUF (Prop_obuf_I_O) 3.545 9.343 r video_hsync_OBUF_inst/O + net (fo=0) 0.000 9.343 video_hsync J24 r video_hsync (OUT) ------------------------------------------------------------------- ------------------- -Slack: inf - Source: u_confreg/led_data_reg[8]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[8] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.822ns (logic 4.079ns (34.503%) route 7.743ns (65.497%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.016 -2.326 u_confreg/sys_clk - SLICE_X2Y81 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X2Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.808 r u_confreg/led_data_reg[8]_lopt_replica/Q - net (fo=1, routed) 7.743 5.935 lopt_14 - C23 OBUF (Prop_obuf_I_O) 3.561 9.496 r leds_OBUF[8]_inst/O - net (fo=0) 0.000 9.496 leds[8] - C23 r leds[8] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[15]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[15] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.646ns (logic 4.019ns (34.509%) route 7.627ns (65.491%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[15]_lopt_replica/Q - net (fo=1, routed) 7.627 5.768 lopt_6 - B20 OBUF (Prop_obuf_I_O) 3.563 9.331 r leds_OBUF[15]_inst/O - net (fo=0) 0.000 9.331 leds[15] - B20 r leds[15] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[4]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[4] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.447ns (logic 4.018ns (35.101%) route 7.429ns (64.899%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.025 -2.317 u_confreg/sys_clk - SLICE_X3Y89 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.456 -1.861 r u_confreg/led_data_reg[4]_lopt_replica/Q - net (fo=1, routed) 7.429 5.569 lopt_10 - C22 OBUF (Prop_obuf_I_O) 3.562 9.131 r leds_OBUF[4]_inst/O - net (fo=0) 0.000 9.131 leds[4] - C22 r leds[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[4] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.583ns (logic 3.995ns (34.493%) route 7.588ns (65.507%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q - net (fo=1, routed) 7.588 5.556 dpy0_OBUF[4] - E18 OBUF (Prop_obuf_I_O) 3.539 9.095 r dpy0_OBUF[4]_inst/O - net (fo=0) 0.000 9.095 dpy0[4] - E18 r dpy0[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[5]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[5] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.360ns (logic 4.147ns (36.509%) route 7.213ns (63.491%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.419 -1.896 r u_confreg/led_data_reg[5]_lopt_replica/Q - net (fo=1, routed) 7.213 5.317 lopt_11 - C21 OBUF (Prop_obuf_I_O) 3.728 9.045 r leds_OBUF[5]_inst/O - net (fo=0) 0.000 9.045 leds[5] - C21 r leds[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[9]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[9] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.061ns (logic 4.038ns (36.509%) route 7.023ns (63.491%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.022 -2.320 u_confreg/sys_clk - SLICE_X0Y86 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.456 -1.864 r u_confreg/led_data_reg[9]_lopt_replica/Q - net (fo=1, routed) 7.023 5.159 lopt_15 - A23 OBUF (Prop_obuf_I_O) 3.582 8.741 r leds_OBUF[9]_inst/O - net (fo=0) 0.000 8.741 leds[9] - A23 r leds[9] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_uart_controller/uart0/regs/mcr_reg[4]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: UART_TX - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.130ns (logic 4.308ns (38.708%) route 6.822ns (61.292%)) - Logic Levels: 2 (LUT4=1 OBUFT=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_axi_uart_controller/uart0/regs/sys_clk - SLICE_X8Y66 FDRE r u_axi_uart_controller/uart0/regs/mcr_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X8Y66 FDRE (Prop_fdre_C_Q) 0.478 -1.925 r u_axi_uart_controller/uart0/regs/mcr_reg[4]/Q - net (fo=8, routed) 1.213 -0.712 u_axi_uart_controller/uart0/regs/transmitter/counter_b_reg[7]_0[0] - SLICE_X1Y60 LUT4 (Prop_lut4_I3_O) 0.301 -0.411 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_1/O - net (fo=1, routed) 5.609 5.198 UART_TX_IOBUF_inst/I - H18 OBUFT (Prop_obuft_I_O) 3.529 8.727 r UART_TX_IOBUF_inst/OBUFT/O - net (fo=1, unset) 0.000 8.727 UART_TX - H18 r UART_TX (INOUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[3] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 10.508ns (logic 3.970ns (37.784%) route 6.537ns (62.216%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q - net (fo=1, routed) 6.537 4.680 dpy1_OBUF[3] - F17 OBUF (Prop_obuf_I_O) 3.514 8.194 r dpy1_OBUF[3]_inst/O - net (fo=0) 0.000 8.194 dpy1[3] - F17 r dpy1[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[2] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 10.468ns (logic 4.014ns (38.349%) route 6.454ns (61.651%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q - net (fo=1, routed) 6.454 4.422 dpy0_OBUF[2] - B21 OBUF (Prop_obuf_I_O) 3.558 7.981 r dpy0_OBUF[2]_inst/O - net (fo=0) 0.000 7.981 dpy0[2] - B21 r dpy0[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[3]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[3] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 10.251ns (logic 4.018ns (39.198%) route 6.233ns (60.802%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[3]_lopt_replica/Q - net (fo=1, routed) 6.233 4.375 lopt_9 - D23 OBUF (Prop_obuf_I_O) 3.562 7.937 r leds_OBUF[3]_inst/O - net (fo=0) 0.000 7.937 leds[3] - D23 r leds[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[2]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[2] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 10.239ns (logic 4.043ns (39.483%) route 6.196ns (60.517%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[2]_lopt_replica/Q - net (fo=1, routed) 6.196 4.339 lopt_8 - A24 OBUF (Prop_obuf_I_O) 3.587 7.926 r leds_OBUF[2]_inst/O - net (fo=0) 0.000 7.926 leds[2] - A24 r leds[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[11]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[11] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.633ns (logic 4.023ns (41.758%) route 5.611ns (58.242%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y96 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[11]_lopt_replica/Q - net (fo=1, routed) 5.611 3.752 lopt_2 - A18 OBUF (Prop_obuf_I_O) 3.567 7.319 r leds_OBUF[11]_inst/O - net (fo=0) 0.000 7.319 leds[11] - A18 r leds[11] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[6] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.588ns (logic 3.993ns (41.645%) route 5.595ns (58.355%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q - net (fo=1, routed) 5.595 3.738 dpy1_OBUF[6] - F15 OBUF (Prop_obuf_I_O) 3.537 7.275 r dpy1_OBUF[6]_inst/O - net (fo=0) 0.000 7.275 dpy1[6] - F15 r dpy1[6] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[6]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[6] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.545ns (logic 4.133ns (43.294%) route 5.413ns (56.706%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.419 -1.896 r u_confreg/led_data_reg[6]_lopt_replica/Q - net (fo=1, routed) 5.413 3.517 lopt_12 - E20 OBUF (Prop_obuf_I_O) 3.714 7.231 r leds_OBUF[6]_inst/O - net (fo=0) 0.000 7.231 leds[6] - E20 r leds[6] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[5] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.552ns (logic 4.002ns (41.895%) route 5.550ns (58.105%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q - net (fo=1, routed) 5.550 3.519 dpy0_OBUF[5] - C19 OBUF (Prop_obuf_I_O) 3.546 7.065 r dpy0_OBUF[5]_inst/O - net (fo=0) 0.000 7.065 dpy0[5] - C19 r dpy0[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[2] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.354ns (logic 3.998ns (42.735%) route 5.357ns (57.265%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q - net (fo=1, routed) 5.357 3.499 dpy1_OBUF[2] - E17 OBUF (Prop_obuf_I_O) 3.542 7.041 r dpy1_OBUF[2]_inst/O - net (fo=0) 0.000 7.041 dpy1[2] - E17 r dpy1[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_uart_controller/uart0/regs/sclk_reg_reg/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: UART_RX - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.365ns (logic 4.162ns (44.443%) route 5.203ns (55.557%)) - Logic Levels: 2 (LUT2=1 OBUFT=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.944 -2.398 u_axi_uart_controller/uart0/regs/sys_clk - SLICE_X10Y64 FDRE r u_axi_uart_controller/uart0/regs/sclk_reg_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X10Y64 FDRE (Prop_fdre_C_Q) 0.518 -1.880 r u_axi_uart_controller/uart0/regs/sclk_reg_reg/Q - net (fo=2, routed) 0.521 -1.358 u_axi_uart_controller/uart0/regs/sclk_reg_reg_n_0 - SLICE_X10Y64 LUT2 (Prop_lut2_I0_O) 0.124 -1.234 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/O - net (fo=1, routed) 4.682 3.448 UART_RX_IOBUF_inst/I - J20 OBUFT (Prop_obuft_I_O) 3.520 6.968 r UART_RX_IOBUF_inst/OBUFT/O - net (fo=1, unset) 0.000 6.968 UART_RX - J20 r UART_RX (INOUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[1] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.190ns (logic 4.001ns (43.538%) route 5.189ns (56.462%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q - net (fo=1, routed) 5.189 3.157 dpy0_OBUF[1] - D19 OBUF (Prop_obuf_I_O) 3.545 6.703 r dpy0_OBUF[1]_inst/O - net (fo=0) 0.000 6.703 dpy0[1] - D19 r dpy0[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[4] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.973ns (logic 3.998ns (44.549%) route 4.976ns (55.451%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q - net (fo=1, routed) 4.976 3.118 dpy1_OBUF[4] - E16 OBUF (Prop_obuf_I_O) 3.542 6.660 r dpy1_OBUF[4]_inst/O - net (fo=0) 0.000 6.660 dpy1[4] - E16 r dpy1[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[3] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.071ns (logic 4.029ns (44.418%) route 5.042ns (55.582%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q - net (fo=1, routed) 5.042 3.010 dpy0_OBUF[3] - A19 OBUF (Prop_obuf_I_O) 3.573 6.583 r dpy0_OBUF[3]_inst/O - net (fo=0) 0.000 6.583 dpy0[3] - A19 r dpy0[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[1] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.824ns (logic 4.005ns (45.390%) route 4.819ns (54.610%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q - net (fo=1, routed) 4.819 2.961 dpy1_OBUF[1] - D16 OBUF (Prop_obuf_I_O) 3.549 6.510 r dpy1_OBUF[1]_inst/O - net (fo=0) 0.000 6.510 dpy1[1] - D16 r dpy1[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[12]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[12] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.826ns (logic 3.998ns (45.302%) route 4.828ns (54.698%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.025 -2.317 u_confreg/sys_clk - SLICE_X3Y89 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.456 -1.861 r u_confreg/led_data_reg[12]_lopt_replica/Q - net (fo=1, routed) 4.828 2.967 lopt_3 - D20 OBUF (Prop_obuf_I_O) 3.542 6.510 r leds_OBUF[12]_inst/O - net (fo=0) 0.000 6.510 leds[12] - D20 r leds[12] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[0] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.940ns (logic 4.016ns (44.923%) route 4.924ns (55.077%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q - net (fo=1, routed) 4.924 2.892 dpy0_OBUF[0] - B19 OBUF (Prop_obuf_I_O) 3.560 6.452 r dpy0_OBUF[0]_inst/O - net (fo=0) 0.000 6.452 dpy0[0] - B19 r dpy0[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[5] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.755ns (logic 3.990ns (45.576%) route 4.765ns (54.424%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q - net (fo=1, routed) 4.765 2.907 dpy1_OBUF[5] - G16 OBUF (Prop_obuf_I_O) 3.534 6.441 r dpy1_OBUF[5]_inst/O - net (fo=0) 0.000 6.441 dpy1[5] - G16 r dpy1[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[0] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.735ns (logic 4.021ns (46.039%) route 4.713ns (53.961%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q - net (fo=1, routed) 4.713 2.856 dpy1_OBUF[0] - A17 OBUF (Prop_obuf_I_O) 3.565 6.421 r dpy1_OBUF[0]_inst/O - net (fo=0) 0.000 6.421 dpy1[0] - A17 r dpy1[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[7] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.710ns (logic 3.976ns (45.648%) route 4.734ns (54.352%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q - net (fo=1, routed) 4.734 2.877 dpy1_OBUF[7] - G17 OBUF (Prop_obuf_I_O) 3.520 6.397 r dpy1_OBUF[7]_inst/O - net (fo=0) 0.000 6.397 dpy1[7] - G17 r dpy1[7] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[14]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[14] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.585ns (logic 4.019ns (46.814%) route 4.566ns (53.186%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[14]_lopt_replica/Q - net (fo=1, routed) 4.566 2.707 lopt_5 - A20 OBUF (Prop_obuf_I_O) 3.563 6.270 r leds_OBUF[14]_inst/O - net (fo=0) 0.000 6.270 leds[14] - A20 r leds[14] (OUT) - ------------------------------------------------------------------- ------------------- - Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -36578,12 +34970,12 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 8.741ns (logic 4.012ns (45.901%) route 4.729ns (54.099%)) + Data Path Delay: 10.827ns (logic 4.074ns (37.631%) route 6.753ns (62.369%)) Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -36596,29 +34988,29 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q - net (fo=1, routed) 4.729 2.697 dpy0_OBUF[6] - B17 OBUF (Prop_obuf_I_O) 3.556 6.254 r dpy0_OBUF[6]_inst/O - net (fo=0) 0.000 6.254 dpy0[6] + SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q + net (fo=1, routed) 6.753 4.594 dpy0_OBUF[6] + B17 OBUF (Prop_obuf_I_O) 3.556 8.151 r dpy0_OBUF[6]_inst/O + net (fo=0) 0.000 8.151 dpy0[6] B17 r dpy0[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[10]_lopt_replica/C + Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[10] + Destination: UART_TX (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 8.566ns (logic 4.003ns (46.730%) route 4.563ns (53.270%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Data Path Delay: 10.830ns (logic 4.317ns (39.866%) route 6.513ns (60.134%)) + Logic Levels: 2 (LUT3=1 OBUFT=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -36631,14 +35023,17 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.022 -2.320 u_confreg/sys_clk - SLICE_X0Y86 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C + net (fo=9971, routed) 1.638 -2.704 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X80Y133 FDRE r u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.456 -1.864 r u_confreg/led_data_reg[10]_lopt_replica/Q - net (fo=1, routed) 4.563 2.700 lopt_1 - D21 OBUF (Prop_obuf_I_O) 3.547 6.247 r leds_OBUF[10]_inst/O - net (fo=0) 0.000 6.247 leds[10] - D21 r leds[10] (OUT) + SLICE_X80Y133 FDRE (Prop_fdre_C_Q) 0.478 -2.226 f u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/Q + net (fo=13, routed) 1.393 -0.832 u_axi_uart_controller/uart0/regs/transmitter/tf_pop_reg_0[1] + SLICE_X77Y137 LUT3 (Prop_lut3_I1_O) 0.295 -0.537 f u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O + net (fo=1, routed) 5.119 4.582 UART_TX_IOBUF_inst/T + H18 OBUFT (TriStatE_obuft_T_O) + 3.544 8.126 r UART_TX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 8.126 UART_TX + H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -36648,12 +35043,12 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 8.730ns (logic 4.001ns (45.828%) route 4.729ns (54.172%)) + Data Path Delay: 10.564ns (logic 4.063ns (38.456%) route 6.502ns (61.544%)) Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -36666,16 +35061,613 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q - net (fo=1, routed) 4.729 2.697 dpy0_OBUF[7] - C17 OBUF (Prop_obuf_I_O) 3.545 6.242 r dpy0_OBUF[7]_inst/O - net (fo=0) 0.000 6.242 dpy0[7] + SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q + net (fo=1, routed) 6.502 4.343 dpy0_OBUF[7] + C17 OBUF (Prop_obuf_I_O) 3.545 7.888 r dpy0_OBUF[7]_inst/O + net (fo=0) 0.000 7.888 dpy0[7] C17 r dpy0[7] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[4] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.495ns (logic 4.057ns (38.657%) route 6.438ns (61.343%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q + net (fo=1, routed) 6.438 4.280 dpy0_OBUF[4] + E18 OBUF (Prop_obuf_I_O) 3.539 7.819 r dpy0_OBUF[4]_inst/O + net (fo=0) 0.000 7.819 dpy0[4] + E18 r dpy0[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: UART_RX + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.517ns (logic 4.100ns (38.989%) route 6.416ns (61.011%)) + Logic Levels: 2 (LUT2=1 OBUFT=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.643 -2.699 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X85Y134 FDRE r u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X85Y134 FDRE (Prop_fdre_C_Q) 0.456 -2.243 r u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/Q + net (fo=2, routed) 0.810 -1.433 u_axi_uart_controller/uart0/regs/sclk_por + SLICE_X86Y135 LUT2 (Prop_lut2_I1_O) 0.124 -1.309 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/O + net (fo=1, routed) 5.607 4.298 UART_RX_IOBUF_inst/I + J20 OBUFT (Prop_obuft_I_O) 3.520 7.818 r UART_RX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 7.818 UART_RX + J20 r UART_RX (INOUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[0] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.196ns (logic 4.016ns (39.389%) route 6.180ns (60.611%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.666 -2.676 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X63Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X63Y141 FDCE (Prop_fdce_C_Q) 0.456 -2.220 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q + net (fo=1, routed) 6.180 3.960 dpy0_OBUF[0] + B19 OBUF (Prop_obuf_I_O) 3.560 7.520 r dpy0_OBUF[0]_inst/O + net (fo=0) 0.000 7.520 dpy0[0] + B19 r dpy0[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[7] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.115ns (logic 4.038ns (39.923%) route 6.077ns (60.077%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q + net (fo=1, routed) 6.077 3.899 dpy1_OBUF[7] + G17 OBUF (Prop_obuf_I_O) 3.520 7.419 r dpy1_OBUF[7]_inst/O + net (fo=0) 0.000 7.419 dpy1[7] + G17 r dpy1[7] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[5] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.022ns (logic 4.002ns (39.929%) route 6.021ns (60.071%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q + net (fo=1, routed) 6.021 3.800 dpy0_OBUF[5] + C19 OBUF (Prop_obuf_I_O) 3.546 7.346 r dpy0_OBUF[5]_inst/O + net (fo=0) 0.000 7.346 dpy0[5] + C19 r dpy0[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[3] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.920ns (logic 4.091ns (41.241%) route 5.829ns (58.759%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q + net (fo=1, routed) 5.829 3.670 dpy0_OBUF[3] + A19 OBUF (Prop_obuf_I_O) 3.573 7.243 r dpy0_OBUF[3]_inst/O + net (fo=0) 0.000 7.243 dpy0[3] + A19 r dpy0[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[3] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.911ns (logic 4.032ns (40.684%) route 5.879ns (59.316%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q + net (fo=1, routed) 5.879 3.701 dpy1_OBUF[3] + F17 OBUF (Prop_obuf_I_O) 3.514 7.215 r dpy1_OBUF[3]_inst/O + net (fo=0) 0.000 7.215 dpy1[3] + F17 r dpy1[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[6] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.858ns (logic 4.055ns (41.135%) route 5.803ns (58.865%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.644 -2.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.518 -2.180 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q + net (fo=1, routed) 5.803 3.623 dpy1_OBUF[6] + F15 OBUF (Prop_obuf_I_O) 3.537 7.160 r dpy1_OBUF[6]_inst/O + net (fo=0) 0.000 7.160 dpy1[6] + F15 r dpy1[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[5] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.779ns (logic 4.052ns (41.435%) route 5.727ns (58.565%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.644 -2.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.518 -2.180 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q + net (fo=1, routed) 5.727 3.547 dpy1_OBUF[5] + G16 OBUF (Prop_obuf_I_O) 3.534 7.081 r dpy1_OBUF[5]_inst/O + net (fo=0) 0.000 7.081 dpy1[5] + G16 r dpy1[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[4] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.775ns (logic 4.060ns (41.529%) route 5.716ns (58.471%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q + net (fo=1, routed) 5.716 3.538 dpy1_OBUF[4] + E16 OBUF (Prop_obuf_I_O) 3.542 7.079 r dpy1_OBUF[4]_inst/O + net (fo=0) 0.000 7.079 dpy1[4] + E16 r dpy1[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[1] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.705ns (logic 4.067ns (41.907%) route 5.638ns (58.093%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.644 -2.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.518 -2.180 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q + net (fo=1, routed) 5.638 3.458 dpy1_OBUF[1] + D16 OBUF (Prop_obuf_I_O) 3.549 7.007 r dpy1_OBUF[1]_inst/O + net (fo=0) 0.000 7.007 dpy1[1] + D16 r dpy1[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[0] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.696ns (logic 4.083ns (42.113%) route 5.613ns (57.887%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q + net (fo=1, routed) 5.613 3.435 dpy1_OBUF[0] + A17 OBUF (Prop_obuf_I_O) 3.565 7.000 r dpy1_OBUF[0]_inst/O + net (fo=0) 0.000 7.000 dpy1[0] + A17 r dpy1[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.645ns (logic 4.014ns (41.623%) route 5.630ns (58.377%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q + net (fo=1, routed) 5.630 3.410 dpy0_OBUF[2] + B21 OBUF (Prop_obuf_I_O) 3.558 6.968 r dpy0_OBUF[2]_inst/O + net (fo=0) 0.000 6.968 dpy0[2] + B21 r dpy0[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[1] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.634ns (logic 4.001ns (41.531%) route 5.633ns (58.469%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q + net (fo=1, routed) 5.633 3.413 dpy0_OBUF[1] + D19 OBUF (Prop_obuf_I_O) 3.545 6.958 r dpy0_OBUF[1]_inst/O + net (fo=0) 0.000 6.958 dpy0[1] + D19 r dpy0[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.306ns (logic 4.060ns (43.623%) route 5.246ns (56.377%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.644 -2.698 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.518 -2.180 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q + net (fo=1, routed) 5.246 3.066 dpy1_OBUF[2] + E17 OBUF (Prop_obuf_I_O) 3.542 6.608 r dpy1_OBUF[2]_inst/O + net (fo=0) 0.000 6.608 dpy1[2] + E17 r dpy1[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[14]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[14] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.878ns (logic 4.081ns (45.964%) route 4.798ns (54.036%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.769 -2.573 u_confreg/sys_clk + SLICE_X22Y141 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.055 r u_confreg/led_data_reg[14]_lopt_replica/Q + net (fo=1, routed) 4.798 2.743 lopt_5 + A20 OBUF (Prop_obuf_I_O) 3.563 6.306 r leds_OBUF[14]_inst/O + net (fo=0) 0.000 6.306 leds[14] + A20 r leds[14] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[6]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[6] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.860ns (logic 4.060ns (45.821%) route 4.800ns (54.179%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk + SLICE_X12Y142 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.518 -2.051 r u_confreg/led_data_reg[6]_lopt_replica/Q + net (fo=1, routed) 4.800 2.749 lopt_12 + E20 OBUF (Prop_obuf_I_O) 3.542 6.291 r leds_OBUF[6]_inst/O + net (fo=0) 0.000 6.291 leds[6] + E20 r leds[6] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: u_confreg/led_data_reg[7]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -36683,12 +35675,12 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 8.548ns (logic 4.164ns (48.712%) route 4.384ns (51.288%)) + Data Path Delay: 8.741ns (logic 4.090ns (46.792%) route 4.651ns (53.208%)) Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -36701,16 +35693,156 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C + net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk + SLICE_X12Y142 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.419 -1.896 r u_confreg/led_data_reg[7]_lopt_replica/Q - net (fo=1, routed) 4.384 2.489 lopt_13 - B22 OBUF (Prop_obuf_I_O) 3.745 6.234 r leds_OBUF[7]_inst/O - net (fo=0) 0.000 6.234 leds[7] + SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.518 -2.051 r u_confreg/led_data_reg[7]_lopt_replica/Q + net (fo=1, routed) 4.651 2.600 lopt_13 + B22 OBUF (Prop_obuf_I_O) 3.572 6.172 r leds_OBUF[7]_inst/O + net (fo=0) 0.000 6.172 leds[7] B22 r leds[7] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: u_confreg/led_data_reg[8]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[8] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.684ns (logic 4.079ns (46.970%) route 4.605ns (53.030%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.769 -2.573 u_confreg/sys_clk + SLICE_X22Y141 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.055 r u_confreg/led_data_reg[8]_lopt_replica/Q + net (fo=1, routed) 4.605 2.551 lopt_14 + C23 OBUF (Prop_obuf_I_O) 3.561 6.112 r leds_OBUF[8]_inst/O + net (fo=0) 0.000 6.112 leds[8] + C23 r leds[8] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[2]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.692ns (logic 4.105ns (47.224%) route 4.587ns (52.776%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.758 -2.584 u_confreg/sys_clk + SLICE_X36Y140 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X36Y140 FDRE (Prop_fdre_C_Q) 0.518 -2.066 r u_confreg/led_data_reg[2]_lopt_replica/Q + net (fo=1, routed) 4.587 2.522 lopt_8 + A24 OBUF (Prop_obuf_I_O) 3.587 6.109 r leds_OBUF[2]_inst/O + net (fo=0) 0.000 6.109 leds[2] + A24 r leds[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[5]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[5] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.677ns (logic 4.071ns (46.921%) route 4.606ns (53.079%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.771 -2.571 u_confreg/sys_clk + SLICE_X20Y141 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X20Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.053 r u_confreg/led_data_reg[5]_lopt_replica/Q + net (fo=1, routed) 4.606 2.553 lopt_11 + C21 OBUF (Prop_obuf_I_O) 3.553 6.107 r leds_OBUF[5]_inst/O + net (fo=0) 0.000 6.107 leds[5] + C21 r leds[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[4]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[4] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.674ns (logic 4.080ns (47.039%) route 4.594ns (52.961%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.769 -2.573 u_confreg/sys_clk + SLICE_X22Y141 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.055 r u_confreg/led_data_reg[4]_lopt_replica/Q + net (fo=1, routed) 4.594 2.539 lopt_10 + C22 OBUF (Prop_obuf_I_O) 3.562 6.101 r leds_OBUF[4]_inst/O + net (fo=0) 0.000 6.101 leds[4] + C22 r leds[4] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: u_confreg/led_data_reg[13]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -36718,12 +35850,12 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 8.473ns (logic 4.027ns (47.524%) route 4.446ns (52.476%)) + Data Path Delay: 8.553ns (logic 4.027ns (47.079%) route 4.526ns (52.921%)) Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -36736,16 +35868,51 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk - SLICE_X1Y98 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C + net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk + SLICE_X13Y142 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[13]_lopt_replica/Q - net (fo=1, routed) 4.446 2.588 lopt_4 - A22 OBUF (Prop_obuf_I_O) 3.571 6.159 r leds_OBUF[13]_inst/O - net (fo=0) 0.000 6.159 leds[13] + SLICE_X13Y142 FDRE (Prop_fdre_C_Q) 0.456 -2.113 r u_confreg/led_data_reg[13]_lopt_replica/Q + net (fo=1, routed) 4.526 2.414 lopt_4 + A22 OBUF (Prop_obuf_I_O) 3.571 5.984 r leds_OBUF[13]_inst/O + net (fo=0) 0.000 5.984 leds[13] A22 r leds[13] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: u_confreg/led_data_reg[3]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[3] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.563ns (logic 4.080ns (47.648%) route 4.483ns (52.352%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.759 -2.583 u_confreg/sys_clk + SLICE_X36Y141 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X36Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.065 r u_confreg/led_data_reg[3]_lopt_replica/Q + net (fo=1, routed) 4.483 2.418 lopt_9 + D23 OBUF (Prop_obuf_I_O) 3.562 5.980 r leds_OBUF[3]_inst/O + net (fo=0) 0.000 5.980 leds[3] + D23 r leds[3] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: u_confreg/led_data_reg[1]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -36753,12 +35920,12 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 8.398ns (logic 3.997ns (47.597%) route 4.401ns (52.403%)) + Data Path Delay: 8.399ns (logic 4.059ns (48.331%) route 4.339ns (51.669%)) Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -36771,16 +35938,86 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C + net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk + SLICE_X12Y142 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[1]_lopt_replica/Q - net (fo=1, routed) 4.401 2.543 lopt_7 - E21 OBUF (Prop_obuf_I_O) 3.541 6.084 r leds_OBUF[1]_inst/O - net (fo=0) 0.000 6.084 leds[1] + SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.518 -2.051 r u_confreg/led_data_reg[1]_lopt_replica/Q + net (fo=1, routed) 4.339 2.289 lopt_7 + E21 OBUF (Prop_obuf_I_O) 3.541 5.830 r leds_OBUF[1]_inst/O + net (fo=0) 0.000 5.830 leds[1] E21 r leds[1] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: u_confreg/led_data_reg[11]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[11] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.149ns (logic 4.085ns (50.125%) route 4.064ns (49.875%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk + SLICE_X12Y141 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.051 r u_confreg/led_data_reg[11]_lopt_replica/Q + net (fo=1, routed) 4.064 2.014 lopt_2 + A18 OBUF (Prop_obuf_I_O) 3.567 5.580 r leds_OBUF[11]_inst/O + net (fo=0) 0.000 5.580 leds[11] + A18 r leds[11] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[12]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[12] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.027ns (logic 3.998ns (49.809%) route 4.029ns (50.191%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk + SLICE_X13Y142 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y142 FDRE (Prop_fdre_C_Q) 0.456 -2.113 r u_confreg/led_data_reg[12]_lopt_replica/Q + net (fo=1, routed) 4.029 1.916 lopt_3 + D20 OBUF (Prop_obuf_I_O) 3.542 5.459 r leds_OBUF[12]_inst/O + net (fo=0) 0.000 5.459 leds[12] + D20 r leds[12] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: u_confreg/led_data_reg[0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -36788,12 +36025,12 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 8.138ns (logic 4.031ns (49.529%) route 4.108ns (50.471%)) + Data Path Delay: 7.984ns (logic 4.093ns (51.265%) route 3.891ns (48.735%)) Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -36806,16 +36043,121 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y96 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C + net (fo=9971, routed) 1.769 -2.573 u_confreg/sys_clk + SLICE_X22Y141 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[0]_lopt_replica/Q - net (fo=1, routed) 4.108 2.249 lopt - B24 OBUF (Prop_obuf_I_O) 3.575 5.824 r leds_OBUF[0]_inst/O - net (fo=0) 0.000 5.824 leds[0] + SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.055 r u_confreg/led_data_reg[0]_lopt_replica/Q + net (fo=1, routed) 3.891 1.836 lopt + B24 OBUF (Prop_obuf_I_O) 3.575 5.411 r leds_OBUF[0]_inst/O + net (fo=0) 0.000 5.411 leds[0] B24 r leds[0] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: u_confreg/led_data_reg[10]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[10] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 7.925ns (logic 4.065ns (51.296%) route 3.860ns (48.704%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.771 -2.571 u_confreg/sys_clk + SLICE_X20Y141 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X20Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.053 r u_confreg/led_data_reg[10]_lopt_replica/Q + net (fo=1, routed) 3.860 1.807 lopt_1 + D21 OBUF (Prop_obuf_I_O) 3.547 5.354 r leds_OBUF[10]_inst/O + net (fo=0) 0.000 5.354 leds[10] + D21 r leds[10] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[15]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[15] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 7.829ns (logic 4.081ns (52.122%) route 3.749ns (47.878%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk + SLICE_X12Y142 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.518 -2.051 r u_confreg/led_data_reg[15]_lopt_replica/Q + net (fo=1, routed) 3.749 1.698 lopt_6 + B20 OBUF (Prop_obuf_I_O) 3.563 5.261 r leds_OBUF[15]_inst/O + net (fo=0) 0.000 5.261 leds[15] + B20 r leds[15] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[9]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[9] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 7.704ns (logic 4.100ns (53.220%) route 3.604ns (46.780%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.773 -2.569 u_confreg/sys_clk + SLICE_X14Y141 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X14Y141 FDRE (Prop_fdre_C_Q) 0.518 -2.051 r u_confreg/led_data_reg[9]_lopt_replica/Q + net (fo=1, routed) 3.604 1.553 lopt_15 + A23 OBUF (Prop_obuf_I_O) 3.582 5.136 r leds_OBUF[9]_inst/O + net (fo=0) 0.000 5.136 leds[9] + A23 r leds[9] (OUT) + ------------------------------------------------------------------- ------------------- + @@ -36832,1242 +36174,6 @@ Min Delay 0 Endpoints Max Delay Paths -------------------------------------------------------------------------------------- -Slack: inf - Source: dip_sw[8] - (input port) - Destination: u_confreg/s_rdata_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.851ns (logic 1.724ns (14.546%) route 10.127ns (85.454%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.940ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.940ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M6 0.000 0.000 r dip_sw[8] (IN) - net (fo=0) 0.000 0.000 dip_sw[8] - M6 IBUF (Prop_ibuf_I_O) 1.476 1.476 r dip_sw_IBUF[8]_inst/O - net (fo=1, routed) 9.460 10.936 u_confreg/dip_sw_IBUF[8] - SLICE_X5Y79 LUT5 (Prop_lut5_I4_O) 0.124 11.060 r u_confreg/s_rdata[8]_i_4/O - net (fo=1, routed) 0.667 11.727 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 - SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.124 11.851 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O - net (fo=1, routed) 0.000 11.851 u_confreg/u_int_ctrl_n_23 - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.888 -1.940 u_confreg/sys_clk - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/C - -Slack: inf - Source: dip_sw[20] - (input port) - Destination: u_confreg/s_rdata_reg[20]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.647ns (logic 1.723ns (14.794%) route 9.924ns (85.206%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M4 0.000 0.000 r dip_sw[20] (IN) - net (fo=0) 0.000 0.000 dip_sw[20] - M4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r dip_sw_IBUF[20]_inst/O - net (fo=1, routed) 9.163 10.638 u_confreg/dip_sw_IBUF[20] - SLICE_X7Y92 LUT5 (Prop_lut5_I4_O) 0.124 10.762 r u_confreg/s_rdata[20]_i_4/O - net (fo=1, routed) 0.761 11.523 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.124 11.647 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O - net (fo=1, routed) 0.000 11.647 u_confreg/u_int_ctrl_n_11 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/C - -Slack: inf - Source: dip_sw[13] - (input port) - Destination: u_confreg/s_rdata_reg[13]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.183ns (logic 1.734ns (15.504%) route 9.449ns (84.496%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.932ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.932ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K3 0.000 0.000 r dip_sw[13] (IN) - net (fo=0) 0.000 0.000 dip_sw[13] - K3 IBUF (Prop_ibuf_I_O) 1.486 1.486 r dip_sw_IBUF[13]_inst/O - net (fo=1, routed) 8.863 10.349 u_confreg/dip_sw_IBUF[13] - SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.124 10.473 r u_confreg/s_rdata[13]_i_4/O - net (fo=1, routed) 0.586 11.059 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 - SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.124 11.183 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O - net (fo=1, routed) 0.000 11.183 u_confreg/u_int_ctrl_n_18 - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.896 -1.932 u_confreg/sys_clk - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/C - -Slack: inf - Source: dip_sw[1] - (input port) - Destination: u_confreg/s_rdata_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.155ns (logic 1.746ns (15.651%) route 9.409ns (84.349%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - J3 0.000 0.000 r dip_sw[1] (IN) - net (fo=0) 0.000 0.000 dip_sw[1] - J3 IBUF (Prop_ibuf_I_O) 1.498 1.498 r dip_sw_IBUF[1]_inst/O - net (fo=1, routed) 8.467 9.965 u_confreg/dip_sw_IBUF[1] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.124 10.089 r u_confreg/s_rdata[1]_i_4/O - net (fo=1, routed) 0.942 11.031 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 11.155 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O - net (fo=1, routed) 0.000 11.155 u_confreg/u_int_ctrl_n_30 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/C - -Slack: inf - Source: dip_sw[11] - (input port) - Destination: u_confreg/s_rdata_reg[11]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.052ns (logic 1.719ns (15.556%) route 9.333ns (84.444%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.937ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.937ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L7 0.000 0.000 r dip_sw[11] (IN) - net (fo=0) 0.000 0.000 dip_sw[11] - L7 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[11]_inst/O - net (fo=1, routed) 8.677 10.148 u_confreg/dip_sw_IBUF[11] - SLICE_X4Y82 LUT5 (Prop_lut5_I4_O) 0.124 10.272 r u_confreg/s_rdata[11]_i_4/O - net (fo=1, routed) 0.656 10.928 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 - SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.124 11.052 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O - net (fo=1, routed) 0.000 11.052 u_confreg/u_int_ctrl_n_20 - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.891 -1.937 u_confreg/sys_clk - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/C - -Slack: inf - Source: dip_sw[25] - (input port) - Destination: u_confreg/s_rdata_reg[25]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 10.711ns (logic 1.737ns (16.220%) route 8.974ns (83.780%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.010ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R3 0.000 0.000 r dip_sw[25] (IN) - net (fo=0) 0.000 0.000 dip_sw[25] - R3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[25]_inst/O - net (fo=1, routed) 8.245 9.734 u_confreg/dip_sw_IBUF[25] - SLICE_X9Y88 LUT5 (Prop_lut5_I4_O) 0.124 9.858 r u_confreg/s_rdata[25]_i_4/O - net (fo=1, routed) 0.729 10.587 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 10.711 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O - net (fo=1, routed) 0.000 10.711 u_confreg/u_int_ctrl_n_6 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/C - -Slack: inf - Source: dip_sw[19] - (input port) - Destination: u_confreg/s_rdata_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 10.426ns (logic 1.726ns (16.557%) route 8.700ns (83.443%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.934ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.934ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L4 0.000 0.000 r dip_sw[19] (IN) - net (fo=0) 0.000 0.000 dip_sw[19] - L4 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[19]_inst/O - net (fo=1, routed) 8.546 10.024 u_confreg/dip_sw_IBUF[19] - SLICE_X7Y86 LUT5 (Prop_lut5_I4_O) 0.124 10.148 r u_confreg/s_rdata[19]_i_4/O - net (fo=1, routed) 0.154 10.302 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 - SLICE_X7Y86 LUT6 (Prop_lut6_I4_O) 0.124 10.426 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O - net (fo=1, routed) 0.000 10.426 u_confreg/u_int_ctrl_n_12 - SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.894 -1.934 u_confreg/sys_clk - SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/C - -Slack: inf - Source: touch_btn[2] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 10.138ns (logic 1.487ns (14.666%) route 8.651ns (85.334%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -1.936ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.936ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P3 0.000 0.000 r touch_btn[2] (IN) - net (fo=0) 0.000 0.000 touch_btn[2] - P3 IBUF (Prop_ibuf_I_O) 1.487 1.487 r touch_btn_IBUF[2]_inst/O - net (fo=1, routed) 8.651 10.138 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] - SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.892 -1.936 u_confreg/u_int_ctrl/sys_clk - SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C - -Slack: inf - Source: dip_sw[9] - (input port) - Destination: u_confreg/s_rdata_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.432ns (logic 1.718ns (20.372%) route 6.714ns (79.628%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.938ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.938ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N7 0.000 0.000 r dip_sw[9] (IN) - net (fo=0) 0.000 0.000 dip_sw[9] - N7 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[9]_inst/O - net (fo=1, routed) 6.067 7.537 u_confreg/dip_sw_IBUF[9] - SLICE_X1Y80 LUT5 (Prop_lut5_I4_O) 0.124 7.661 r u_confreg/s_rdata[9]_i_4/O - net (fo=1, routed) 0.647 8.308 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 - SLICE_X1Y80 LUT6 (Prop_lut6_I4_O) 0.124 8.432 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O - net (fo=1, routed) 0.000 8.432 u_confreg/u_int_ctrl_n_22 - SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.890 -1.938 u_confreg/sys_clk - SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/C - -Slack: inf - Source: dip_sw[4] - (input port) - Destination: u_confreg/s_rdata_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.408ns (logic 1.736ns (20.649%) route 6.672ns (79.351%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.934ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.934ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P4 0.000 0.000 r dip_sw[4] (IN) - net (fo=0) 0.000 0.000 dip_sw[4] - P4 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[4]_inst/O - net (fo=1, routed) 6.006 7.495 u_confreg/dip_sw_IBUF[4] - SLICE_X2Y85 LUT5 (Prop_lut5_I4_O) 0.124 7.619 r u_confreg/s_rdata[4]_i_4/O - net (fo=1, routed) 0.666 8.284 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 - SLICE_X2Y83 LUT6 (Prop_lut6_I4_O) 0.124 8.408 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O - net (fo=1, routed) 0.000 8.408 u_confreg/u_int_ctrl_n_27 - SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.894 -1.934 u_confreg/sys_clk - SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/C - -Slack: inf - Source: dip_sw[10] - (input port) - Destination: u_confreg/s_rdata_reg[10]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.284ns (logic 1.720ns (20.765%) route 6.564ns (79.235%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M7 0.000 0.000 r dip_sw[10] (IN) - net (fo=0) 0.000 0.000 dip_sw[10] - M7 IBUF (Prop_ibuf_I_O) 1.472 1.472 r dip_sw_IBUF[10]_inst/O - net (fo=1, routed) 6.100 7.572 u_confreg/dip_sw_IBUF[10] - SLICE_X8Y80 LUT5 (Prop_lut5_I4_O) 0.124 7.696 r u_confreg/s_rdata[10]_i_4/O - net (fo=1, routed) 0.464 8.160 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 8.284 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O - net (fo=1, routed) 0.000 8.284 u_confreg/u_int_ctrl_n_21 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/C - -Slack: inf - Source: dip_sw[23] - (input port) - Destination: u_confreg/s_rdata_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.265ns (logic 1.766ns (21.372%) route 6.499ns (78.628%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.010ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N1 0.000 0.000 r dip_sw[23] (IN) - net (fo=0) 0.000 0.000 dip_sw[23] - N1 IBUF (Prop_ibuf_I_O) 1.518 1.518 r dip_sw_IBUF[23]_inst/O - net (fo=1, routed) 5.411 6.929 u_confreg/dip_sw_IBUF[23] - SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.124 7.053 r u_confreg/s_rdata[23]_i_4/O - net (fo=1, routed) 1.088 8.141 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 8.265 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O - net (fo=1, routed) 0.000 8.265 u_confreg/u_int_ctrl_n_8 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/C - -Slack: inf - Source: dip_sw[5] - (input port) - Destination: u_confreg/s_rdata_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.233ns (logic 1.718ns (20.872%) route 6.515ns (79.128%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L5 0.000 0.000 r dip_sw[5] (IN) - net (fo=0) 0.000 0.000 dip_sw[5] - L5 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[5]_inst/O - net (fo=1, routed) 5.514 6.985 u_confreg/dip_sw_IBUF[5] - SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.124 7.109 r u_confreg/s_rdata[5]_i_4/O - net (fo=1, routed) 1.000 8.109 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 8.233 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O - net (fo=1, routed) 0.000 8.233 u_confreg/u_int_ctrl_n_26 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/C - -Slack: inf - Source: dip_sw[26] - (input port) - Destination: u_confreg/s_rdata_reg[26]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.161ns (logic 1.757ns (21.535%) route 6.403ns (78.465%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.011ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T4 0.000 0.000 r dip_sw[26] (IN) - net (fo=0) 0.000 0.000 dip_sw[26] - T4 IBUF (Prop_ibuf_I_O) 1.509 1.509 r dip_sw_IBUF[26]_inst/O - net (fo=1, routed) 5.313 6.823 u_confreg/dip_sw_IBUF[26] - SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.947 r u_confreg/s_rdata[26]_i_4/O - net (fo=1, routed) 1.090 8.037 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 - SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.124 8.161 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O - net (fo=1, routed) 0.000 8.161 u_confreg/u_int_ctrl_n_5 - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 -2.011 u_confreg/sys_clk - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/C - -Slack: inf - Source: dip_sw[17] - (input port) - Destination: u_confreg/s_rdata_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.117ns (logic 1.752ns (21.585%) route 6.365ns (78.415%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K1 0.000 0.000 r dip_sw[17] (IN) - net (fo=0) 0.000 0.000 dip_sw[17] - K1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[17]_inst/O - net (fo=1, routed) 5.516 7.020 u_confreg/dip_sw_IBUF[17] - SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.124 7.144 r u_confreg/s_rdata[17]_i_4/O - net (fo=1, routed) 0.849 7.993 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.124 8.117 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O - net (fo=1, routed) 0.000 8.117 u_confreg/u_int_ctrl_n_14 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/C - -Slack: inf - Source: dip_sw[2] - (input port) - Destination: u_confreg/s_rdata_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.080ns (logic 1.743ns (21.573%) route 6.337ns (78.427%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M2 0.000 0.000 r dip_sw[2] (IN) - net (fo=0) 0.000 0.000 dip_sw[2] - M2 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[2]_inst/O - net (fo=1, routed) 5.346 6.841 u_confreg/dip_sw_IBUF[2] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.965 r u_confreg/s_rdata[2]_i_4/O - net (fo=1, routed) 0.991 7.956 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 8.080 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O - net (fo=1, routed) 0.000 8.080 u_confreg/u_int_ctrl_n_29 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/C - -Slack: inf - Source: dip_sw[6] - (input port) - Destination: u_confreg/s_rdata_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.077ns (logic 1.736ns (21.494%) route 6.341ns (78.506%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.936ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.936ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L3 0.000 0.000 r dip_sw[6] (IN) - net (fo=0) 0.000 0.000 dip_sw[6] - L3 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[6]_inst/O - net (fo=1, routed) 5.394 6.882 u_confreg/dip_sw_IBUF[6] - SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.124 7.006 r u_confreg/s_rdata[6]_i_4/O - net (fo=1, routed) 0.947 7.953 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 - SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.124 8.077 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O - net (fo=1, routed) 0.000 8.077 u_confreg/u_int_ctrl_n_25 - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.892 -1.936 u_confreg/sys_clk - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/C - -Slack: inf - Source: dip_sw[14] - (input port) - Destination: u_confreg/s_rdata_reg[14]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.038ns (logic 1.763ns (21.934%) route 6.275ns (78.066%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - J1 0.000 0.000 r dip_sw[14] (IN) - net (fo=0) 0.000 0.000 dip_sw[14] - J1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r dip_sw_IBUF[14]_inst/O - net (fo=1, routed) 5.331 6.846 u_confreg/dip_sw_IBUF[14] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.970 r u_confreg/s_rdata[14]_i_4/O - net (fo=1, routed) 0.944 7.914 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 8.038 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O - net (fo=1, routed) 0.000 8.038 u_confreg/u_int_ctrl_n_17 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/C - -Slack: inf - Source: dip_sw[15] - (input port) - Destination: u_confreg/s_rdata_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.951ns (logic 1.742ns (21.911%) route 6.209ns (78.089%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L2 0.000 0.000 r dip_sw[15] (IN) - net (fo=0) 0.000 0.000 dip_sw[15] - L2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[15]_inst/O - net (fo=1, routed) 5.453 6.948 u_confreg/dip_sw_IBUF[15] - SLICE_X1Y95 LUT5 (Prop_lut5_I4_O) 0.124 7.072 r u_confreg/s_rdata[15]_i_4/O - net (fo=1, routed) 0.755 7.827 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.951 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O - net (fo=1, routed) 0.000 7.951 u_confreg/u_int_ctrl_n_16 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/C - -Slack: inf - Source: dip_sw[0] - (input port) - Destination: u_confreg/s_rdata_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.807ns (logic 1.743ns (22.326%) route 6.064ns (77.674%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.937ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.937ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T3 0.000 0.000 r dip_sw[0] (IN) - net (fo=0) 0.000 0.000 dip_sw[0] - T3 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[0]_inst/O - net (fo=1, routed) 5.166 6.661 u_confreg/dip_sw_IBUF[0] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.785 r u_confreg/s_rdata[0]_i_4/O - net (fo=1, routed) 0.898 7.683 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 - SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.124 7.807 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O - net (fo=1, routed) 0.000 7.807 u_confreg/u_int_ctrl_n_31 - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.891 -1.937 u_confreg/sys_clk - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/C - -Slack: inf - Source: dip_sw[3] - (input port) - Destination: u_confreg/s_rdata_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.770ns (logic 1.752ns (22.553%) route 6.018ns (77.447%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.940ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.940ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P1 0.000 0.000 r dip_sw[3] (IN) - net (fo=0) 0.000 0.000 dip_sw[3] - P1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[3]_inst/O - net (fo=1, routed) 5.171 6.676 u_confreg/dip_sw_IBUF[3] - SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.800 r u_confreg/s_rdata[3]_i_4/O - net (fo=1, routed) 0.846 7.646 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 - SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.124 7.770 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O - net (fo=1, routed) 0.000 7.770 u_confreg/u_int_ctrl_n_28 - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.888 -1.940 u_confreg/sys_clk - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/C - -Slack: inf - Source: dip_sw[21] - (input port) - Destination: u_confreg/s_rdata_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.691ns (logic 1.736ns (22.574%) route 5.955ns (77.426%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.010ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N2 0.000 0.000 r dip_sw[21] (IN) - net (fo=0) 0.000 0.000 dip_sw[21] - N2 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[21]_inst/O - net (fo=1, routed) 5.069 6.557 u_confreg/dip_sw_IBUF[21] - SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.681 r u_confreg/s_rdata[21]_i_4/O - net (fo=1, routed) 0.886 7.567 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.691 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O - net (fo=1, routed) 0.000 7.691 u_confreg/u_int_ctrl_n_10 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/C - -Slack: inf - Source: dip_sw[16] - (input port) - Destination: u_confreg/s_rdata_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.536ns (logic 1.748ns (23.196%) route 5.788ns (76.804%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K2 0.000 0.000 r dip_sw[16] (IN) - net (fo=0) 0.000 0.000 dip_sw[16] - K2 IBUF (Prop_ibuf_I_O) 1.500 1.500 r dip_sw_IBUF[16]_inst/O - net (fo=1, routed) 5.492 6.993 u_confreg/dip_sw_IBUF[16] - SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.124 7.117 r u_confreg/s_rdata[16]_i_4/O - net (fo=1, routed) 0.296 7.412 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.536 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O - net (fo=1, routed) 0.000 7.536 u_confreg/u_int_ctrl_n_15 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/C - -Slack: inf - Source: dip_sw[24] - (input port) - Destination: u_confreg/s_rdata_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.500ns (logic 1.714ns (22.860%) route 5.785ns (77.140%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P5 0.000 0.000 r dip_sw[24] (IN) - net (fo=0) 0.000 0.000 dip_sw[24] - P5 IBUF (Prop_ibuf_I_O) 1.466 1.466 r dip_sw_IBUF[24]_inst/O - net (fo=1, routed) 4.979 6.445 u_confreg/dip_sw_IBUF[24] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.569 r u_confreg/s_rdata[24]_i_4/O - net (fo=1, routed) 0.806 7.376 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.500 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O - net (fo=1, routed) 0.000 7.500 u_confreg/u_int_ctrl_n_7 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/C - -Slack: inf - Source: dip_sw[18] - (input port) - Destination: u_confreg/s_rdata_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.469ns (logic 1.737ns (23.257%) route 5.732ns (76.743%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.011ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N3 0.000 0.000 r dip_sw[18] (IN) - net (fo=0) 0.000 0.000 dip_sw[18] - N3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[18]_inst/O - net (fo=1, routed) 5.052 6.541 u_confreg/dip_sw_IBUF[18] - SLICE_X8Y87 LUT5 (Prop_lut5_I4_O) 0.124 6.665 r u_confreg/s_rdata[18]_i_4/O - net (fo=1, routed) 0.680 7.345 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 - SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.124 7.469 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O - net (fo=1, routed) 0.000 7.469 u_confreg/u_int_ctrl_n_13 - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 -2.011 u_confreg/sys_clk - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/C - -Slack: inf - Source: dip_sw[7] - (input port) - Destination: u_confreg/s_rdata_reg[7]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.415ns (logic 1.719ns (23.186%) route 5.696ns (76.814%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.933ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.933ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N6 0.000 0.000 r dip_sw[7] (IN) - net (fo=0) 0.000 0.000 dip_sw[7] - N6 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[7]_inst/O - net (fo=1, routed) 5.542 7.013 u_confreg/dip_sw_IBUF[7] - SLICE_X1Y84 LUT5 (Prop_lut5_I4_O) 0.124 7.137 r u_confreg/s_rdata[7]_i_4/O - net (fo=1, routed) 0.154 7.291 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 - SLICE_X1Y84 LUT6 (Prop_lut6_I4_O) 0.124 7.415 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O - net (fo=1, routed) 0.000 7.415 u_confreg/u_int_ctrl_n_24 - SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.895 -1.933 u_confreg/sys_clk - SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/C - -Slack: inf - Source: dip_sw[12] - (input port) - Destination: u_confreg/s_rdata_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.331ns (logic 1.717ns (23.423%) route 5.614ns (76.577%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.936ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.936ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M5 0.000 0.000 r dip_sw[12] (IN) - net (fo=0) 0.000 0.000 dip_sw[12] - M5 IBUF (Prop_ibuf_I_O) 1.469 1.469 r dip_sw_IBUF[12]_inst/O - net (fo=1, routed) 5.177 6.646 u_confreg/dip_sw_IBUF[12] - SLICE_X5Y86 LUT5 (Prop_lut5_I4_O) 0.124 6.770 r u_confreg/s_rdata[12]_i_4/O - net (fo=1, routed) 0.437 7.207 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 - SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.124 7.331 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O - net (fo=1, routed) 0.000 7.331 u_confreg/u_int_ctrl_n_19 - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.892 -1.936 u_confreg/sys_clk - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/C - -Slack: inf - Source: dip_sw[30] - (input port) - Destination: u_confreg/s_rdata_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.316ns (logic 1.707ns (23.334%) route 5.609ns (76.666%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.930ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.930ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R6 0.000 0.000 r dip_sw[30] (IN) - net (fo=0) 0.000 0.000 dip_sw[30] - R6 IBUF (Prop_ibuf_I_O) 1.459 1.459 r dip_sw_IBUF[30]_inst/O - net (fo=1, routed) 4.515 5.975 u_confreg/dip_sw_IBUF[30] - SLICE_X2Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.099 r u_confreg/s_rdata[30]_i_4/O - net (fo=1, routed) 1.093 7.192 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 - SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.316 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O - net (fo=1, routed) 0.000 7.316 u_confreg/u_int_ctrl_n_1 - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.898 -1.930 u_confreg/sys_clk - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/C - -Slack: inf - Source: dip_sw[29] - (input port) - Destination: u_confreg/s_rdata_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.273ns (logic 1.726ns (23.732%) route 5.547ns (76.268%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.930ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.930ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T5 0.000 0.000 r dip_sw[29] (IN) - net (fo=0) 0.000 0.000 dip_sw[29] - T5 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[29]_inst/O - net (fo=1, routed) 4.537 6.015 u_confreg/dip_sw_IBUF[29] - SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.124 6.139 r u_confreg/s_rdata[29]_i_4/O - net (fo=1, routed) 1.010 7.149 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 - SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.273 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O - net (fo=1, routed) 0.000 7.273 u_confreg/u_int_ctrl_n_2 - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.898 -1.930 u_confreg/sys_clk - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/C - -Slack: inf - Source: touch_btn[3] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.267ns (logic 1.513ns (20.816%) route 5.755ns (79.184%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -1.938ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.938ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - U2 0.000 0.000 r touch_btn[3] (IN) - net (fo=0) 0.000 0.000 touch_btn[3] - U2 IBUF (Prop_ibuf_I_O) 1.513 1.513 r touch_btn_IBUF[3]_inst/O - net (fo=1, routed) 5.755 7.267 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] - SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.890 -1.938 u_confreg/u_int_ctrl/sys_clk - SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C - -Slack: inf - Source: touch_btn[1] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.239ns (logic 1.515ns (20.930%) route 5.724ns (79.070%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -2.009ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M1 0.000 0.000 r touch_btn[1] (IN) - net (fo=0) 0.000 0.000 touch_btn[1] - M1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r touch_btn_IBUF[1]_inst/O - net (fo=1, routed) 5.724 7.239 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.819 -2.009 u_confreg/u_int_ctrl/sys_clk - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C - -Slack: inf - Source: dip_sw[28] - (input port) - Destination: u_confreg/s_rdata_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.116ns (logic 1.716ns (24.110%) route 5.400ns (75.890%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R5 0.000 0.000 r dip_sw[28] (IN) - net (fo=0) 0.000 0.000 dip_sw[28] - R5 IBUF (Prop_ibuf_I_O) 1.468 1.468 r dip_sw_IBUF[28]_inst/O - net (fo=1, routed) 4.960 6.427 u_confreg/dip_sw_IBUF[28] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.551 r u_confreg/s_rdata[28]_i_4/O - net (fo=1, routed) 0.440 6.992 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.116 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O - net (fo=1, routed) 0.000 7.116 u_confreg/u_int_ctrl_n_3 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/C - Slack: inf Source: dip_sw[22] (input port) @@ -38075,10 +36181,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.094ns (logic 1.710ns (24.108%) route 5.384ns (75.892%)) + Data Path Delay: 8.330ns (logic 1.710ns (20.531%) route 6.620ns (79.469%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.932ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.932ns + Clock Path Skew: -2.277ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -38087,12 +36193,12 @@ Slack: inf P6 0.000 0.000 r dip_sw[22] (IN) net (fo=0) 0.000 0.000 dip_sw[22] P6 IBUF (Prop_ibuf_I_O) 1.462 1.462 r dip_sw_IBUF[22]_inst/O - net (fo=1, routed) 4.542 6.004 u_confreg/dip_sw_IBUF[22] - SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.124 6.128 r u_confreg/s_rdata[22]_i_4/O - net (fo=1, routed) 0.842 6.970 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 - SLICE_X4Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.094 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O - net (fo=1, routed) 0.000 7.094 u_confreg/u_int_ctrl_n_9 - SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/D + net (fo=1, routed) 5.658 7.120 u_confreg/dip_sw_IBUF[22] + SLICE_X58Y140 LUT5 (Prop_lut5_I4_O) 0.124 7.244 r u_confreg/s_rdata[22]_i_4/O + net (fo=1, routed) 0.963 8.206 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 + SLICE_X52Y140 LUT6 (Prop_lut6_I4_O) 0.124 8.330 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O + net (fo=1, routed) 0.000 8.330 u_confreg/u_int_ctrl_n_9 + SLICE_X52Y140 FDRE r u_confreg/s_rdata_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38104,8 +36210,86 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.896 -1.932 u_confreg/sys_clk - SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/C + net (fo=9971, routed) 1.551 -2.277 u_confreg/sys_clk + SLICE_X52Y140 FDRE r u_confreg/s_rdata_reg[22]/C + +Slack: inf + Source: dip_sw[29] + (input port) + Destination: u_confreg/s_rdata_reg[29]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.156ns (logic 1.726ns (21.164%) route 6.430ns (78.836%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.278ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T5 0.000 0.000 r dip_sw[29] (IN) + net (fo=0) 0.000 0.000 dip_sw[29] + T5 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[29]_inst/O + net (fo=1, routed) 5.466 6.944 u_confreg/dip_sw_IBUF[29] + SLICE_X60Y139 LUT5 (Prop_lut5_I4_O) 0.124 7.068 r u_confreg/s_rdata[29]_i_4/O + net (fo=1, routed) 0.963 8.032 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 + SLICE_X57Y140 LUT6 (Prop_lut6_I4_O) 0.124 8.156 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O + net (fo=1, routed) 0.000 8.156 u_confreg/u_int_ctrl_n_2 + SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk + SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[29]/C + +Slack: inf + Source: dip_sw[19] + (input port) + Destination: u_confreg/s_rdata_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.100ns (logic 1.726ns (21.311%) route 6.374ns (78.689%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L4 0.000 0.000 r dip_sw[19] (IN) + net (fo=0) 0.000 0.000 dip_sw[19] + L4 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[19]_inst/O + net (fo=1, routed) 5.423 6.901 u_confreg/dip_sw_IBUF[19] + SLICE_X54Y136 LUT5 (Prop_lut5_I4_O) 0.124 7.025 r u_confreg/s_rdata[19]_i_4/O + net (fo=1, routed) 0.951 7.976 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 + SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.124 8.100 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O + net (fo=1, routed) 0.000 8.100 u_confreg/u_int_ctrl_n_12 + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[19]/C Slack: inf Source: UART_TX @@ -38114,10 +36298,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.945ns (logic 1.963ns (28.269%) route 4.982ns (71.731%)) + Data Path Delay: 7.928ns (logic 1.980ns (24.979%) route 5.948ns (75.021%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) - Clock Path Skew: -1.929ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.929ns + Clock Path Skew: -2.306ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -38126,12 +36310,12 @@ Slack: inf H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 3.916 5.391 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.117 5.508 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O - net (fo=2, routed) 0.683 6.191 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 - SLICE_X2Y60 LUT5 (Prop_lut5_I1_O) 0.372 6.563 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O - net (fo=1, routed) 0.382 6.945 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D + net (fo=4, routed) 5.067 6.541 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X79Y136 LUT2 (Prop_lut2_I1_O) 0.152 6.693 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O + net (fo=2, routed) 0.881 7.574 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 + SLICE_X78Y136 LUT5 (Prop_lut5_I1_O) 0.354 7.928 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O + net (fo=1, routed) 0.000 7.928 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 + SLICE_X78Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38143,8 +36327,47 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.899 -1.929 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C + net (fo=9971, routed) 1.522 -2.306 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X78Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C + +Slack: inf + Source: dip_sw[14] + (input port) + Destination: u_confreg/s_rdata_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.857ns (logic 1.763ns (22.438%) route 6.094ns (77.562%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + J1 0.000 0.000 r dip_sw[14] (IN) + net (fo=0) 0.000 0.000 dip_sw[14] + J1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r dip_sw_IBUF[14]_inst/O + net (fo=1, routed) 4.730 6.245 u_confreg/dip_sw_IBUF[14] + SLICE_X62Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.369 r u_confreg/s_rdata[14]_i_4/O + net (fo=1, routed) 1.365 7.733 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 + SLICE_X49Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.857 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O + net (fo=1, routed) 0.000 7.857 u_confreg/u_int_ctrl_n_17 + SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[14]/C Slack: inf Source: dip_sw[27] @@ -38153,10 +36376,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.892ns (logic 1.753ns (25.432%) route 5.139ns (74.568%)) + Data Path Delay: 7.823ns (logic 1.753ns (22.406%) route 6.070ns (77.594%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.010ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -38165,12 +36388,12 @@ Slack: inf R1 0.000 0.000 r dip_sw[27] (IN) net (fo=0) 0.000 0.000 dip_sw[27] R1 IBUF (Prop_ibuf_I_O) 1.505 1.505 r dip_sw_IBUF[27]_inst/O - net (fo=1, routed) 4.238 5.743 u_confreg/dip_sw_IBUF[27] - SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.124 5.867 r u_confreg/s_rdata[27]_i_4/O - net (fo=1, routed) 0.902 6.768 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 6.892 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O - net (fo=1, routed) 0.000 6.892 u_confreg/u_int_ctrl_n_4 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/D + net (fo=1, routed) 4.956 6.461 u_confreg/dip_sw_IBUF[27] + SLICE_X61Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.585 r u_confreg/s_rdata[27]_i_4/O + net (fo=1, routed) 1.114 7.699 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 + SLICE_X50Y137 LUT6 (Prop_lut6_I4_O) 0.124 7.823 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O + net (fo=1, routed) 0.000 7.823 u_confreg/u_int_ctrl_n_4 + SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38182,34 +36405,34 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/C + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[27]/C Slack: inf - Source: dip_sw[31] + Source: dip_sw[15] (input port) - Destination: u_confreg/s_rdata_reg[31]/D + Destination: u_confreg/s_rdata_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.857ns (logic 1.742ns (25.399%) route 5.116ns (74.601%)) + Data Path Delay: 7.701ns (logic 1.742ns (22.623%) route 5.959ns (77.377%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.932ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.932ns + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - R2 0.000 0.000 r dip_sw[31] (IN) - net (fo=0) 0.000 0.000 dip_sw[31] - R2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[31]_inst/O - net (fo=1, routed) 4.636 6.130 u_confreg/dip_sw_IBUF[31] - SLICE_X2Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.254 r u_confreg/s_rdata[31]_i_6/O - net (fo=1, routed) 0.480 6.733 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 - SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.124 6.857 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O - net (fo=1, routed) 0.000 6.857 u_confreg/u_int_ctrl_n_0 - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/D + L2 0.000 0.000 r dip_sw[15] (IN) + net (fo=0) 0.000 0.000 dip_sw[15] + L2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[15]_inst/O + net (fo=1, routed) 5.004 6.498 u_confreg/dip_sw_IBUF[15] + SLICE_X58Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.622 r u_confreg/s_rdata[15]_i_4/O + net (fo=1, routed) 0.955 7.577 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 + SLICE_X49Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.701 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O + net (fo=1, routed) 0.000 7.701 u_confreg/u_int_ctrl_n_16 + SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38221,8 +36444,515 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.896 -1.932 u_confreg/sys_clk - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/C + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[15]/C + +Slack: inf + Source: dip_sw[7] + (input port) + Destination: u_confreg/s_rdata_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.567ns (logic 1.719ns (22.721%) route 5.848ns (77.279%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.286ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.286ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N6 0.000 0.000 r dip_sw[7] (IN) + net (fo=0) 0.000 0.000 dip_sw[7] + N6 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[7]_inst/O + net (fo=1, routed) 4.586 6.058 u_confreg/dip_sw_IBUF[7] + SLICE_X66Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.182 r u_confreg/s_rdata[7]_i_4/O + net (fo=1, routed) 1.261 7.443 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 + SLICE_X56Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.567 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O + net (fo=1, routed) 0.000 7.567 u_confreg/u_int_ctrl_n_24 + SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk + SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[7]/C + +Slack: inf + Source: dip_sw[12] + (input port) + Destination: u_confreg/s_rdata_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.550ns (logic 1.717ns (22.743%) route 5.833ns (77.257%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M5 0.000 0.000 r dip_sw[12] (IN) + net (fo=0) 0.000 0.000 dip_sw[12] + M5 IBUF (Prop_ibuf_I_O) 1.469 1.469 r dip_sw_IBUF[12]_inst/O + net (fo=1, routed) 4.809 6.278 u_confreg/dip_sw_IBUF[12] + SLICE_X59Y137 LUT5 (Prop_lut5_I4_O) 0.124 6.402 r u_confreg/s_rdata[12]_i_4/O + net (fo=1, routed) 1.024 7.426 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 + SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.550 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O + net (fo=1, routed) 0.000 7.550 u_confreg/u_int_ctrl_n_19 + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[12]/C + +Slack: inf + Source: dip_sw[16] + (input port) + Destination: u_confreg/s_rdata_reg[16]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.532ns (logic 1.748ns (23.209%) route 5.784ns (76.791%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K2 0.000 0.000 r dip_sw[16] (IN) + net (fo=0) 0.000 0.000 dip_sw[16] + K2 IBUF (Prop_ibuf_I_O) 1.500 1.500 r dip_sw_IBUF[16]_inst/O + net (fo=1, routed) 4.874 6.374 u_confreg/dip_sw_IBUF[16] + SLICE_X62Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.498 r u_confreg/s_rdata[16]_i_4/O + net (fo=1, routed) 0.910 7.408 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 + SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.532 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O + net (fo=1, routed) 0.000 7.532 u_confreg/u_int_ctrl_n_15 + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[16]/C + +Slack: inf + Source: dip_sw[25] + (input port) + Destination: u_confreg/s_rdata_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.498ns (logic 1.737ns (23.169%) route 5.761ns (76.831%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.278ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R3 0.000 0.000 r dip_sw[25] (IN) + net (fo=0) 0.000 0.000 dip_sw[25] + R3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[25]_inst/O + net (fo=1, routed) 5.036 6.525 u_confreg/dip_sw_IBUF[25] + SLICE_X55Y138 LUT5 (Prop_lut5_I4_O) 0.124 6.649 r u_confreg/s_rdata[25]_i_4/O + net (fo=1, routed) 0.725 7.374 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 + SLICE_X51Y138 LUT6 (Prop_lut6_I4_O) 0.124 7.498 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O + net (fo=1, routed) 0.000 7.498 u_confreg/u_int_ctrl_n_6 + SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk + SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[25]/C + +Slack: inf + Source: dip_sw[24] + (input port) + Destination: u_confreg/s_rdata_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.497ns (logic 1.714ns (22.868%) route 5.783ns (77.132%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.277ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P5 0.000 0.000 r dip_sw[24] (IN) + net (fo=0) 0.000 0.000 dip_sw[24] + P5 IBUF (Prop_ibuf_I_O) 1.466 1.466 r dip_sw_IBUF[24]_inst/O + net (fo=1, routed) 5.182 6.648 u_confreg/dip_sw_IBUF[24] + SLICE_X55Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.772 r u_confreg/s_rdata[24]_i_4/O + net (fo=1, routed) 0.601 7.373 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 + SLICE_X52Y139 LUT6 (Prop_lut6_I4_O) 0.124 7.497 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O + net (fo=1, routed) 0.000 7.497 u_confreg/u_int_ctrl_n_7 + SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.551 -2.277 u_confreg/sys_clk + SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[24]/C + +Slack: inf + Source: dip_sw[4] + (input port) + Destination: u_confreg/s_rdata_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.485ns (logic 1.736ns (23.197%) route 5.748ns (76.803%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.281ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P4 0.000 0.000 r dip_sw[4] (IN) + net (fo=0) 0.000 0.000 dip_sw[4] + P4 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[4]_inst/O + net (fo=1, routed) 4.844 6.332 u_confreg/dip_sw_IBUF[4] + SLICE_X63Y134 LUT5 (Prop_lut5_I4_O) 0.124 6.456 r u_confreg/s_rdata[4]_i_4/O + net (fo=1, routed) 0.904 7.361 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 + SLICE_X55Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.485 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O + net (fo=1, routed) 0.000 7.485 u_confreg/u_int_ctrl_n_27 + SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.547 -2.281 u_confreg/sys_clk + SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[4]/C + +Slack: inf + Source: dip_sw[8] + (input port) + Destination: u_confreg/s_rdata_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.481ns (logic 1.724ns (23.040%) route 5.758ns (76.960%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.286ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.286ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M6 0.000 0.000 r dip_sw[8] (IN) + net (fo=0) 0.000 0.000 dip_sw[8] + M6 IBUF (Prop_ibuf_I_O) 1.476 1.476 r dip_sw_IBUF[8]_inst/O + net (fo=1, routed) 4.998 6.474 u_confreg/dip_sw_IBUF[8] + SLICE_X61Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.598 r u_confreg/s_rdata[8]_i_4/O + net (fo=1, routed) 0.760 7.357 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 + SLICE_X59Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.481 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O + net (fo=1, routed) 0.000 7.481 u_confreg/u_int_ctrl_n_23 + SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk + SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[8]/C + +Slack: inf + Source: dip_sw[20] + (input port) + Destination: u_confreg/s_rdata_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.437ns (logic 1.723ns (23.170%) route 5.714ns (76.830%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.278ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M4 0.000 0.000 r dip_sw[20] (IN) + net (fo=0) 0.000 0.000 dip_sw[20] + M4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r dip_sw_IBUF[20]_inst/O + net (fo=1, routed) 4.743 6.219 u_confreg/dip_sw_IBUF[20] + SLICE_X54Y140 LUT5 (Prop_lut5_I4_O) 0.124 6.343 r u_confreg/s_rdata[20]_i_4/O + net (fo=1, routed) 0.970 7.313 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 + SLICE_X50Y138 LUT6 (Prop_lut6_I4_O) 0.124 7.437 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O + net (fo=1, routed) 0.000 7.437 u_confreg/u_int_ctrl_n_11 + SLICE_X50Y138 FDRE r u_confreg/s_rdata_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk + SLICE_X50Y138 FDRE r u_confreg/s_rdata_reg[20]/C + +Slack: inf + Source: dip_sw[6] + (input port) + Destination: u_confreg/s_rdata_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.429ns (logic 1.736ns (23.368%) route 5.693ns (76.632%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.284ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L3 0.000 0.000 r dip_sw[6] (IN) + net (fo=0) 0.000 0.000 dip_sw[6] + L3 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[6]_inst/O + net (fo=1, routed) 4.696 6.184 u_confreg/dip_sw_IBUF[6] + SLICE_X65Y134 LUT5 (Prop_lut5_I4_O) 0.124 6.308 r u_confreg/s_rdata[6]_i_4/O + net (fo=1, routed) 0.997 7.305 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 + SLICE_X57Y132 LUT6 (Prop_lut6_I4_O) 0.124 7.429 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O + net (fo=1, routed) 0.000 7.429 u_confreg/u_int_ctrl_n_25 + SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.544 -2.284 u_confreg/sys_clk + SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[6]/C + +Slack: inf + Source: dip_sw[13] + (input port) + Destination: u_confreg/s_rdata_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.400ns (logic 1.734ns (23.431%) route 5.666ns (76.569%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.283ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.283ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K3 0.000 0.000 r dip_sw[13] (IN) + net (fo=0) 0.000 0.000 dip_sw[13] + K3 IBUF (Prop_ibuf_I_O) 1.486 1.486 r dip_sw_IBUF[13]_inst/O + net (fo=1, routed) 5.048 6.534 u_confreg/dip_sw_IBUF[13] + SLICE_X58Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.658 r u_confreg/s_rdata[13]_i_4/O + net (fo=1, routed) 0.618 7.276 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 + SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.124 7.400 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O + net (fo=1, routed) 0.000 7.400 u_confreg/u_int_ctrl_n_18 + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.545 -2.283 u_confreg/sys_clk + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[13]/C + +Slack: inf + Source: dip_sw[21] + (input port) + Destination: u_confreg/s_rdata_reg[21]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.324ns (logic 1.736ns (23.706%) route 5.588ns (76.294%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.278ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N2 0.000 0.000 r dip_sw[21] (IN) + net (fo=0) 0.000 0.000 dip_sw[21] + N2 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[21]_inst/O + net (fo=1, routed) 5.103 6.592 u_confreg/dip_sw_IBUF[21] + SLICE_X57Y138 LUT5 (Prop_lut5_I4_O) 0.124 6.716 r u_confreg/s_rdata[21]_i_4/O + net (fo=1, routed) 0.484 7.200 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 + SLICE_X51Y138 LUT6 (Prop_lut6_I4_O) 0.124 7.324 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O + net (fo=1, routed) 0.000 7.324 u_confreg/u_int_ctrl_n_10 + SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk + SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[21]/C + +Slack: inf + Source: dip_sw[2] + (input port) + Destination: u_confreg/s_rdata_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.267ns (logic 1.743ns (23.989%) route 5.524ns (76.011%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.286ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.286ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M2 0.000 0.000 r dip_sw[2] (IN) + net (fo=0) 0.000 0.000 dip_sw[2] + M2 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[2]_inst/O + net (fo=1, routed) 4.493 5.988 u_confreg/dip_sw_IBUF[2] + SLICE_X66Y131 LUT5 (Prop_lut5_I4_O) 0.124 6.112 r u_confreg/s_rdata[2]_i_4/O + net (fo=1, routed) 1.030 7.143 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 + SLICE_X56Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.267 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O + net (fo=1, routed) 0.000 7.267 u_confreg/u_int_ctrl_n_29 + SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk + SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[2]/C + +Slack: inf + Source: dip_sw[0] + (input port) + Destination: u_confreg/s_rdata_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.201ns (logic 1.743ns (24.206%) route 5.458ns (75.794%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.283ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.283ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T3 0.000 0.000 r dip_sw[0] (IN) + net (fo=0) 0.000 0.000 dip_sw[0] + T3 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[0]_inst/O + net (fo=1, routed) 4.700 6.196 u_confreg/dip_sw_IBUF[0] + SLICE_X62Y133 LUT5 (Prop_lut5_I4_O) 0.124 6.320 r u_confreg/s_rdata[0]_i_4/O + net (fo=1, routed) 0.758 7.077 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 + SLICE_X60Y133 LUT6 (Prop_lut6_I4_O) 0.124 7.201 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O + net (fo=1, routed) 0.000 7.201 u_confreg/u_int_ctrl_n_31 + SLICE_X60Y133 FDRE r u_confreg/s_rdata_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.545 -2.283 u_confreg/sys_clk + SLICE_X60Y133 FDRE r u_confreg/s_rdata_reg[0]/C Slack: inf Source: UART_TX @@ -38231,10 +36961,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.182ns (logic 1.939ns (31.371%) route 4.243ns (68.629%)) + Data Path Delay: 7.187ns (logic 1.952ns (27.163%) route 5.235ns (72.837%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) - Clock Path Skew: -1.930ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.930ns + Clock Path Skew: -2.306ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -38243,12 +36973,12 @@ Slack: inf H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 3.916 5.391 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.117 5.508 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O - net (fo=2, routed) 0.326 5.834 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 - SLICE_X2Y61 LUT6 (Prop_lut6_I2_O) 0.348 6.182 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O - net (fo=1, routed) 0.000 6.182 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 - SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D + net (fo=4, routed) 5.067 6.541 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X79Y136 LUT2 (Prop_lut2_I1_O) 0.152 6.693 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O + net (fo=2, routed) 0.169 6.861 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 + SLICE_X79Y136 LUT6 (Prop_lut6_I2_O) 0.326 7.187 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O + net (fo=1, routed) 0.000 7.187 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 + SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38260,8 +36990,320 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.898 -1.930 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C + net (fo=9971, routed) 1.522 -2.306 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C + +Slack: inf + Source: dip_sw[5] + (input port) + Destination: u_confreg/s_rdata_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.162ns (logic 1.718ns (23.993%) route 5.444ns (76.007%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.280ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L5 0.000 0.000 r dip_sw[5] (IN) + net (fo=0) 0.000 0.000 dip_sw[5] + L5 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[5]_inst/O + net (fo=1, routed) 4.578 6.048 u_confreg/dip_sw_IBUF[5] + SLICE_X66Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.172 r u_confreg/s_rdata[5]_i_4/O + net (fo=1, routed) 0.866 7.038 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 + SLICE_X57Y137 LUT6 (Prop_lut6_I4_O) 0.124 7.162 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O + net (fo=1, routed) 0.000 7.162 u_confreg/u_int_ctrl_n_26 + SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.548 -2.280 u_confreg/sys_clk + SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[5]/C + +Slack: inf + Source: dip_sw[18] + (input port) + Destination: u_confreg/s_rdata_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.118ns (logic 1.737ns (24.404%) route 5.381ns (75.596%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.285ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.285ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N3 0.000 0.000 r dip_sw[18] (IN) + net (fo=0) 0.000 0.000 dip_sw[18] + N3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[18]_inst/O + net (fo=1, routed) 4.773 6.262 u_confreg/dip_sw_IBUF[18] + SLICE_X61Y129 LUT5 (Prop_lut5_I4_O) 0.124 6.386 r u_confreg/s_rdata[18]_i_4/O + net (fo=1, routed) 0.608 6.994 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 + SLICE_X48Y129 LUT6 (Prop_lut6_I4_O) 0.124 7.118 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O + net (fo=1, routed) 0.000 7.118 u_confreg/u_int_ctrl_n_13 + SLICE_X48Y129 FDRE r u_confreg/s_rdata_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.543 -2.285 u_confreg/sys_clk + SLICE_X48Y129 FDRE r u_confreg/s_rdata_reg[18]/C + +Slack: inf + Source: dip_sw[3] + (input port) + Destination: u_confreg/s_rdata_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.054ns (logic 1.752ns (24.843%) route 5.301ns (75.157%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.286ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.286ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P1 0.000 0.000 r dip_sw[3] (IN) + net (fo=0) 0.000 0.000 dip_sw[3] + P1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[3]_inst/O + net (fo=1, routed) 4.499 6.003 u_confreg/dip_sw_IBUF[3] + SLICE_X63Y131 LUT5 (Prop_lut5_I4_O) 0.124 6.127 r u_confreg/s_rdata[3]_i_4/O + net (fo=1, routed) 0.802 6.930 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 + SLICE_X59Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.054 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O + net (fo=1, routed) 0.000 7.054 u_confreg/u_int_ctrl_n_28 + SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk + SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[3]/C + +Slack: inf + Source: dip_sw[10] + (input port) + Destination: u_confreg/s_rdata_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.934ns (logic 1.720ns (24.809%) route 5.214ns (75.191%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.281ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.281ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M7 0.000 0.000 r dip_sw[10] (IN) + net (fo=0) 0.000 0.000 dip_sw[10] + M7 IBUF (Prop_ibuf_I_O) 1.472 1.472 r dip_sw_IBUF[10]_inst/O + net (fo=1, routed) 3.839 5.312 u_confreg/dip_sw_IBUF[10] + SLICE_X62Y139 LUT5 (Prop_lut5_I4_O) 0.124 5.436 r u_confreg/s_rdata[10]_i_4/O + net (fo=1, routed) 1.374 6.810 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 + SLICE_X55Y135 LUT6 (Prop_lut6_I4_O) 0.124 6.934 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O + net (fo=1, routed) 0.000 6.934 u_confreg/u_int_ctrl_n_21 + SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.547 -2.281 u_confreg/sys_clk + SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[10]/C + +Slack: inf + Source: dip_sw[26] + (input port) + Destination: u_confreg/s_rdata_reg[26]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.933ns (logic 1.757ns (25.349%) route 5.175ns (74.651%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T4 0.000 0.000 r dip_sw[26] (IN) + net (fo=0) 0.000 0.000 dip_sw[26] + T4 IBUF (Prop_ibuf_I_O) 1.509 1.509 r dip_sw_IBUF[26]_inst/O + net (fo=1, routed) 4.385 5.894 u_confreg/dip_sw_IBUF[26] + SLICE_X52Y137 LUT5 (Prop_lut5_I4_O) 0.124 6.018 r u_confreg/s_rdata[26]_i_4/O + net (fo=1, routed) 0.790 6.809 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 + SLICE_X50Y137 LUT6 (Prop_lut6_I4_O) 0.124 6.933 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O + net (fo=1, routed) 0.000 6.933 u_confreg/u_int_ctrl_n_5 + SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[26]/C + +Slack: inf + Source: dip_sw[1] + (input port) + Destination: u_confreg/s_rdata_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.900ns (logic 1.746ns (25.302%) route 5.154ns (74.698%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.283ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.283ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + J3 0.000 0.000 r dip_sw[1] (IN) + net (fo=0) 0.000 0.000 dip_sw[1] + J3 IBUF (Prop_ibuf_I_O) 1.498 1.498 r dip_sw_IBUF[1]_inst/O + net (fo=1, routed) 4.204 5.702 u_confreg/dip_sw_IBUF[1] + SLICE_X66Y141 LUT5 (Prop_lut5_I4_O) 0.124 5.826 r u_confreg/s_rdata[1]_i_4/O + net (fo=1, routed) 0.950 6.776 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 + SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.124 6.900 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O + net (fo=1, routed) 0.000 6.900 u_confreg/u_int_ctrl_n_30 + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.545 -2.283 u_confreg/sys_clk + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[1]/C + +Slack: inf + Source: dip_sw[30] + (input port) + Destination: u_confreg/s_rdata_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.720ns (logic 1.707ns (25.404%) route 5.013ns (74.596%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.278ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.278ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R6 0.000 0.000 r dip_sw[30] (IN) + net (fo=0) 0.000 0.000 dip_sw[30] + R6 IBUF (Prop_ibuf_I_O) 1.459 1.459 r dip_sw_IBUF[30]_inst/O + net (fo=1, routed) 4.861 6.320 u_confreg/dip_sw_IBUF[30] + SLICE_X57Y140 LUT5 (Prop_lut5_I4_O) 0.124 6.444 r u_confreg/s_rdata[30]_i_4/O + net (fo=1, routed) 0.151 6.596 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 + SLICE_X57Y140 LUT6 (Prop_lut6_I4_O) 0.124 6.720 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O + net (fo=1, routed) 0.000 6.720 u_confreg/u_int_ctrl_n_1 + SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk + SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[30]/C + +Slack: inf + Source: dip_sw[9] + (input port) + Destination: u_confreg/s_rdata_reg[9]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.697ns (logic 1.718ns (25.648%) route 4.980ns (74.352%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.284ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N7 0.000 0.000 r dip_sw[9] (IN) + net (fo=0) 0.000 0.000 dip_sw[9] + N7 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[9]_inst/O + net (fo=1, routed) 4.246 5.716 u_confreg/dip_sw_IBUF[9] + SLICE_X58Y135 LUT5 (Prop_lut5_I4_O) 0.124 5.840 r u_confreg/s_rdata[9]_i_4/O + net (fo=1, routed) 0.733 6.573 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 + SLICE_X57Y132 LUT6 (Prop_lut6_I4_O) 0.124 6.697 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O + net (fo=1, routed) 0.000 6.697 u_confreg/u_int_ctrl_n_22 + SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.544 -2.284 u_confreg/sys_clk + SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[9]/C Slack: inf Source: UART_TX @@ -38270,10 +37312,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.135ns (logic 1.598ns (26.054%) route 4.537ns (73.946%)) + Data Path Delay: 6.665ns (logic 1.598ns (23.982%) route 5.067ns (76.018%)) Logic Levels: 2 (IBUF=1 LUT5=1) - Clock Path Skew: -1.929ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.929ns + Clock Path Skew: -2.306ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -38282,10 +37324,10 @@ Slack: inf H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 r UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 3.916 5.391 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT5 (Prop_lut5_I0_O) 0.124 5.515 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O - net (fo=1, routed) 0.620 6.135 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D + net (fo=4, routed) 5.067 6.541 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X79Y136 LUT5 (Prop_lut5_I0_O) 0.124 6.665 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O + net (fo=1, routed) 0.000 6.665 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 + SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38297,8 +37339,121 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.899 -1.929 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C + net (fo=9971, routed) 1.522 -2.306 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C + +Slack: inf + Source: dip_sw[28] + (input port) + Destination: u_confreg/s_rdata_reg[28]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.630ns (logic 1.716ns (25.877%) route 4.914ns (74.123%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.277ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R5 0.000 0.000 r dip_sw[28] (IN) + net (fo=0) 0.000 0.000 dip_sw[28] + R5 IBUF (Prop_ibuf_I_O) 1.468 1.468 r dip_sw_IBUF[28]_inst/O + net (fo=1, routed) 3.943 5.410 u_confreg/dip_sw_IBUF[28] + SLICE_X59Y139 LUT5 (Prop_lut5_I4_O) 0.124 5.534 r u_confreg/s_rdata[28]_i_4/O + net (fo=1, routed) 0.971 6.506 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 + SLICE_X52Y139 LUT6 (Prop_lut6_I4_O) 0.124 6.630 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O + net (fo=1, routed) 0.000 6.630 u_confreg/u_int_ctrl_n_3 + SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.551 -2.277 u_confreg/sys_clk + SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[28]/C + +Slack: inf + Source: touch_btn[3] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.594ns (logic 1.513ns (22.943%) route 5.081ns (77.057%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -2.286ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.286ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + U2 0.000 0.000 r touch_btn[3] (IN) + net (fo=0) 0.000 0.000 touch_btn[3] + U2 IBUF (Prop_ibuf_I_O) 1.513 1.513 r touch_btn_IBUF[3]_inst/O + net (fo=1, routed) 5.081 6.594 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] + SLICE_X60Y131 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.542 -2.286 u_confreg/u_int_ctrl/sys_clk + SLICE_X60Y131 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C + +Slack: inf + Source: dip_sw[17] + (input port) + Destination: u_confreg/s_rdata_reg[17]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.534ns (logic 1.752ns (26.817%) route 4.781ns (73.183%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.279ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.279ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K1 0.000 0.000 r dip_sw[17] (IN) + net (fo=0) 0.000 0.000 dip_sw[17] + K1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[17]_inst/O + net (fo=1, routed) 4.040 5.544 u_confreg/dip_sw_IBUF[17] + SLICE_X56Y136 LUT5 (Prop_lut5_I4_O) 0.124 5.668 r u_confreg/s_rdata[17]_i_4/O + net (fo=1, routed) 0.742 6.410 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 + SLICE_X49Y136 LUT6 (Prop_lut6_I4_O) 0.124 6.534 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O + net (fo=1, routed) 0.000 6.534 u_confreg/u_int_ctrl_n_14 + SLICE_X49Y136 FDRE r u_confreg/s_rdata_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk + SLICE_X49Y136 FDRE r u_confreg/s_rdata_reg[17]/C Slack: inf Source: touch_btn[0] @@ -38307,10 +37462,10 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 5.929ns (logic 1.499ns (25.283%) route 4.430ns (74.717%)) + Data Path Delay: 6.451ns (logic 1.499ns (23.235%) route 4.952ns (76.765%)) Logic Levels: 1 (IBUF=1) - Clock Path Skew: -2.009ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns + Clock Path Skew: -2.284ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -38319,8 +37474,8 @@ Slack: inf T2 0.000 0.000 r touch_btn[0] (IN) net (fo=0) 0.000 0.000 touch_btn[0] T2 IBUF (Prop_ibuf_I_O) 1.499 1.499 r touch_btn_IBUF[0]_inst/O - net (fo=1, routed) 4.430 5.929 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D + net (fo=1, routed) 4.952 6.451 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] + SLICE_X60Y132 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38332,8 +37487,47 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.819 -2.009 u_confreg/u_int_ctrl/sys_clk - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C + net (fo=9971, routed) 1.544 -2.284 u_confreg/u_int_ctrl/sys_clk + SLICE_X60Y132 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C + +Slack: inf + Source: dip_sw[11] + (input port) + Destination: u_confreg/s_rdata_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.415ns (logic 1.719ns (26.800%) route 4.696ns (73.200%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.283ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.283ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L7 0.000 0.000 r dip_sw[11] (IN) + net (fo=0) 0.000 0.000 dip_sw[11] + L7 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[11]_inst/O + net (fo=1, routed) 4.076 5.548 u_confreg/dip_sw_IBUF[11] + SLICE_X60Y139 LUT5 (Prop_lut5_I4_O) 0.124 5.672 r u_confreg/s_rdata[11]_i_4/O + net (fo=1, routed) 0.619 6.291 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 + SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.124 6.415 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O + net (fo=1, routed) 0.000 6.415 u_confreg/u_int_ctrl_n_20 + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.545 -2.283 u_confreg/sys_clk + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[11]/C Slack: inf Source: UART_RX @@ -38342,10 +37536,10 @@ Slack: inf (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 5.784ns (logic 1.590ns (27.483%) route 4.194ns (72.517%)) + Data Path Delay: 6.183ns (logic 1.590ns (25.709%) route 4.593ns (74.291%)) Logic Levels: 2 (IBUF=1 LUT4=1) - Clock Path Skew: -1.930ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.930ns + Clock Path Skew: -2.297ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.297ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -38354,10 +37548,10 @@ Slack: inf J20 0.000 0.000 r UART_RX (INOUT) net (fo=1, unset) 0.000 0.000 UART_RX_IOBUF_inst/IO J20 IBUF (Prop_ibuf_I_O) 1.466 1.466 r UART_RX_IOBUF_inst/IBUF/O - net (fo=1, routed) 4.194 5.660 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_RX_IBUF - SLICE_X1Y61 LUT4 (Prop_lut4_I3_O) 0.124 5.784 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O - net (fo=1, routed) 0.000 5.784 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D + net (fo=1, routed) 4.593 6.059 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_RX_IBUF + SLICE_X77Y137 LUT4 (Prop_lut4_I3_O) 0.124 6.183 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O + net (fo=1, routed) 0.000 6.183 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i + SLICE_X77Y137 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38369,8 +37563,121 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.898 -1.930 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C + net (fo=9971, routed) 1.531 -2.297 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk + SLICE_X77Y137 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C + +Slack: inf + Source: dip_sw[31] + (input port) + Destination: u_confreg/s_rdata_reg[31]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.133ns (logic 1.742ns (28.400%) route 4.391ns (71.600%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.280ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.280ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R2 0.000 0.000 r dip_sw[31] (IN) + net (fo=0) 0.000 0.000 dip_sw[31] + R2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[31]_inst/O + net (fo=1, routed) 4.089 5.582 u_confreg/dip_sw_IBUF[31] + SLICE_X59Y137 LUT5 (Prop_lut5_I4_O) 0.124 5.706 r u_confreg/s_rdata[31]_i_6/O + net (fo=1, routed) 0.302 6.009 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 + SLICE_X57Y137 LUT6 (Prop_lut6_I4_O) 0.124 6.133 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O + net (fo=1, routed) 0.000 6.133 u_confreg/u_int_ctrl_n_0 + SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.548 -2.280 u_confreg/sys_clk + SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[31]/C + +Slack: inf + Source: dip_sw[23] + (input port) + Destination: u_confreg/s_rdata_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.019ns (logic 1.766ns (29.348%) route 4.253ns (70.652%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.277ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.277ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N1 0.000 0.000 r dip_sw[23] (IN) + net (fo=0) 0.000 0.000 dip_sw[23] + N1 IBUF (Prop_ibuf_I_O) 1.518 1.518 r dip_sw_IBUF[23]_inst/O + net (fo=1, routed) 3.538 5.057 u_confreg/dip_sw_IBUF[23] + SLICE_X51Y139 LUT5 (Prop_lut5_I4_O) 0.124 5.181 r u_confreg/s_rdata[23]_i_4/O + net (fo=1, routed) 0.714 5.895 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 + SLICE_X50Y139 LUT6 (Prop_lut6_I4_O) 0.124 6.019 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O + net (fo=1, routed) 0.000 6.019 u_confreg/u_int_ctrl_n_8 + SLICE_X50Y139 FDRE r u_confreg/s_rdata_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.551 -2.277 u_confreg/sys_clk + SLICE_X50Y139 FDRE r u_confreg/s_rdata_reg[23]/C + +Slack: inf + Source: touch_btn[2] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.014ns (logic 1.487ns (24.725%) route 4.527ns (75.275%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -2.288ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.288ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P3 0.000 0.000 r touch_btn[2] (IN) + net (fo=0) 0.000 0.000 touch_btn[2] + P3 IBUF (Prop_ibuf_I_O) 1.487 1.487 r touch_btn_IBUF[2]_inst/O + net (fo=1, routed) 4.527 6.014 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] + SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.540 -2.288 u_confreg/u_int_ctrl/sys_clk + SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C Slack: inf Source: UART_TX @@ -38379,10 +37686,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 5.395ns (logic 1.598ns (29.628%) route 3.796ns (70.372%)) + Data Path Delay: 5.898ns (logic 1.598ns (27.102%) route 4.299ns (72.898%)) Logic Levels: 2 (IBUF=1 LUT5=1) - Clock Path Skew: -1.932ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.932ns + Clock Path Skew: -2.297ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.297ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -38391,10 +37698,10 @@ Slack: inf H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 3.796 5.271 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF - SLICE_X4Y61 LUT5 (Prop_lut5_I2_O) 0.124 5.395 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O - net (fo=1, routed) 0.000 5.395 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 - SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D + net (fo=4, routed) 4.299 5.774 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF + SLICE_X77Y137 LUT5 (Prop_lut5_I2_O) 0.124 5.898 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O + net (fo=1, routed) 0.000 5.898 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 + SLICE_X77Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38406,8 +37713,43 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.896 -1.932 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C + net (fo=9971, routed) 1.531 -2.297 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X77Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C + +Slack: inf + Source: touch_btn[1] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.747ns (logic 1.515ns (26.361%) route 4.232ns (73.639%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -2.294ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M1 0.000 0.000 r touch_btn[1] (IN) + net (fo=0) 0.000 0.000 touch_btn[1] + M1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r touch_btn_IBUF[1]_inst/O + net (fo=1, routed) 4.232 5.747 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] + SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.534 -2.294 u_confreg/u_int_ctrl/sys_clk + SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED @@ -38416,20 +37758,20 @@ Slack: inf (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 4.648ns (logic 0.124ns (2.668%) route 4.524ns (97.332%)) + Data Path Delay: 4.333ns (logic 0.124ns (2.862%) route 4.209ns (97.138%)) Logic Levels: 1 (LUT1=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - net (fo=1, routed) 3.378 3.378 pll_clk.u_rst_sys/locked - SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.124 3.502 f pll_clk.u_rst_sys/delay[1]_i_1/O - net (fo=2, routed) 1.146 4.648 pll_clk.u_rst_sys/delay[1]_i_1_n_0 - SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR + net (fo=1, routed) 3.680 3.680 pll_clk.u_rst_sys/locked + SLICE_X22Y139 LUT1 (Prop_lut1_I0_O) 0.124 3.804 f pll_clk.u_rst_sys/delay[1]_i_1/O + net (fo=2, routed) 0.529 4.333 pll_clk.u_rst_sys/delay[1]_i_1_n_0 + SLICE_X22Y139 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38441,8 +37783,8 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.736 -2.092 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C + net (fo=9971, routed) 1.649 -2.179 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED @@ -38451,20 +37793,20 @@ Slack: inf (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 4.648ns (logic 0.124ns (2.668%) route 4.524ns (97.332%)) + Data Path Delay: 4.333ns (logic 0.124ns (2.862%) route 4.209ns (97.138%)) Logic Levels: 1 (LUT1=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - net (fo=1, routed) 3.378 3.378 pll_clk.u_rst_sys/locked - SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.124 3.502 f pll_clk.u_rst_sys/delay[1]_i_1/O - net (fo=2, routed) 1.146 4.648 pll_clk.u_rst_sys/delay[1]_i_1_n_0 - SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR + net (fo=1, routed) 3.680 3.680 pll_clk.u_rst_sys/locked + SLICE_X22Y139 LUT1 (Prop_lut1_I0_O) 0.124 3.804 f pll_clk.u_rst_sys/delay[1]_i_1/O + net (fo=2, routed) 0.529 4.333 pll_clk.u_rst_sys/delay[1]_i_1_n_0 + SLICE_X22Y139 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38476,8 +37818,8 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.736 -2.092 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=9971, routed) 1.649 -2.179 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C diff --git a/fpga/vivado_reports_nodsp/timing_summary_hold_full.rpt b/fpga/vivado_reports_nodsp/timing_summary_hold_full.rpt index 288f9a5..8eff3e5 100644 --- a/fpga/vivado_reports_nodsp/timing_summary_hold_full.rpt +++ b/fpga/vivado_reports_nodsp/timing_summary_hold_full.rpt @@ -1,13 +1,17 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:11 2026 +<<<<<<< Updated upstream +| Date : Fri Jul 10 04:14:53 2026 +======= +| Date : Sat Jul 11 09:20:55 2026 +>>>>>>> Stashed changes | Host : fedora running 64-bit unknown -| Command : report_timing_summary -delay_type min -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/vivado_reports_nodsp/timing_summary_hold_full.rpt +| Command : report_timing_summary -delay_type min -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_summary_hold_full.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report @@ -208,7 +212,11 @@ video_vsync WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 0.032 0.000 0 115177 7.000 0.000 0 42610 +<<<<<<< Updated upstream + 0.040 0.000 0 113333 7.000 0.000 0 42143 +======= + 0.024 0.000 0 88843 5.250 0.000 0 33736 +>>>>>>> Stashed changes All user specified timing constraints are met. @@ -219,13 +227,17 @@ All user specified timing constraints are met. | ------------- ------------------------------------------------------------------------------------------------ -Clock Waveform(ns) Period(ns) Frequency(MHz) ------ ------------ ---------- -------------- -clk {0.000 10.000} 20.000 50.000 - clkfbout_clk_pll {0.000 10.000} 20.000 50.000 - cpu_clk {0.000 15.161} 30.323 32.979 - mlkem_clk_clk_pll {0.000 20.000} 40.000 25.000 - sys_clk {0.000 10.000} 20.000 50.000 +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 10.000} 20.000 50.000 + clkfbout_clk_pll {0.000 10.000} 20.000 50.000 +<<<<<<< Updated upstream + cpu_clk {0.000 15.161} 30.323 32.979 +======= + cpu_clk {0.000 15.000} 30.000 33.333 + mlkem_clk {0.000 6.500} 13.000 76.923 +>>>>>>> Stashed changes + sys_clk {0.000 10.000} 20.000 50.000 ------------------------------------------------------------------------------------------------ @@ -233,13 +245,18 @@ clk {0.000 10.000} 20.000 50.000 | ----------------- ------------------------------------------------------------------------------------------------ -Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------ ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -clk 7.000 0.000 0 1 - clkfbout_clk_pll 17.845 0.000 0 3 - cpu_clk 0.049 0.000 0 17197 13.911 0.000 0 6486 - mlkem_clk_clk_pll 0.058 0.000 0 48474 18.750 0.000 0 26131 - sys_clk 0.079 0.000 0 22818 8.750 0.000 0 9989 +Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 7.000 0.000 0 1 + clkfbout_clk_pll 17.845 0.000 0 3 +<<<<<<< Updated upstream + cpu_clk 0.049 0.000 0 17197 13.911 0.000 0 6486 + sys_clk 0.040 0.000 0 69558 8.750 0.000 0 35653 +======= + cpu_clk 0.040 0.000 0 17197 13.750 0.000 0 6486 + mlkem_clk 0.057 0.000 0 31646 5.250 0.000 0 17274 + sys_clk 0.024 0.000 0 22307 8.750 0.000 0 9972 +>>>>>>> Stashed changes ------------------------------------------------------------------------------------------------ @@ -247,10 +264,8 @@ clk | ----------------- ------------------------------------------------------------------------------------------------ -From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- -------- ------- ------- --------------------- ------------------- -sys_clk mlkem_clk_clk_pll 0.054 0.000 0 108 -mlkem_clk_clk_pll sys_clk 0.032 0.000 0 59 +From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ @@ -260,11 +275,14 @@ mlkem_clk_clk_pll sys_clk 0.032 0.000 Path Group From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- -**async_default** cpu_clk cpu_clk 0.651 0.000 0 67 -**async_default** mlkem_clk_clk_pll mlkem_clk_clk_pll 0.613 0.000 0 25694 -**async_default** sys_clk mlkem_clk_clk_pll 2.861 0.000 0 4 -**async_default** mlkem_clk_clk_pll sys_clk 2.991 0.000 0 2 -**async_default** sys_clk sys_clk 0.479 0.000 0 886 +<<<<<<< Updated upstream +**async_default** cpu_clk cpu_clk 0.727 0.000 0 67 +**async_default** sys_clk sys_clk 0.761 0.000 0 26511 +======= +**async_default** cpu_clk cpu_clk 0.681 0.000 0 67 +**async_default** mlkem_clk mlkem_clk 0.658 0.000 0 16740 +**async_default** sys_clk sys_clk 0.573 0.000 0 886 +>>>>>>> Stashed changes ------------------------------------------------------------------------------------------------ @@ -275,7 +293,9 @@ Path Group From Clock To Clock WHS(ns) THS(ns Path Group From Clock To Clock ---------- ---------- -------- (none) sys_clk cpu_clk +(none) sys_clk mlkem_clk (none) cpu_clk sys_clk +(none) mlkem_clk sys_clk ------------------------------------------------------------------------------------------------ @@ -341,7 +361,7 @@ Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y19 pll_clk.u_clk_pll/inst/clkf_buf/I +Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkf_buf/I Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN @@ -354,26 +374,1936 @@ From Clock: cpu_clk To Clock: cpu_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.049ns, Total Violation 0.000ns -PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.040ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 13.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- +Slack (MET) : 0.040ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_csr/csr_badv_reg[0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): 0.216ns +======= + Data Path Delay: 0.405ns (logic 0.186ns (45.911%) route 0.219ns (54.089%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.274ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk + SLICE_X113Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X113Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/Q + net (fo=3, routed) 0.219 -0.314 u_cpu/wb_stage/ms_to_ws_bus_r_reg_n_0_[0] + SLICE_X107Y149 LUT6 (Prop_lut6_I2_O) 0.045 -0.269 r u_cpu/wb_stage/csr_badv[0]_i_1/O + net (fo=1, routed) 0.000 -0.269 u_cpu/u_csr/csr_badv_reg[31]_4[0] + SLICE_X107Y149 FDRE r u_cpu/u_csr/csr_badv_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.863 -0.445 u_cpu/u_csr/cpu_clk + SLICE_X107Y149 FDRE r u_cpu/u_csr/csr_badv_reg[0]/C + clock pessimism 0.045 -0.400 + SLICE_X107Y149 FDRE (Hold_fdre_C_D) 0.091 -0.309 u_cpu/u_csr/csr_badv_reg[0] + ------------------------------------------------------------------- + required time 0.309 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.040 + Slack (MET) : 0.049ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C + Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.213ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.650 -0.612 u_cpu/u_csr/cpu_clk + SLICE_X97Y50 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.471 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q + net (fo=4, routed) 0.068 -0.403 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 + SLICE_X96Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk + SLICE_X117Y149 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[20]/C + ------------------------------------------------------------------- ------------------- + SLICE_X117Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q + net (fo=4, routed) 0.068 -0.458 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 + SLICE_X116Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.925 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/WCLK + SLICE_X96Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/CLK + clock pessimism -0.216 -0.599 + SLICE_X96Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.452 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA + ------------------------------------------------------------------- + required time 0.452 + arrival time -0.403 + ------------------------------------------------------------------- + slack 0.049 + +Slack (MET) : 0.051ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK + SLICE_X116Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/CLK + clock pessimism -0.213 -0.654 + SLICE_X116Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.458 + ------------------------------------------------------------------- + slack 0.049 + +Slack (MET) : 0.058ns (arrival time - required time) + Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.400ns (logic 0.164ns (40.951%) route 0.236ns (59.049%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.453ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_cpu/mem_stage/cpu_clk + SLICE_X98Y152 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C + ------------------------------------------------------------------- ------------------- + SLICE_X98Y152 FDRE (Prop_fdre_C_Q) 0.164 -0.521 r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/Q + net (fo=2, routed) 0.236 -0.284 u_cpu/wb_stage/ms_to_ws_bus[78] + SLICE_X99Y148 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.855 -0.453 u_cpu/wb_stage/cpu_clk + SLICE_X99Y148 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/C + clock pessimism 0.045 -0.408 + SLICE_X99Y148 FDRE (Hold_fdre_C_D) 0.066 -0.342 u_cpu/wb_stage/ms_to_ws_bus_r_reg[114] + ------------------------------------------------------------------- + required time 0.342 + arrival time -0.284 + ------------------------------------------------------------------- + slack 0.058 + +Slack (MET) : 0.061ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) +>>>>>>> Stashed changes + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.211ns (logic 0.141ns (66.741%) route 0.070ns (33.259%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) +<<<<<<< Updated upstream + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.647 -0.615 u_cpu/u_csr/cpu_clk + SLICE_X67Y50 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[20]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q + net (fo=4, routed) 0.070 -0.404 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 + SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.922 -0.386 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK + SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/CLK + clock pessimism -0.216 -0.602 + SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.455 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA + ------------------------------------------------------------------- + required time 0.455 + arrival time -0.404 + ------------------------------------------------------------------- + slack 0.051 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.349ns (logic 0.164ns (46.999%) route 0.185ns (53.001%)) + Logic Levels: 0 + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.506ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.757 -0.506 u_cpu/u_csr/cpu_clk + SLICE_X40Y49 FDRE r u_cpu/u_csr/csr_tlbidx_reg[26]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q + net (fo=33, routed) 0.185 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] + SLICE_X39Y52 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X39Y52 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/C + clock pessimism 0.037 -0.310 + SLICE_X39Y52 FDRE (Hold_fdre_C_D) 0.070 -0.240 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2] + ------------------------------------------------------------------- + required time 0.240 + arrival time -0.157 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[5]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%)) + Data Path Delay: 0.339ns (logic 0.128ns (37.707%) route 0.211ns (62.293%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.727 -0.536 u_cpu/axi_bridge/cpu_clk + SLICE_X47Y47 FDRE r u_cpu/axi_bridge/araddr_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y47 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[5]/Q + net (fo=1, routed) 0.211 -0.196 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIC1 + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.930 -0.378 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK + clock pessimism 0.037 -0.341 + SLICE_X44Y51 RAMD32 (Hold_ramd32_CLK_I) + 0.061 -0.280 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1 + ------------------------------------------------------------------- + required time 0.280 + arrival time -0.196 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/axi_bridge/wstrb_reg[2]/C + (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.496ns + Clock Pessimism Removal (CPR): 0.221ns +======= + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.683ns + Clock Pessimism Removal (CPR): 0.212ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.767 -0.496 u_cpu/axi_bridge/cpu_clk + SLICE_X15Y41 FDSE r u_cpu/axi_bridge/wstrb_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X15Y41 FDSE (Prop_fdse_C_Q) 0.128 -0.368 r u_cpu/axi_bridge/wstrb_reg[2]/Q + net (fo=1, routed) 0.059 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0 + SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.580 -0.683 u_cpu/wb_stage/cpu_clk + SLICE_X103Y161 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y161 FDRE (Prop_fdre_C_Q) 0.141 -0.542 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/Q + net (fo=6, routed) 0.080 -0.462 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/DIA0 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK + SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK + clock pessimism -0.221 -0.483 + SLICE_X14Y41 RAMD32 (Hold_ramd32_CLK_I) + 0.090 -0.393 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC + ------------------------------------------------------------------- + required time 0.393 + arrival time -0.309 +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/CLK + clock pessimism -0.212 -0.670 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.523 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA + ------------------------------------------------------------------- + required time 0.523 + arrival time -0.462 +>>>>>>> Stashed changes + ------------------------------------------------------------------- + slack 0.084 + +<<<<<<< Updated upstream +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[27]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.347ns (logic 0.141ns (40.688%) route 0.206ns (59.312%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.504ns + Clock Pessimism Removal (CPR): -0.037ns +======= +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.355ns (logic 0.128ns (36.084%) route 0.227ns (63.916%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.586 -0.677 u_cpu/exe_stage/cpu_clk + SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C + ------------------------------------------------------------------- ------------------- + SLICE_X105Y150 FDRE (Prop_fdre_C_Q) 0.128 -0.549 r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/Q + net (fo=1, routed) 0.227 -0.322 u_cpu/mem_stage/D[126] + SLICE_X106Y149 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.863 -0.445 u_cpu/mem_stage/cpu_clk + SLICE_X106Y149 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/C + clock pessimism 0.045 -0.400 + SLICE_X106Y149 FDRE (Hold_fdre_C_D) 0.016 -0.384 u_cpu/mem_stage/es_to_ms_bus_r_reg[126] + ------------------------------------------------------------------- + required time 0.384 + arrival time -0.322 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk + SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q + net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 + SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK + SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/CLK + clock pessimism 0.045 -0.415 + SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) + 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1 + ------------------------------------------------------------------- + required time 0.161 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.062 + +Slack (MET) : 0.063ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.223ns (logic 0.141ns (63.098%) route 0.082ns (36.902%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk + SLICE_X121Y148 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[26]/C + ------------------------------------------------------------------- ------------------- + SLICE_X121Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo0_reg[26]/Q + net (fo=4, routed) 0.082 -0.444 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/DIA0 + SLICE_X120Y148 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/WCLK + SLICE_X120Y148 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/CLK + clock pessimism -0.213 -0.654 + SLICE_X120Y148 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.444 + ------------------------------------------------------------------- + slack 0.063 + +Slack (MET) : 0.064ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.443ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): 0.213ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.759 -0.504 u_cpu/u_csr/cpu_clk + SLICE_X37Y49 FDRE r u_cpu/u_csr/csr_tlbidx_reg[27]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[27]/Q + net (fo=33, routed) 0.206 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[8] + SLICE_X37Y50 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.594 -0.669 u_cpu/u_csr/cpu_clk + SLICE_X109Y149 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 r u_cpu/u_csr/csr_tlbelo0_reg[5]/Q + net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D + SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.962 -0.346 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X37Y50 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/C + clock pessimism 0.037 -0.309 + SLICE_X37Y50 FDRE (Hold_fdre_C_D) 0.066 -0.243 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3] + ------------------------------------------------------------------- + required time 0.243 + arrival time -0.157 +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.865 -0.443 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/WCLK + SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/CLK + clock pessimism -0.213 -0.656 + SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.512 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP + ------------------------------------------------------------------- + required time 0.512 + arrival time -0.448 + ------------------------------------------------------------------- + slack 0.064 + +Slack (MET) : 0.066ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.226ns (logic 0.141ns (62.492%) route 0.085ns (37.508%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk + SLICE_X117Y147 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X117Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[14]/Q + net (fo=4, routed) 0.085 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIA0 + SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/WCLK + SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/CLK + clock pessimism -0.213 -0.654 + SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA + ------------------------------------------------------------------- + required time 0.507 + arrival time -0.441 + ------------------------------------------------------------------- + slack 0.066 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.403ns (logic 0.164ns (40.684%) route 0.239ns (59.316%)) + Logic Levels: 0 + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns + Source Clock Delay (SCD): -0.679ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.584 -0.679 u_cpu/mem_stage/cpu_clk + SLICE_X98Y148 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C + ------------------------------------------------------------------- ------------------- + SLICE_X98Y148 FDRE (Prop_fdre_C_Q) 0.164 -0.515 r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/Q + net (fo=2, routed) 0.239 -0.276 u_cpu/wb_stage/ms_to_ws_bus[69] + SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.851 -0.457 u_cpu/wb_stage/cpu_clk + SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/C + clock pessimism 0.045 -0.412 + SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.052 -0.360 u_cpu/wb_stage/ms_to_ws_bus_r_reg[105] + ------------------------------------------------------------------- + required time 0.360 + arrival time -0.276 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.085ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.479ns (logic 0.141ns (29.406%) route 0.338ns (70.594%)) + Logic Levels: 0 + Clock Path Skew: 0.275ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.444ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/u_csr/cpu_clk + SLICE_X115Y150 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[27]/C + ------------------------------------------------------------------- ------------------- + SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q + net (fo=4, routed) 0.338 -0.194 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 + SLICE_X112Y141 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.864 -0.444 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/WCLK + SLICE_X112Y141 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/CLK + clock pessimism 0.045 -0.399 + SLICE_X112Y141 RAMD32 (Hold_ramd32_CLK_I) + 0.120 -0.279 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 + ------------------------------------------------------------------- + required time 0.279 + arrival time -0.194 +>>>>>>> Stashed changes + ------------------------------------------------------------------- + slack 0.086 + +<<<<<<< Updated upstream +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns +======= +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.415ns (logic 0.141ns (33.953%) route 0.274ns (66.047%)) + Logic Levels: 0 + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns + Source Clock Delay (SCD): -0.679ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.584 -0.679 u_cpu/mem_stage/cpu_clk + SLICE_X97Y148 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.538 r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/Q + net (fo=2, routed) 0.274 -0.264 u_cpu/wb_stage/ms_to_ws_bus[68] + SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.851 -0.457 u_cpu/wb_stage/cpu_clk + SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/C + clock pessimism 0.045 -0.412 + SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.059 -0.353 u_cpu/wb_stage/ms_to_ws_bus_r_reg[104] + ------------------------------------------------------------------- + required time 0.353 + arrival time -0.264 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.091ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.443ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.594 -0.669 u_cpu/u_csr/cpu_clk + SLICE_X109Y149 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 r u_cpu/u_csr/csr_tlbelo0_reg[5]/Q + net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D + SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.865 -0.443 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/WCLK + SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/CLK + clock pessimism -0.213 -0.656 + SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.117 -0.539 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP + ------------------------------------------------------------------- + required time 0.539 + arrival time -0.448 + ------------------------------------------------------------------- + slack 0.091 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_csr/csr_cntc_reg[1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.141ns (31.802%) route 0.302ns (68.198%)) + Logic Levels: 0 + Clock Path Skew: 0.278ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.684ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.579 -0.684 u_cpu/wb_stage/cpu_clk + SLICE_X101Y154 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/C + ------------------------------------------------------------------- ------------------- + SLICE_X101Y154 FDRE (Prop_fdre_C_Q) 0.141 -0.543 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[73]/Q + net (fo=21, routed) 0.302 -0.241 u_cpu/u_csr/wr_csr_data[1] + SLICE_X101Y149 FDRE r u_cpu/u_csr/csr_cntc_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.857 -0.451 u_cpu/u_csr/cpu_clk + SLICE_X101Y149 FDRE r u_cpu/u_csr/csr_cntc_reg[1]/C + clock pessimism 0.045 -0.406 + SLICE_X101Y149 FDRE (Hold_fdre_C_D) 0.070 -0.336 u_cpu/u_csr/csr_cntc_reg[1] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.241 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.281ns (logic 0.141ns (50.221%) route 0.140ns (49.779%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.447ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/u_csr/cpu_clk + SLICE_X115Y150 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[26]/C + ------------------------------------------------------------------- ------------------- + SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q + net (fo=4, routed) 0.140 -0.393 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/DIA0 + SLICE_X116Y151 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.861 -0.447 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/WCLK + SLICE_X116Y151 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/CLK + clock pessimism -0.189 -0.636 + SLICE_X116Y151 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.489 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA + ------------------------------------------------------------------- + required time 0.489 + arrival time -0.393 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.258ns (logic 0.141ns (54.698%) route 0.117ns (45.302%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.671ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.592 -0.671 u_cpu/u_csr/cpu_clk + SLICE_X106Y147 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X106Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.530 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q + net (fo=7, routed) 0.117 -0.413 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/D + SLICE_X104Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/I +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -386,13 +2316,13 @@ Slack (MET) : 0.049ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk - SLICE_X47Y34 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[14]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- - SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q - net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -403,32 +2333,491 @@ Slack (MET) : 0.049ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.998 -0.310 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/WCLK - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/CLK - clock pessimism -0.218 -0.528 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- - required time 0.381 - arrival time -0.332 + required time 0.196 + arrival time -0.109 ------------------------------------------------------------------- - slack 0.049 + slack 0.087 -Slack (MET) : 0.052ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.090ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.252ns (logic 0.141ns (55.979%) route 0.111ns (44.021%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.647 -0.615 u_cpu/u_csr/cpu_clk + SLICE_X69Y50 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[22]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[22]/Q + net (fo=4, routed) 0.111 -0.363 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIB0 + SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.922 -0.386 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK + SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/CLK + clock pessimism -0.213 -0.599 + SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.453 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB + ------------------------------------------------------------------- + required time 0.453 + arrival time -0.363 + ------------------------------------------------------------------- + slack 0.090 + +Slack (MET) : 0.090ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[11]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.128ns (37.132%) route 0.217ns (62.868%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.863 -0.445 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/WCLK + SLICE_X104Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP/CLK + clock pessimism -0.210 -0.655 + SLICE_X104Y147 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.509 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_0_0/SP + ------------------------------------------------------------------- + required time 0.509 + arrival time -0.413 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[18]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.256ns (logic 0.141ns (55.072%) route 0.115ns (44.928%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.441ns + Source Clock Delay (SCD): -0.667ns + Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -441,12 +2830,12 @@ Slack (MET) : 0.052ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X43Y35 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[3]/C + net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk + SLICE_X118Y147 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[18]/C ------------------------------------------------------------------- ------------------- - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I + SLICE_X118Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[18]/Q + net (fo=4, routed) 0.115 -0.411 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIC0 + SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -458,18 +2847,192 @@ Slack (MET) : 0.052ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.000 -0.308 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/WCLK - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/CLK - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP + net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/WCLK + SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC/CLK + clock pessimism -0.210 -0.651 + SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMC ------------------------------------------------------------------- - required time 0.383 - arrival time -0.331 + required time 0.507 + arrival time -0.411 ------------------------------------------------------------------- - slack 0.052 + slack 0.096 -Slack (MET) : 0.057ns (arrival time - required time) +Slack (MET) : 0.098ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[24]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.258ns (logic 0.141ns (54.609%) route 0.117ns (45.391%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.442ns + Source Clock Delay (SCD): -0.668ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.595 -0.668 u_cpu/u_csr/cpu_clk + SLICE_X114Y149 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X114Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.527 r u_cpu/u_csr/csr_tlbelo0_reg[24]/Q + net (fo=4, routed) 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIC0 + SLICE_X112Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.866 -0.442 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/WCLK + SLICE_X112Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC/CLK + clock pessimism -0.210 -0.652 + SLICE_X112Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.508 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMC + ------------------------------------------------------------------- + required time 0.508 + arrival time -0.410 + ------------------------------------------------------------------- + slack 0.098 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.727 -0.536 u_cpu/axi_bridge/cpu_clk + SLICE_X47Y49 FDRE r u_cpu/axi_bridge/araddr_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[11]/Q + net (fo=1, routed) 0.217 -0.191 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC1 + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk + SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMA/WADR0 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.930 -0.378 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.060 -0.281 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1 + ------------------------------------------------------------------- + required time 0.281 + arrival time -0.191 + ------------------------------------------------------------------- + slack 0.090 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.358ns (logic 0.128ns (35.706%) route 0.230ns (64.294%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.727 -0.536 u_cpu/axi_bridge/cpu_clk + SLICE_X47Y49 FDRE r u_cpu/axi_bridge/araddr_reg[9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[9]/Q + net (fo=1, routed) 0.230 -0.177 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIB1 + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.930 -0.378 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.071 -0.270 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.270 + arrival time -0.177 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.094ns (arrival time - required time) Source: u_cpu/axi_bridge/awaddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I @@ -477,12 +3040,12 @@ Slack (MET) : 0.057ns (arrival time - required time) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%)) + Data Path Delay: 0.251ns (logic 0.141ns (56.174%) route 0.110ns (43.826%)) Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.496ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Pessimism Removal (CPR): 0.222ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -494,13 +3057,13 @@ Slack (MET) : 0.057ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_cpu/axi_bridge/cpu_clk SLICE_X17Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q - net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I + net (fo=1, routed) 0.110 -0.245 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 + SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -511,301 +3074,31 @@ Slack (MET) : 0.057ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK - clock pessimism 0.037 -0.301 - SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK + clock pessimism -0.222 -0.483 + SLICE_X16Y49 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- - required time 0.157 - arrival time -0.100 + required time 0.339 + arrival time -0.245 ------------------------------------------------------------------- - slack 0.057 + slack 0.094 -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[0]/C +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.766 -0.497 u_cpu/axi_bridge/cpu_clk - SLICE_X23Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[0]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.155 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.061ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.273ns - Source Clock Delay (SCD): -0.507ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.756 -0.507 u_cpu/u_csr/cpu_clk - SLICE_X37Y38 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[20]/C - ------------------------------------------------------------------- ------------------- - SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q - net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 - SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.035 -0.273 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK - SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/CLK - clock pessimism -0.221 -0.494 - SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.347 - arrival time -0.285 - ------------------------------------------------------------------- - slack 0.061 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X43Y35 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.000 -0.308 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/WCLK - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/CLK - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.410 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.766 -0.497 u_cpu/axi_bridge/cpu_clk - SLICE_X23Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[1]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.182 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.796 -0.467 u_cpu/axi_bridge/cpu_clk - SLICE_X7Y48 FDRE r u_cpu/axi_bridge/wdata_reg[14]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[14]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB - ------------------------------------------------------------------- - required time 0.306 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -818,13 +3111,13 @@ Slack (MET) : 0.099ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk - SLICE_X47Y35 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[26]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q - net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -835,31 +3128,409 @@ Slack (MET) : 0.099ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/WCLK - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/CLK - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- - required time 0.379 - arrival time -0.280 + required time 0.214 + arrival time -0.118 ------------------------------------------------------------------- - slack 0.099 + slack 0.095 -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[3]/C +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%)) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.366ns (logic 0.164ns (44.815%) route 0.202ns (55.185%)) + Logic Levels: 0 + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.506ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -872,13 +3543,13 @@ Slack (MET) : 0.103ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.766 -0.497 u_cpu/axi_bridge/cpu_clk - SLICE_X21Y48 FDRE r u_cpu/axi_bridge/awaddr_reg[3]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.757 -0.506 u_cpu/u_csr/cpu_clk + SLICE_X40Y49 FDRE r u_cpu/u_csr/csr_tlbidx_reg[26]/C ------------------------------------------------------------------- ------------------- - SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[3]/Q - net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I + SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q + net (fo=33, routed) 0.202 -0.140 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] + SLICE_X37Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -889,86 +3560,545 @@ Slack (MET) : 0.103ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1 + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.962 -0.346 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X37Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/C + clock pessimism 0.037 -0.309 + SLICE_X37Y51 FDRE (Hold_fdre_C_D) 0.070 -0.239 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2] ------------------------------------------------------------------- - required time 0.178 - arrival time -0.075 + required time 0.239 + arrival time -0.140 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[4]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.286ns (logic 0.141ns (49.244%) route 0.145ns (50.756%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.537ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.726 -0.537 u_cpu/u_csr/cpu_clk + SLICE_X50Y43 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X50Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_cpu/u_csr/csr_tlbelo0_reg[4]/Q + net (fo=7, routed) 0.145 -0.250 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/D + SLICE_X48Y43 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.004 -0.304 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/WCLK + SLICE_X48Y43 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/CLK + clock pessimism -0.196 -0.500 + SLICE_X48Y43 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.354 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP + ------------------------------------------------------------------- + required time 0.354 + arrival time -0.250 ------------------------------------------------------------------- slack 0.103 -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[1]/C +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%)) + Data Path Delay: 0.442ns (logic 0.141ns (31.876%) route 0.301ns (68.124%)) Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.795 -0.468 u_cpu/axi_bridge/cpu_clk - SLICE_X5Y45 FDRE r u_cpu/axi_bridge/wdata_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[1]/Q - net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns +======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1 + net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMA/CLK + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMA ------------------------------------------------------------------- - required time 0.332 - arrival time -0.226 + required time 0.351 + arrival time -0.248 ------------------------------------------------------------------- - slack 0.106 + slack 0.103 -Slack (MET) : 0.118ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -980,13 +4110,23 @@ Slack (MET) : 0.118ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.796 -0.467 u_cpu/axi_bridge/cpu_clk - SLICE_X7Y48 FDRE r u_cpu/axi_bridge/wdata_reg[15]/C +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.727 -0.536 u_cpu/axi_bridge/cpu_clk + SLICE_X47Y49 FDRE r u_cpu/axi_bridge/araddr_reg[10]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[15]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_cpu/axi_bridge/araddr_reg[10]/Q + net (fo=1, routed) 0.301 -0.093 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC0 + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk + SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/WADR0 +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -997,1207 +4137,962 @@ Slack (MET) : 0.118ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1 +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.930 -0.378 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.197 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- - required time 0.328 - arrival time -0.210 + required time 0.197 + arrival time -0.093 ------------------------------------------------------------------- - slack 0.118 + slack 0.104 -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.376ns (logic 0.141ns (37.453%) route 0.235ns (62.547%)) + Logic Levels: 0 + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.345ns + Source Clock Delay (SCD): -0.504ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.759 -0.504 u_cpu/u_csr/cpu_clk + SLICE_X37Y49 FDRE r u_cpu/u_csr/csr_tlbidx_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[24]/Q + net (fo=33, routed) 0.235 -0.127 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[5] + SLICE_X32Y53 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.963 -0.345 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X32Y53 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/C + clock pessimism 0.037 -0.308 + SLICE_X32Y53 FDRE (Hold_fdre_C_D) 0.070 -0.238 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0] + ------------------------------------------------------------------- + required time 0.238 + arrival time -0.127 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk - SLICE_X39Y39 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/WCLK - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/CLK - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.369 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.499 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.710 -0.552 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.985 -0.323 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.476 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X45Y36 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[10]/C - ------------------------------------------------------------------- ------------------- - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[10]/Q - net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/WCLK - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/CLK - clock pessimism -0.217 -0.526 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.710 -0.552 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.985 -0.323 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.477 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.553ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.709 -0.553 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.984 -0.324 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.229 -0.553 - SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.478 - arrival time -0.356 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.123ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X45Y34 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[12]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/WCLK - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/CLK - clock pessimism -0.218 -0.527 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.123 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk - SLICE_X47Y36 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[16]/C - ------------------------------------------------------------------- ------------------- - SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[16]/Q - net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.998 -0.310 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/WCLK - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/CLK - clock pessimism -0.217 -0.527 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[22]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%)) - Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.796 -0.467 u_cpu/axi_bridge/cpu_clk - SLICE_X5Y47 FDRE r u_cpu/axi_bridge/wdata_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[22]/Q - net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0 - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK - clock pessimism -0.196 -0.425 - SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC - ------------------------------------------------------------------- - required time 0.281 - arrival time -0.157 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk - SLICE_X39Y39 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/WCLK - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/CLK - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.504 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.710 -0.552 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.985 -0.323 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.481 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.394 - arrival time -0.266 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%)) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.510ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.753 -0.510 u_cpu/u_csr/cpu_clk - SLICE_X41Y37 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[15]/C - ------------------------------------------------------------------- ------------------- - SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[15]/Q - net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1 - SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/WCLK - SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/CLK - clock pessimism -0.218 -0.493 - SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1 - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk - SLICE_X47Y35 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[27]/C - ------------------------------------------------------------------- ------------------- - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q - net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/WCLK - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/CLK - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 + net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1/CLK + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMA_D1 ------------------------------------------------------------------- - required time 0.406 - arrival time -0.278 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0 - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.230 -0.575 - SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.369 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.390 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.542ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.721 -0.542 u_cpu/u_csr/cpu_clk - SLICE_X43Y32 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[20]/C - ------------------------------------------------------------------- ------------------- - SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 r u_cpu/u_csr/csr_tlbelo0_reg[20]/Q - net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0 - SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.998 -0.310 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/WCLK - SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/CLK - clock pessimism -0.217 -0.527 - SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.380 + required time 0.351 arrival time -0.248 ------------------------------------------------------------------- - slack 0.132 + slack 0.103 -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[0]/C +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk + SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMB/WADR0 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.003 -0.305 u_cpu/btb/ras_reg_0_7_6_11/WCLK + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA/CLK + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%)) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.003 -0.305 u_cpu/btb/ras_reg_0_7_6_11/WCLK + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/CLK + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1 + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMB/CLK + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMB + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk + SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1/CLK + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMB_D1 + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk + SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMC/CLK + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMC + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk + SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK + SLICE_X132Y164 RAMD32 r u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1/CLK + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMC_D1 + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk + SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMS32 r u_cpu/btb/ras_reg_0_7_12_17/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK + SLICE_X132Y164 RAMS32 r u_cpu/btb/ras_reg_0_7_12_17/RAMD/CLK + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMD + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.962%) route 0.287ns (67.038%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk + SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.287 -0.248 u_cpu/btb/ras_reg_0_7_12_17/ADDRD0 + SLICE_X132Y164 RAMS32 r u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.856 -0.451 u_cpu/btb/ras_reg_0_7_12_17/WCLK + SLICE_X132Y164 RAMS32 r u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1/CLK + clock pessimism -0.210 -0.661 + SLICE_X132Y164 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.351 u_cpu/btb/ras_reg_0_7_12_17/RAMD_D1 + ------------------------------------------------------------------- + required time 0.351 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.103 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk + SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/CLK + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk + SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1/CLK + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk + SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB/CLK + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk + SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1/CLK + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMB_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk + SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC/CLK + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk + SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK + SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1/CLK + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMC_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk + SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMS32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK + SLICE_X102Y161 RAMS32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD/CLK + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.564ns (logic 0.141ns (24.981%) route 0.423ns (75.019%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk + SLICE_X103Y147 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.423 -0.110 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/ADDRD4 + SLICE_X102Y161 RAMS32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK + SLICE_X102Y161 RAMS32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1/CLK + clock pessimism 0.045 -0.413 + SLICE_X102Y161 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.213 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMD_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.110 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.107ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[22]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.269ns (logic 0.141ns (52.500%) route 0.128ns (47.500%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns + Destination Clock Delay (DCD): -0.442ns + Source Clock Delay (SCD): -0.668ns + Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2210,12 +5105,12 @@ Slack (MET) : 0.133ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.795 -0.468 u_cpu/axi_bridge/cpu_clk - SLICE_X5Y45 FDRE r u_cpu/axi_bridge/wdata_reg[0]/C + net (fo=6484, routed) 0.595 -0.668 u_cpu/u_csr/cpu_clk + SLICE_X115Y149 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[22]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[0]/Q - net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I + SLICE_X115Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.527 r u_cpu/u_csr/csr_tlbelo0_reg[22]/Q + net (fo=4, routed) 0.128 -0.399 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIB0 + SLICE_X112Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -2227,31 +5122,31 @@ Slack (MET) : 0.133ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA + net (fo=6484, routed) 0.866 -0.442 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/WCLK + SLICE_X112Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB/CLK + clock pessimism -0.210 -0.652 + SLICE_X112Y149 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.506 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMB ------------------------------------------------------------------- - required time 0.305 - arrival time -0.172 + required time 0.506 + arrival time -0.399 ------------------------------------------------------------------- - slack 0.133 + slack 0.107 -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/u_csr/timer_64_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns + Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2264,12 +5159,14 @@ Slack (MET) : 0.134ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk - SLICE_X39Y39 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[2]/C + net (fo=6484, routed) 0.586 -0.677 u_cpu/u_csr/cpu_clk + SLICE_X106Y151 FDRE r u_cpu/u_csr/timer_64_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q - net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I + SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q + net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] + SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O + net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/A1 + SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -2281,31 +5178,31 @@ Slack (MET) : 0.134ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/WCLK - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/CLK - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP + net (fo=6484, routed) 0.862 -0.446 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/WCLK + SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP/CLK + clock pessimism 0.045 -0.401 + SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/DP ------------------------------------------------------------------- - required time 0.379 - arrival time -0.245 + required time 0.092 + arrival time 0.016 ------------------------------------------------------------------- - slack 0.134 + slack 0.108 -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/u_csr/timer_64_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2318,12 +5215,14 @@ Slack (MET) : 0.135ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.763 -0.500 u_cpu/axi_bridge/cpu_clk - SLICE_X28Y48 FDRE r u_cpu/axi_bridge/araddr_reg[2]/C + net (fo=6484, routed) 0.586 -0.677 u_cpu/u_csr/cpu_clk + SLICE_X106Y151 FDRE r u_cpu/u_csr/timer_64_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[2]/Q - net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I + SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q + net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] + SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O + net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/A1 + SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -2335,31 +5234,31 @@ Slack (MET) : 0.135ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB + net (fo=6484, routed) 0.862 -0.446 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/WCLK + SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP/CLK + clock pessimism 0.045 -0.401 + SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r2_0_31_0_0/SP ------------------------------------------------------------------- - required time 0.165 - arrival time -0.031 + required time 0.092 + arrival time 0.016 ------------------------------------------------------------------- - slack 0.135 + slack 0.108 -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/u_csr/timer_64_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns + Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2372,12 +5271,14 @@ Slack (MET) : 0.135ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.795 -0.468 u_cpu/axi_bridge/cpu_clk - SLICE_X5Y45 FDRE r u_cpu/axi_bridge/wdata_reg[12]/C + net (fo=6484, routed) 0.586 -0.677 u_cpu/u_csr/cpu_clk + SLICE_X106Y151 FDRE r u_cpu/u_csr/timer_64_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[12]/Q - net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I + SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q + net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] + SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O + net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/A1 + SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -2389,460 +5290,258 @@ Slack (MET) : 0.135ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA + net (fo=6484, routed) 0.862 -0.446 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/WCLK + SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP/CLK + clock pessimism 0.045 -0.401 + SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/DP ------------------------------------------------------------------- - required time 0.305 - arrival time -0.170 + required time 0.092 + arrival time 0.016 ------------------------------------------------------------------- - slack 0.135 + slack 0.108 -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/u_csr/timer_64_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%)) + Data Path Delay: 0.693ns (logic 0.186ns (26.853%) route 0.507ns (73.147%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.677ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.586 -0.677 u_cpu/u_csr/cpu_clk + SLICE_X106Y151 FDRE r u_cpu/u_csr/timer_64_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X106Y151 FDRE (Prop_fdre_C_Q) 0.141 -0.536 r u_cpu/u_csr/timer_64_reg[1]/Q + net (fo=4, routed) 0.227 -0.309 u_cpu/wb_stage/rand_index[1] + SLICE_X106Y146 LUT6 (Prop_lut6_I0_O) 0.045 -0.264 r u_cpu/wb_stage/tlb_ppn0_reg_r1_0_31_0_5_i_10/O + net (fo=358, routed) 0.280 0.016 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/A1 + SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.862 -0.446 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/WCLK + SLICE_X104Y145 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP/CLK + clock pessimism 0.045 -0.401 + SLICE_X104Y145 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.092 u_cpu/addr_trans/tlb_entry/tlb_d0_reg_r3_0_31_0_0/SP + ------------------------------------------------------------------- + required time 0.092 + arrival time 0.016 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk + SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 + SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR0 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.003 -0.305 u_cpu/btb/ras_reg_0_7_6_11/WCLK + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB/CLK + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.720 -0.543 u_cpu/u_csr/cpu_clk - SLICE_X48Y32 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[12]/Q - net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.996 -0.312 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/WCLK - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/CLK - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC + net (fo=6484, routed) 0.855 -0.452 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/CLK + clock pessimism -0.210 -0.662 + SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- - required time 0.385 - arrival time -0.249 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.763 -0.500 u_cpu/axi_bridge/cpu_clk - SLICE_X29Y48 FDRE r u_cpu/axi_bridge/araddr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[0]/Q - net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.164 - arrival time -0.028 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.720 -0.543 u_cpu/u_csr/cpu_clk - SLICE_X48Y32 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[11]/Q - net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.996 -0.312 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/WCLK - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/CLK - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.405 - arrival time -0.268 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[28]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_cpu/axi_bridge/cpu_clk - SLICE_X3Y48 FDRE r u_cpu/axi_bridge/wdata_reg[28]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 r u_cpu/axi_bridge/wdata_reg[28]/Q - net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK - clock pessimism -0.220 -0.449 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I) - 0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC - ------------------------------------------------------------------- - required time 0.359 - arrival time -0.221 - ------------------------------------------------------------------- - slack 0.138 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.795 -0.468 u_cpu/icache/lfsr/cpu_clk - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/icache/lfsr/r_lfsr_reg[6]/Q - net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0] - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_cpu/icache/lfsr/cpu_clk - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/C - clock pessimism -0.236 -0.468 - SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7] - ------------------------------------------------------------------- - required time 0.397 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X45Y36 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[11]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1 - SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/WCLK - SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/CLK - clock pessimism -0.217 -0.524 - SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.400 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.268ns - Source Clock Delay (SCD): -0.502ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.761 -0.502 u_cpu/wb_stage/cpu_clk - SLICE_X31Y41 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - ------------------------------------------------------------------- ------------------- - SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q - net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16] - SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.040 -0.268 u_cpu/u_csr/cpu_clk - SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/C - clock pessimism -0.221 -0.489 - SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16] - ------------------------------------------------------------------- - required time 0.442 - arrival time -0.301 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%)) - Logic Levels: 0 - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.269ns - Source Clock Delay (SCD): -0.504ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.759 -0.504 u_cpu/wb_stage/cpu_clk - SLICE_X32Y40 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q - net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9] - SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.039 -0.269 u_cpu/u_csr/cpu_clk - SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/C - clock pessimism -0.196 -0.465 - SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9] - ------------------------------------------------------------------- - required time 0.387 + required time 0.352 arrival time -0.244 ------------------------------------------------------------------- - slack 0.143 + slack 0.108 -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%)) + Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 - Clock Path Skew: 0.035ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.282ns - Source Clock Delay (SCD): -0.513ns - Clock Pessimism Removal (CPR): 0.196ns + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk + SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 + SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR0 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.003 -0.305 u_cpu/btb/ras_reg_0_7_6_11/WCLK + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/CLK + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.855 -0.452 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/CLK + clock pessimism -0.210 -0.662 + SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 + ------------------------------------------------------------------- + required time 0.352 + arrival time -0.244 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2855,12 +5554,12 @@ Slack (MET) : 0.148ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.750 -0.513 u_cpu/mem_stage/cpu_clk - SLICE_X27Y26 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C + net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk + SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q - net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46] - SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 + SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -2872,30 +5571,31 @@ Slack (MET) : 0.148ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.026 -0.282 u_cpu/wb_stage/cpu_clk - SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/C - clock pessimism -0.196 -0.478 - SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82] + net (fo=6484, routed) 0.855 -0.452 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/CLK + clock pessimism -0.210 -0.662 + SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMB ------------------------------------------------------------------- - required time 0.407 - arrival time -0.259 + required time 0.352 + arrival time -0.244 ------------------------------------------------------------------- - slack 0.148 + slack 0.108 -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) + Data Path Delay: 0.432ns (logic 0.141ns (32.643%) route 0.291ns (67.357%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): -0.676ns + Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2908,12 +5608,12 @@ Slack (MET) : 0.148ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C + net (fo=6484, routed) 0.587 -0.676 u_cpu/btb/cpu_clk + SLICE_X133Y163 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 + SLICE_X133Y163 FDRE (Prop_fdre_C_Q) 0.141 -0.535 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.291 -0.244 u_cpu/btb/ras_reg_0_7_18_23/ADDRD0 + SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -2925,124 +5625,17 @@ Slack (MET) : 0.148ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA + net (fo=6484, routed) 0.855 -0.452 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X132Y165 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/CLK + clock pessimism -0.210 -0.662 + SLICE_X132Y165 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.352 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 + required time 0.352 + arrival time -0.244 ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1 - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 + slack 0.108 +>>>>>>> Stashed changes @@ -3051,426 +5644,348 @@ Slack (MET) : 0.148ns (arrival time - required time) Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: cpu_clk -Waveform(ns): { 0.000 15.161 } -Period(ns): 30.323 +Waveform(ns): { 0.000 15.000 } +Period(ns): 30.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +<<<<<<< Updated upstream +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y4 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y4 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y6 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y6 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y7 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y7 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y5 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y5 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y8 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y8 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y20 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y20 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y18 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y18 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X3Y20 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X3Y20 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X3Y21 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X3Y21 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.323 29.074 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 -Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[1]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y5 u_cpu/btb/btb_untaken_entry_r_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y6 u_cpu/btb/btb_untaken_entry_r_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y8 u_cpu/btb/btb_untaken_entry_r_reg[11]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y4 u_cpu/btb/btb_untaken_entry_r_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X50Y5 u_cpu/btb/btb_untaken_entry_r_reg[13]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X49Y9 u_cpu/btb/btb_untaken_entry_r_reg[14]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y1 u_cpu/btb/btb_add_entry_index_r_reg[0]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X41Y3 u_cpu/btb/btb_add_entry_index_r_reg[1]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X47Y0 u_cpu/btb/btb_add_entry_index_r_reg[2]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y6 u_cpu/btb/btb_add_entry_index_r_reg[3]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y6 u_cpu/btb/btb_add_entry_index_r_reg[4]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X41Y6 u_cpu/btb/btb_add_entry_r_reg/C +Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X5Y45 pll_clk.u_rst_cpu/delay_reg[0]/C +Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X5Y45 pll_clk.u_rst_cpu/delay_reg[1]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y57 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y57 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y8 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y8 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK +======= +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y47 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y47 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y46 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y46 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y48 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y48 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y49 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y49 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y50 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y50 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y51 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y51 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y48 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y48 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y49 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y49 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y52 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y52 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y51 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y51 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y52 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y52 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y51 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y51 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y53 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X7Y50 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X7Y50 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X7Y51 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X7Y51 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X6Y48 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X6Y48 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.000 27.424 RAMB18_X6Y49 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.000 27.424 RAMB18_X6Y49 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a BUFG/I n/a 2.155 30.000 27.845 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I +Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.000 28.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X140Y147 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[10][9]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X143Y140 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][0]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X143Y140 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][10]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X142Y141 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][11]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X142Y141 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][12]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X145Y142 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][13]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X143Y143 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][14]/C +Min Period n/a FDRE/C n/a 1.000 30.000 29.000 SLICE_X142Y141 u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[11][15]/C +Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.000 130.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X72Y104 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y99 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X88Y130 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X124Y169 u_cpu/btb/btb_target_reg_0_31_22_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X124Y169 u_cpu/btb/btb_target_reg_0_31_22_23/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y109 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- -From Clock: mlkem_clk_clk_pll - To Clock: mlkem_clk_clk_pll +From Clock: mlkem_clk + To Clock: mlkem_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.058ns, Total Violation 0.000ns -PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.057ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 5.250ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.057ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.695ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.568 -0.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y144 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q - net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0 - SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O - net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0 - SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.833 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/C - clock pessimism 0.045 -0.430 - SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6] - ------------------------------------------------------------------- - required time 0.309 - arrival time -0.251 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.077ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.277ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X86Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q - net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] - SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O - net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0 - SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.839 -0.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/C - clock pessimism 0.045 -0.424 - SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.255 - ------------------------------------------------------------------- - slack 0.077 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.591 -0.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X138Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - ------------------------------------------------------------------- ------------------- - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.869 -0.439 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/C - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X85Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.095ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.276ns (logic 0.141ns (51.000%) route 0.135ns (49.000%)) Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.464ns - Source Clock Delay (SCD): -0.683ns - Clock Pessimism Removal (CPR): -0.045ns + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -3480,15 +5995,15 @@ Slack (MET) : 0.095ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.580 -0.683 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X73Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C + net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X135Y114 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q - net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16] - SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D + SLICE_X135Y114 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/Q + net (fo=7, routed) 0.135 -0.394 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[6] + SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -3498,34 +6013,35 @@ Slack (MET) : 0.095ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.844 -0.464 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/C - clock pessimism 0.045 -0.419 - SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16] + net (fo=17272, routed) 0.863 -0.445 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK + clock pessimism -0.189 -0.634 + SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) + 0.183 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- - required time 0.362 - arrival time -0.267 + required time 0.451 + arrival time -0.394 ------------------------------------------------------------------- - slack 0.095 + slack 0.057 -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.062ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.455ns (logic 0.164ns (36.015%) route 0.291ns (63.985%)) + Logic Levels: 0 + Clock Path Skew: 0.334ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.375ns + Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -3535,20 +6051,15 @@ Slack (MET) : 0.099ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X85Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C + net (fo=17272, routed) 0.594 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X108Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C ------------------------------------------------------------------- ------------------- - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D + SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/Q + net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[16] + SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -3558,34 +6069,34 @@ Slack (MET) : 0.099ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/C - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] + net (fo=17272, routed) 0.933 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/C + clock pessimism 0.040 -0.335 + SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.059 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16] ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 + required time 0.276 + arrival time -0.214 ------------------------------------------------------------------- - slack 0.099 + slack 0.062 -Slack (MET) : 0.105ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.069ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.455ns (logic 0.164ns (36.017%) route 0.291ns (63.983%)) + Logic Levels: 0 + Clock Path Skew: 0.334ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.375ns + Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -3595,17 +6106,15 @@ Slack (MET) : 0.105ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C + net (fo=17272, routed) 0.594 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X108Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C ------------------------------------------------------------------- ------------------- - SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q - net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5] - SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0 - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D + SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/Q + net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[17] + SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -3615,34 +6124,90 @@ Slack (MET) : 0.105ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/C - clock pessimism 0.040 -0.436 - SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5] + net (fo=17272, routed) 0.933 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/C + clock pessimism 0.040 -0.335 + SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.052 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17] ------------------------------------------------------------------- - required time 0.305 - arrival time -0.200 + required time 0.283 + arrival time -0.214 ------------------------------------------------------------------- - slack 0.105 + slack 0.069 -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.085ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.281ns (logic 0.141ns (50.089%) route 0.140ns (49.911%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.211ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X133Y115 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/Q + net (fo=6, routed) 0.140 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[7] + SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.862 -0.446 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK + clock pessimism -0.211 -0.657 + SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) + 0.183 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 + ------------------------------------------------------------------- + required time 0.474 + arrival time -0.388 + ------------------------------------------------------------------- + slack 0.085 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -3652,20 +6217,15 @@ Slack (MET) : 0.107ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C ------------------------------------------------------------------- ------------------- - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q + net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[5] + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -3675,34 +6235,35 @@ Slack (MET) : 0.107ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mlkem_clk + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK + clock pessimism 0.040 -0.333 + RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 + required time 0.150 + arrival time -0.061 ------------------------------------------------------------------- - slack 0.107 + slack 0.089 -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -3712,20 +6273,15 @@ Slack (MET) : 0.107ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C ------------------------------------------------------------------- ------------------- - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q + net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[5] + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -3735,34 +6291,35 @@ Slack (MET) : 0.107ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mlkem_clk + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK + clock pessimism 0.040 -0.333 + RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 + required time 0.150 + arrival time -0.061 ------------------------------------------------------------------- - slack 0.107 + slack 0.089 -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.233ns (logic 0.141ns (60.420%) route 0.092ns (39.580%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.446ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.211ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -3772,20 +6329,15 @@ Slack (MET) : 0.107ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C + net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X133Y115 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D + SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/Q + net (fo=7, routed) 0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[2] + SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -3795,451 +6347,35 @@ Slack (MET) : 0.107ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] + net (fo=17272, routed) 0.862 -0.446 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK + clock pessimism -0.211 -0.657 + SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) + 0.117 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 + required time 0.540 + arrival time -0.437 ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.280ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.458ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.570 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X89Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - ------------------------------------------------------------------- ------------------- - SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q - net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] - SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O - net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0 - SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/C - clock pessimism 0.045 -0.413 - SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8] - ------------------------------------------------------------------- - required time 0.292 - arrival time -0.185 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.829 -0.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/C - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 + slack 0.103 Slack (MET) : 0.111ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.510ns (logic 0.256ns (50.190%) route 0.254ns (49.810%)) - Logic Levels: 2 (CARRY4=1 LUT4=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.702ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4249,20 +6385,15 @@ Slack (MET) : 0.111ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X82Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/Q - net (fo=7, routed) 0.254 -0.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[10] - SLICE_X84Y157 LUT4 (Prop_lut4_I3_O) 0.045 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]_i_9/O - net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave_n_123 - SLICE_X84Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.192 r u_bf/u_barrett/qprod_s4_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[4] - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/D + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[7] + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4272,34 +6403,35 @@ Slack (MET) : 0.111ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - clock pessimism 0.040 -0.437 - SLICE_X84Y157 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12] + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mlkem_clk + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK + clock pessimism 0.040 -0.333 + RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- - required time 0.303 - arrival time -0.192 + required time 0.150 + arrival time -0.040 ------------------------------------------------------------------- slack 0.111 -Slack (MET) : 0.114ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[445]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.557ns (logic 0.234ns (42.015%) route 0.323ns (57.985%)) - Logic Levels: 2 (LUT3=1 LUT6=1) - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.398ns - Source Clock Delay (SCD): -0.694ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4309,19 +6441,15 @@ Slack (MET) : 0.114ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.569 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X79Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[445]/C + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X79Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[445]/Q - net (fo=2, routed) 0.169 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/data18[13] - SLICE_X81Y99 LUT6 (Prop_lut6_I0_O) 0.045 -0.339 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[445]_i_2/O - net (fo=1, routed) 0.154 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[185] - SLICE_X81Y99 LUT3 (Prop_lut3_I1_O) 0.048 -0.137 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[445]_i_1/O - net (fo=1, routed) 0.000 -0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[445] - SLICE_X81Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]/D + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[7] + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4331,34 +6459,35 @@ Slack (MET) : 0.114ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.910 -0.398 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X81Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]/C - clock pessimism 0.040 -0.358 - SLICE_X81Y99 FDCE (Hold_fdce_C_D) 0.107 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445] + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mlkem_clk + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK + clock pessimism 0.040 -0.333 + RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- - required time 0.251 - arrival time -0.137 + required time 0.150 + arrival time -0.040 ------------------------------------------------------------------- - slack 0.114 + slack 0.111 -Slack (MET) : 0.115ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.518ns (logic 0.186ns (35.884%) route 0.332ns (64.116%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.282ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.456ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) + Logic Levels: 0 + Clock Path Skew: 0.058ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.303ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4368,17 +6497,15 @@ Slack (MET) : 0.115ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.570 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X89Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[4]/C + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X89Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[4]/Q - net (fo=234, routed) 0.332 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] - SLICE_X92Y145 LUT6 (Prop_lut6_I3_O) 0.045 -0.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][4]_i_1/O - net (fo=1, routed) 0.000 -0.175 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][4]_i_1_n_0 - SLICE_X92Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]/D + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/Q[6] + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4388,34 +6515,35 @@ Slack (MET) : 0.115ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.852 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X92Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]/C - clock pessimism 0.045 -0.411 - SLICE_X92Y145 FDCE (Hold_fdce_C_D) 0.121 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4] + net (fo=17272, routed) 1.005 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mlkem_clk + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKARDCLK + clock pessimism -0.214 -0.517 + RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg ------------------------------------------------------------------- - required time 0.290 - arrival time -0.175 + required time 0.334 + arrival time -0.223 ------------------------------------------------------------------- - slack 0.115 + slack 0.111 -Slack (MET) : 0.116ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg[6]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.474ns (logic 0.226ns (47.682%) route 0.248ns (52.318%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.704ns - Clock Pessimism Removal (CPR): -0.040ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) + Logic Levels: 0 + Clock Path Skew: 0.058ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.303ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4425,17 +6553,15 @@ Slack (MET) : 0.116ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.559 -0.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X81Y162 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg[6]/C + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X81Y162 FDCE (Prop_fdce_C_Q) 0.128 -0.576 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg[6]/Q - net (fo=4, routed) 0.248 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg_n_0_[6] - SLICE_X87Y160 LUT3 (Prop_lut3_I0_O) 0.098 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r[6]_i_1__0/O - net (fo=1, routed) 0.000 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r[6]_i_1__0_n_0 - SLICE_X87Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]/D + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q + net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/Q[6] + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4445,34 +6571,90 @@ Slack (MET) : 0.116ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X87Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]/C - clock pessimism 0.040 -0.438 - SLICE_X87Y160 FDCE (Hold_fdce_C_D) 0.092 -0.346 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6] + net (fo=17272, routed) 1.005 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mlkem_clk + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKARDCLK + clock pessimism -0.214 -0.517 + RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) + 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg ------------------------------------------------------------------- - required time 0.346 - arrival time -0.230 + required time 0.334 + arrival time -0.223 ------------------------------------------------------------------- - slack 0.116 + slack 0.111 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[19] + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.935 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/C + clock pessimism -0.229 -0.602 + SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.078 -0.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19] + ------------------------------------------------------------------- + required time 0.524 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.119 Slack (MET) : 0.120ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.519ns (logic 0.252ns (48.552%) route 0.267ns (51.448%)) - Logic Levels: 2 (CARRY4=1 LUT5=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.301ns (logic 0.141ns (46.859%) route 0.160ns (53.141%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4482,20 +6664,15 @@ Slack (MET) : 0.120ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C + net (fo=17272, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X57Y91 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X82Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/Q - net (fo=7, routed) 0.267 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[10] - SLICE_X84Y157 LUT5 (Prop_lut5_I0_O) 0.045 -0.249 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]_i_8/O - net (fo=1, routed) 0.000 -0.249 u_fft_mlkem_axi_slave_n_122 - SLICE_X84Y157 CARRY4 (Prop_carry4_S[1]_O[1]) - 0.066 -0.183 r u_bf/u_barrett/qprod_s4_reg[15]_i_1/O[1] - net (fo=1, routed) 0.000 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[5] - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]/D + SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/Q + net (fo=1, routed) 0.160 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIC0 + SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4505,34 +6682,204 @@ Slack (MET) : 0.120ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]/C - clock pessimism 0.040 -0.437 - SLICE_X84Y157 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13] + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK + SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK + clock pessimism -0.192 -0.573 + SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.429 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC ------------------------------------------------------------------- - required time 0.303 - arrival time -0.183 + required time 0.429 + arrival time -0.309 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.410ns (logic 0.186ns (45.405%) route 0.224ns (54.595%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.198ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.442ns + Source Clock Delay (SCD): -0.600ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.662 -0.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X118Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X118Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.459 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/Q + net (fo=29, routed) 0.224 -0.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0[0] + SLICE_X114Y100 LUT6 (Prop_lut6_I1_O) 0.045 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/O + net (fo=1, routed) 0.000 -0.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_next0[5] + SLICE_X114Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.866 -0.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X114Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/C + clock pessimism 0.040 -0.402 + SLICE_X114Y100 FDCE (Hold_fdce_C_D) 0.091 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5] + ------------------------------------------------------------------- + required time 0.311 + arrival time -0.191 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.598 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X138Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q + net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[4] + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.004 -0.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mlkem_clk + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKBWRCLK + clock pessimism 0.040 -0.263 + RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.040 + ------------------------------------------------------------------- + slack 0.120 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.598 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X138Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q + net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[4] + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.004 -0.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mlkem_clk + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKBWRCLK + clock pessimism 0.040 -0.263 + RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.040 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.228ns + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4542,15 +6889,15 @@ Slack (MET) : 0.121ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + net (fo=17272, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C ------------------------------------------------------------------- ------------------- - SLICE_X27Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D + SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[18] + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4560,34 +6907,34 @@ Slack (MET) : 0.121ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.581 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.076 -0.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] + net (fo=17272, routed) 0.935 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/C + clock pessimism -0.229 -0.602 + SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.076 -0.526 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18] ------------------------------------------------------------------- - required time 0.505 - arrival time -0.384 + required time 0.526 + arrival time -0.405 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.227ns + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4597,15 +6944,15 @@ Slack (MET) : 0.121ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X27Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q + net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[1] + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4615,34 +6962,91 @@ Slack (MET) : 0.121ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.227 -0.582 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2] + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mlkem_clk + RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK + clock pessimism 0.040 -0.333 + RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 + required time 0.150 + arrival time -0.029 + ------------------------------------------------------------------- + slack 0.121 + +Slack (MET) : 0.121ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) + Logic Levels: 0 + Clock Path Skew: 0.242ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.575ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q + net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[1] + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mlkem_clk + RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK + clock pessimism 0.040 -0.333 + RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) + 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.029 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.228ns + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4652,15 +7056,15 @@ Slack (MET) : 0.122ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X27Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4670,34 +7074,35 @@ Slack (MET) : 0.122ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.228 -0.581 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.075 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA ------------------------------------------------------------------- - required time 0.506 - arrival time -0.384 + required time 0.268 + arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.228ns + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4707,15 +7112,15 @@ Slack (MET) : 0.122ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C + net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0 - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4725,34 +7130,371 @@ Slack (MET) : 0.122ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.228 -0.581 - SLICE_X25Y79 FDCE (Hold_fdce_C_D) 0.075 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1 ------------------------------------------------------------------- - required time 0.506 - arrival time -0.384 + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1 + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC/CLK + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1/CLK + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMC_D1 + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD/CLK + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 + ------------------------------------------------------------------- + slack 0.122 + +Slack (MET) : 0.122ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) + Logic Levels: 0 + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.618ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X64Y90 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1/CLK + clock pessimism -0.192 -0.578 + SLICE_X64Y90 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMD_D1 + ------------------------------------------------------------------- + required time 0.268 + arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.227ns + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4762,15 +7504,15 @@ Slack (MET) : 0.122ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + net (fo=17272, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X27Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D + SLICE_X59Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q + net (fo=1, routed) 0.056 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0] + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4780,34 +7522,34 @@ Slack (MET) : 0.122ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.227 -0.582 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0] + net (fo=17272, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.229 -0.612 + SLICE_X59Y91 FDCE (Hold_fdce_C_D) 0.075 -0.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 + required time 0.537 + arrival time -0.415 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): 0.226ns + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4817,15 +7559,15 @@ Slack (MET) : 0.122ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X115Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D + SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q + net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[1] + SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4835,34 +7577,34 @@ Slack (MET) : 0.122ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.226 -0.615 - SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.075 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] + net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.229 -0.616 + SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.075 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- - required time 0.540 - arrival time -0.418 + required time 0.541 + arrival time -0.419 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.614ns - Clock Pessimism Removal (CPR): 0.226ns + Source Clock Delay (SCD): -0.617ns + Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4872,15 +7614,15 @@ Slack (MET) : 0.122ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X117Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D + SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q + net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[2] + SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4890,34 +7632,34 @@ Slack (MET) : 0.122ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.226 -0.614 - SLICE_X117Y75 FDCE (Hold_fdce_C_D) 0.075 -0.539 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.229 -0.617 + SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- - required time 0.539 - arrival time -0.417 + required time 0.542 + arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.521ns (logic 0.273ns (52.394%) route 0.248ns (47.606%)) - Logic Levels: 2 (CARRY4=1 LUT4=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.454ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4927,20 +7669,15 @@ Slack (MET) : 0.122ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X80Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[3]/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X80Y155 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[3]/Q - net (fo=6, routed) 0.248 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[3] - SLICE_X84Y156 LUT4 (Prop_lut4_I1_O) 0.045 -0.244 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[11]_i_5/O - net (fo=1, routed) 0.000 -0.244 u_fft_mlkem_axi_slave_n_417 - SLICE_X84Y156 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.064 -0.180 r u_bf/u_barrett/qprod_s4_reg[11]_i_1/O[3] - net (fo=1, routed) 0.000 -0.180 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[3] - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/D + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/Q + net (fo=1, routed) 0.056 -0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0 + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -4950,384 +7687,34 @@ Slack (MET) : 0.122ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/C - clock pessimism 0.040 -0.436 - SLICE_X84Y156 FDCE (Hold_fdce_C_D) 0.134 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11] + net (fo=17272, routed) 0.854 -0.454 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + clock pessimism -0.226 -0.680 + SLICE_X65Y102 FDCE (Hold_fdce_C_D) 0.075 -0.605 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg ------------------------------------------------------------------- - required time 0.302 - arrival time -0.180 + required time 0.605 + arrival time -0.483 ------------------------------------------------------------------- slack 0.122 -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.124ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/Q - net (fo=1, routed) 0.222 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[11] - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.269 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_2/O - net (fo=1, routed) 0.000 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_2_n_0 - SLICE_X83Y156 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.063 -0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[3] - net (fo=1, routed) 0.000 -0.206 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[11] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.206 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[15]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[15]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[15]/Q - net (fo=1, routed) 0.222 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15] - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_2/O - net (fo=1, routed) 0.000 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_2_n_0 - SLICE_X83Y157 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.063 -0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[3] - net (fo=1, routed) 0.000 -0.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[15] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.207 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/Q - net (fo=1, routed) 0.222 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[19] - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_2/O - net (fo=1, routed) 0.000 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_2_n_0 - SLICE_X83Y158 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.063 -0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[3] - net (fo=1, routed) 0.000 -0.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[19] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.207 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]/Q - net (fo=1, routed) 0.222 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[23] - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_2/O - net (fo=1, routed) 0.000 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_2_n_0 - SLICE_X83Y159 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.063 -0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[3] - net (fo=1, routed) 0.000 -0.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[23] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.207 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.200ns (logic 0.141ns (70.589%) route 0.059ns (29.411%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.581 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.071 -0.510 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.510 - arrival time -0.384 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.227 -0.582 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.071 -0.511 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.511 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5337,15 +7724,15 @@ Slack (MET) : 0.126ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X115Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D + SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q + net (fo=1, routed) 0.059 -0.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[2] + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5355,34 +7742,203 @@ Slack (MET) : 0.126ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.226 -0.615 - SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.071 -0.544 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] + net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.226 -0.613 + SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.076 -0.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- - required time 0.544 - arrival time -0.418 + required time 0.537 + arrival time -0.414 + ------------------------------------------------------------------- + slack 0.124 + +Slack (MET) : 0.125ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.577ns (logic 0.231ns (40.066%) route 0.346ns (59.934%)) + Logic Levels: 2 (LUT3=1 LUT6=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.290ns + Source Clock Delay (SCD): -0.598ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.664 -0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk + SLICE_X135Y50 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/C + ------------------------------------------------------------------- ------------------- + SLICE_X135Y50 FDCE (Prop_fdce_C_Q) 0.141 -0.457 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[753]/Q + net (fo=2, routed) 0.126 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/data31[9] + SLICE_X135Y48 LUT6 (Prop_lut6_I0_O) 0.045 -0.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[753]_i_2/O + net (fo=1, routed) 0.220 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[493] + SLICE_X135Y48 LUT3 (Prop_lut3_I1_O) 0.045 -0.022 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[753]_i_1/O + net (fo=1, routed) 0.000 -0.022 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[753] + SLICE_X135Y48 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.018 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk + SLICE_X135Y48 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753]/C + clock pessimism 0.037 -0.253 + SLICE_X135Y48 FDCE (Hold_fdce_C_D) 0.107 -0.146 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[753] + ------------------------------------------------------------------- + required time 0.146 + arrival time -0.022 + ------------------------------------------------------------------- + slack 0.125 + +Slack (MET) : 0.125ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.512ns (logic 0.164ns (32.024%) route 0.348ns (67.976%)) + Logic Levels: 0 + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.594 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X108Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/C + ------------------------------------------------------------------- ------------------- + SLICE_X108Y100 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[15]/Q + net (fo=1, routed) 0.348 -0.157 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[15] + SLICE_X103Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X103Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15]/C + clock pessimism 0.040 -0.339 + SLICE_X103Y99 FDCE (Hold_fdce_C_D) 0.057 -0.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[15] + ------------------------------------------------------------------- + required time 0.282 + arrival time -0.157 + ------------------------------------------------------------------- + slack 0.125 + +Slack (MET) : 0.126ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X59Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q + net (fo=1, routed) 0.056 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2] + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.229 -0.612 + SLICE_X59Y91 FDCE (Hold_fdce_C_D) 0.071 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.541 + arrival time -0.415 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.614ns - Clock Pessimism Removal (CPR): 0.226ns + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5392,15 +7948,15 @@ Slack (MET) : 0.126ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + net (fo=17272, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/C ------------------------------------------------------------------- ------------------- - SLICE_X117Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D + SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[17]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[17] + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5410,34 +7966,256 @@ Slack (MET) : 0.126ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.226 -0.614 - SLICE_X117Y75 FDCE (Hold_fdce_C_D) 0.071 -0.543 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] + net (fo=17272, routed) 0.935 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17]/C + clock pessimism -0.229 -0.602 + SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.071 -0.531 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[17] ------------------------------------------------------------------- - required time 0.543 - arrival time -0.417 + required time 0.531 + arrival time -0.405 ------------------------------------------------------------------- slack 0.126 +Slack (MET) : 0.126ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.374ns + Source Clock Delay (SCD): -0.603ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.659 -0.603 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X115Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[1]/Q + net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[1] + SLICE_X115Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1]/C + clock pessimism -0.229 -0.603 + SLICE_X115Y91 FDCE (Hold_fdce_C_D) 0.071 -0.532 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[1] + ------------------------------------------------------------------- + required time 0.532 + arrival time -0.406 + ------------------------------------------------------------------- + slack 0.126 + +Slack (MET) : 0.126ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.373ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): 0.229ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/C + ------------------------------------------------------------------- ------------------- + SLICE_X115Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[21]/Q + net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[21] + SLICE_X115Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.935 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X115Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21]/C + clock pessimism -0.229 -0.602 + SLICE_X115Y96 FDCE (Hold_fdce_C_D) 0.071 -0.531 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[21] + ------------------------------------------------------------------- + required time 0.531 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.126 + +Slack (MET) : 0.127ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.711ns (logic 0.141ns (19.823%) route 0.570ns (80.177%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.598 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X137Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X137Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/Q + net (fo=10, routed) 0.570 0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[1] + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.004 -0.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mlkem_clk + RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKBWRCLK + clock pessimism 0.040 -0.263 + RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.046 + ------------------------------------------------------------------- + slack 0.127 + +Slack (MET) : 0.127ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[5] + (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.711ns (logic 0.141ns (19.823%) route 0.570ns (80.177%)) + Logic Levels: 0 + Clock Path Skew: 0.401ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.665ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.598 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk + SLICE_X137Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X137Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[1]/Q + net (fo=10, routed) 0.570 0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[1] + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[5] + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.004 -0.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mlkem_clk + RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKBWRCLK + clock pessimism 0.040 -0.263 + RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5]) + 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg + ------------------------------------------------------------------- + required time 0.080 + arrival time 0.046 + ------------------------------------------------------------------- + slack 0.127 + Slack (MET) : 0.128ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.527ns (logic 0.251ns (47.592%) route 0.276ns (52.408%)) - Logic Levels: 2 (CARRY4=1 LUT4=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5447,20 +8225,15 @@ Slack (MET) : 0.128ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[5]/C + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X82Y157 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[5]/Q - net (fo=7, routed) 0.276 -0.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[5] - SLICE_X84Y157 LUT4 (Prop_lut4_I0_O) 0.045 -0.240 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]_i_7/O - net (fo=1, routed) 0.000 -0.240 u_fft_mlkem_axi_slave_n_121 - SLICE_X84Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.065 -0.175 r u_bf/u_barrett/qprod_s4_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.175 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[6] - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/D + SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q + net (fo=1, routed) 0.058 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[1] + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5470,34 +8243,34 @@ Slack (MET) : 0.128ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - clock pessimism 0.040 -0.437 - SLICE_X84Y157 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14] + net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.226 -0.613 + SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.071 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- - required time 0.303 - arrival time -0.175 + required time 0.542 + arrival time -0.415 ------------------------------------------------------------------- slack 0.128 Slack (MET) : 0.129ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.526ns (logic 0.185ns (35.176%) route 0.341ns (64.824%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.255ns (logic 0.141ns (55.379%) route 0.114ns (44.621%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.443ns + Source Clock Delay (SCD): -0.670ns + Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5507,17 +8280,15 @@ Slack (MET) : 0.129ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/C + net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/mlkem_clk + SLICE_X123Y110 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X83Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/Q - net (fo=4, routed) 0.341 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[1] - SLICE_X84Y154 LUT3 (Prop_lut3_I0_O) 0.044 -0.176 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[1]_i_1/O - net (fo=1, routed) 0.000 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[1]_i_1_n_0 - SLICE_X84Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]/D + SLICE_X123Y110 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r_reg[3]/Q + net (fo=7, routed) 0.114 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_r[3] + SLICE_X120Y109 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5527,34 +8298,35 @@ Slack (MET) : 0.129ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]/C - clock pessimism 0.040 -0.436 - SLICE_X84Y154 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1] + net (fo=17272, routed) 0.865 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/mlkem_clk + SLICE_X120Y109 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK + clock pessimism -0.210 -0.653 + SLICE_X120Y109 SRL16E (Hold_srl16e_CLK_D) + 0.109 -0.544 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf0/a_d4_reg[3]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- - required time 0.305 - arrival time -0.176 + required time 0.544 + arrival time -0.415 ------------------------------------------------------------------- slack 0.129 Slack (MET) : 0.130ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D + (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.499ns (logic 0.292ns (58.570%) route 0.207ns (41.430%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.282ns (logic 0.141ns (49.987%) route 0.141ns (50.013%)) + Logic Levels: 0 + Clock Path Skew: 0.035ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.445ns + Source Clock Delay (SCD): -0.669ns + Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5564,20 +8336,15 @@ Slack (MET) : 0.130ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X85Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C + net (fo=17272, routed) 0.594 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X134Y112 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.106 -0.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[1] - net (fo=1, routed) 0.000 -0.202 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[1] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/D + SLICE_X134Y112 FDCE (Prop_fdce_C_Q) 0.141 -0.528 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[0]/Q + net (fo=5, routed) 0.141 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[0] + SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5587,34 +8354,146 @@ Slack (MET) : 0.130ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1] + net (fo=17272, routed) 0.863 -0.445 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk + SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK + clock pessimism -0.189 -0.634 + SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) + 0.117 -0.517 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[0]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- - required time 0.332 - arrival time -0.202 + required time 0.517 + arrival time -0.387 + ------------------------------------------------------------------- + slack 0.130 + +Slack (MET) : 0.130ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/I + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.313ns (logic 0.141ns (45.032%) route 0.172ns (54.968%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X57Y91 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[2]/Q + net (fo=1, routed) 0.172 -0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIB0 + SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK + SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK + clock pessimism -0.192 -0.573 + SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.427 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB + ------------------------------------------------------------------- + required time 0.427 + arrival time -0.297 + ------------------------------------------------------------------- + slack 0.130 + +Slack (MET) : 0.130ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.544ns (logic 0.141ns (25.911%) route 0.403ns (74.090%)) + Logic Levels: 0 + Clock Path Skew: 0.343ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.371ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.589 -0.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk + SLICE_X103Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.533 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0/Q + net (fo=1, routed) 0.403 -0.130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_0_n_0 + SLICE_X117Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.937 -0.371 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk + SLICE_X117Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1/C + clock pessimism 0.040 -0.331 + SLICE_X117Y99 FDCE (Hold_fdce_C_D) 0.071 -0.260 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/a0d_reg_c_1 + ------------------------------------------------------------------- + required time 0.260 + arrival time -0.130 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.131ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[352]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.531ns (logic 0.186ns (35.046%) route 0.345ns (64.954%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.337ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.315ns - Source Clock Delay (SCD): -0.612ns - Clock Pessimism Removal (CPR): -0.040ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5624,17 +8503,15 @@ Slack (MET) : 0.131ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.651 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X161Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[352]/C + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X161Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[352]/Q - net (fo=1, routed) 0.156 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[352] - SLICE_X161Y100 LUT2 (Prop_lut2_I0_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/r_r[96]_i_1/O - net (fo=2, routed) 0.189 -0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_hash[352] - SLICE_X158Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]/D + SLICE_X50Y83 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q + net (fo=1, routed) 0.065 -0.407 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[0] + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5644,34 +8521,34 @@ Slack (MET) : 0.131ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.993 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X158Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]/C - clock pessimism 0.040 -0.275 - SLICE_X158Y99 FDCE (Hold_fdce_C_D) 0.063 -0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96] + net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.226 -0.613 + SLICE_X50Y83 FDCE (Hold_fdce_C_D) 0.075 -0.538 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- - required time 0.212 - arrival time -0.081 + required time 0.538 + arrival time -0.407 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.164ns (34.335%) route 0.314ns (65.665%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.694ns - Clock Pessimism Removal (CPR): -0.045ns + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.382ns + Source Clock Delay (SCD): -0.611ns + Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5681,15 +8558,15 @@ Slack (MET) : 0.131ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.569 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X80Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[5]/C + net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X80Y149 FDCE (Prop_fdce_C_Q) 0.164 -0.530 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[5]/Q - net (fo=1, routed) 0.314 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3[5] - SLICE_X80Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]/D + SLICE_X54Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.470 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q + net (fo=1, routed) 0.065 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[1] + SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5699,89 +8576,34 @@ Slack (MET) : 0.131ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.832 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X80Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]/C - clock pessimism 0.045 -0.430 - SLICE_X80Y154 FDCE (Hold_fdce_C_D) 0.083 -0.347 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5] + net (fo=17272, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.229 -0.611 + SLICE_X54Y88 FDCE (Hold_fdce_C_D) 0.075 -0.536 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- - required time 0.347 - arrival time -0.216 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.454ns (logic 0.141ns (31.069%) route 0.313ns (68.931%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X85Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y159 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[0]/Q - net (fo=1, routed) 0.313 -0.248 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3[0] - SLICE_X82Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X82Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]/C - clock pessimism 0.040 -0.438 - SLICE_X82Y159 FDCE (Hold_fdce_C_D) 0.059 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0] - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.248 + required time 0.536 + arrival time -0.405 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.132ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.504ns (logic 0.249ns (49.413%) route 0.255ns (50.587%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.237ns (logic 0.186ns (78.504%) route 0.051ns (21.496%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5791,17 +8613,17 @@ Slack (MET) : 0.132ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/C + net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X84Y155 FDCE (Prop_fdce_C_Q) 0.148 -0.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/Q - net (fo=4, routed) 0.255 -0.298 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg_n_0_[5] - SLICE_X82Y151 LUT3 (Prop_lut3_I0_O) 0.101 -0.197 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r[5]_i_1/O - net (fo=1, routed) 0.000 -0.197 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r[5]_i_1_n_0 - SLICE_X82Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]/D + SLICE_X54Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/Q + net (fo=1, routed) 0.051 -0.421 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_burst_reg[1]_0[14] + SLICE_X55Y85 LUT4 (Prop_lut4_I0_O) 0.045 -0.376 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1/O + net (fo=1, routed) 0.000 -0.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[14]_i_1_n_0 + SLICE_X55Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5811,94 +8633,34 @@ Slack (MET) : 0.132ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.832 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]/C - clock pessimism 0.040 -0.436 - SLICE_X82Y151 FDCE (Hold_fdce_C_D) 0.107 -0.329 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5] + net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X55Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14]/C + clock pessimism -0.215 -0.600 + SLICE_X55Y85 FDRE (Hold_fdre_C_D) 0.092 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[14] ------------------------------------------------------------------- - required time 0.329 - arrival time -0.197 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.503ns (logic 0.285ns (56.653%) route 0.218ns (43.347%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X85Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[3]) - 0.099 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[3] - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[3] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]/C - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.200 + required time 0.508 + arrival time -0.376 ------------------------------------------------------------------- slack 0.132 Slack (MET) : 0.133ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.480ns (logic 0.141ns (29.345%) route 0.339ns (70.655%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.530ns (logic 0.141ns (26.621%) route 0.389ns (73.379%)) Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.481ns - Source Clock Delay (SCD): -0.705ns + Clock Path Skew: 0.338ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.370ns + Source Clock Delay (SCD): -0.668ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5908,15 +8670,15 @@ Slack (MET) : 0.133ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.558 -0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X87Y164 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[20]/C + net (fo=17272, routed) 0.595 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/mlkem_clk + SLICE_X122Y105 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/C ------------------------------------------------------------------- ------------------- - SLICE_X87Y164 FDCE (Prop_fdce_C_Q) 0.141 -0.564 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[20]/Q - net (fo=1, routed) 0.339 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3[20] - SLICE_X80Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]/D + SLICE_X122Y105 FDCE (Prop_fdce_C_Q) 0.141 -0.527 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[16]/Q + net (fo=14, routed) 0.389 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p12_reg[23]_1[16] + SLICE_X128Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -5926,91 +8688,34 @@ Slack (MET) : 0.133ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.826 -0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X80Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]/C - clock pessimism 0.040 -0.441 - SLICE_X80Y165 FDCE (Hold_fdce_C_D) 0.084 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20] + net (fo=17272, routed) 0.938 -0.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/mlkem_clk + SLICE_X128Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16]/C + clock pessimism 0.040 -0.330 + SLICE_X128Y99 FDCE (Hold_fdce_C_D) 0.059 -0.271 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p22_reg[16] ------------------------------------------------------------------- - required time 0.357 - arrival time -0.224 + required time 0.271 + arrival time -0.138 ------------------------------------------------------------------- slack 0.133 -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5_reg[11]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.133ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[22]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[24]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.240ns (logic 0.186ns (77.515%) route 0.054ns (22.485%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.456ns - Source Clock Delay (SCD): -0.681ns - Clock Pessimism Removal (CPR): 0.212ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.582 -0.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk - SLICE_X58Y137 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X58Y137 FDCE (Prop_fdce_C_Q) 0.141 -0.540 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5_reg[11]/Q - net (fo=1, routed) 0.054 -0.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5[11] - SLICE_X59Y137 LUT5 (Prop_lut5_I0_O) 0.045 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r[11]_i_1/O - net (fo=1, routed) 0.000 -0.441 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r[11]_i_1_n_0 - SLICE_X59Y137 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.852 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk - SLICE_X59Y137 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]/C - clock pessimism -0.212 -0.668 - SLICE_X59Y137 FDCE (Hold_fdce_C_D) 0.091 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11] - ------------------------------------------------------------------- - required time 0.577 - arrival time -0.441 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[11]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.536ns (logic 0.250ns (46.632%) route 0.286ns (53.368%)) - Logic Levels: 2 (CARRY4=1 LUT4=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.702ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.466ns (logic 0.327ns (70.202%) route 0.139ns (29.798%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.198ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.449ns + Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -6020,20 +8725,21 @@ Slack (MET) : 0.137ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[11]/C + net (fo=17272, routed) 0.655 -0.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X103Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[22]/C ------------------------------------------------------------------- ------------------- - SLICE_X82Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[11]/Q - net (fo=8, routed) 0.286 -0.275 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3[11] - SLICE_X84Y158 LUT4 (Prop_lut4_I3_O) 0.045 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[19]_i_6/O - net (fo=1, routed) 0.000 -0.230 u_fft_mlkem_axi_slave_n_135 - SLICE_X84Y158 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.064 -0.166 r u_bf/u_barrett/qprod_s4_reg[19]_i_1/O[3] - net (fo=1, routed) 0.000 -0.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[11] - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/D + SLICE_X103Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[22]/Q + net (fo=2, routed) 0.138 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4[22] + SLICE_X102Y99 CARRY4 (Prop_carry4_DI[2]_CO[3]) + 0.133 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[23]_i_1/CO[3] + net (fo=1, routed) 0.001 -0.195 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[23]_i_1_n_0 + SLICE_X102Y100 CARRY4 (Prop_carry4_CI_O[0]) + 0.053 -0.142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[24]_i_1/O[0] + net (fo=1, routed) 0.000 -0.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s50[24] + SLICE_X102Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[24]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -6043,72 +8749,15 @@ Slack (MET) : 0.137ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/C - clock pessimism 0.040 -0.437 - SLICE_X84Y158 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19] + net (fo=17272, routed) 0.859 -0.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[24]/C + clock pessimism 0.040 -0.409 + SLICE_X102Y100 FDCE (Hold_fdce_C_D) 0.134 -0.275 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[24] ------------------------------------------------------------------- - required time 0.303 - arrival time -0.166 + required time 0.275 + arrival time -0.142 ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[6]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.498ns (logic 0.186ns (37.319%) route 0.312ns (62.681%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.269ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.570 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X89Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X89Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[6]/Q - net (fo=234, routed) 0.312 -0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] - SLICE_X86Y149 LUT6 (Prop_lut6_I2_O) 0.045 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[245][6]_i_1/O - net (fo=1, routed) 0.000 -0.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[245][6]_i_1_n_0 - SLICE_X86Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.839 -0.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X86Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]/C - clock pessimism 0.045 -0.424 - SLICE_X86Y149 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.194 - ------------------------------------------------------------------- - slack 0.138 + slack 0.133 @@ -6116,163 +8765,164 @@ Slack (MET) : 0.138ns (arrival time - required time) Pulse Width Checks -------------------------------------------------------------------------------------- -Clock Name: mlkem_clk_clk_pll -Waveform(ns): { 0.000 20.000 } -Period(ns): 40.000 +Clock Name: mlkem_clk +Waveform(ns): { 0.000 6.500 } +Period(ns): 13.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I -Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 40.000 38.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X103Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[897]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X101Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[898]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y118 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[899]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[89]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[900]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[901]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[902]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[903]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X56Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[904]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[905]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[906]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[907]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[908]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[909]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[90]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[910]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[911]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[912]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[913]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X92Y115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[914]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X148Y176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][3]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][4]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][5]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X125Y187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][6]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X132Y173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][7]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][8]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X150Y179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][9]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X130Y211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][0]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][10]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][11]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X121Y226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][1]/C -Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 40.000 120.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y39 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y38 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y40 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y41 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB36_X7Y14 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y37 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X8Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X6Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y44 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y43 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y42 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y45 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y39 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y38 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y40 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y41 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB36_X7Y14 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y37 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X8Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X6Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y44 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y43 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y42 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y45 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg/CLKBWRCLK +Min Period n/a BUFG/I n/a 2.155 13.000 10.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I +Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 13.000 11.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X160Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[0]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[1]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[2]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[3]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[4]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X160Y96 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[5]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[6]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X162Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cp_idx_reg[7]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X102Y84 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[94]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X105Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[95]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X102Y84 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[96]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X107Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[97]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X109Y78 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[98]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X111Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[99]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X127Y86 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[9]/C +Min Period n/a FDCE/C n/a 1.000 13.000 12.000 SLICE_X155Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/snt_ack_reg/C +Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 13.000 147.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK +>>>>>>> Stashed changes @@ -6281,26 +8931,84 @@ From Clock: sys_clk To Clock: sys_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.079ns, Total Violation 0.000ns +<<<<<<< Updated upstream +Hold : 0 Failing Endpoints, Worst Slack 0.040ns, Total Violation 0.000ns +======= +Hold : 0 Failing Endpoints, Worst Slack 0.024ns, Total Violation 0.000ns +>>>>>>> Stashed changes PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +<<<<<<< Updated upstream +Slack (MET) : 0.040ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_b_reg[1][23]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%)) + Data Path Delay: 0.443ns (logic 0.141ns (31.835%) route 0.302ns (68.165%)) Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.260ns - Source Clock Delay (SCD): -0.566ns + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.589 -0.674 u_matmul_axi_slave/sys_clk + SLICE_X47Y102 FDRE r u_matmul_axi_slave/m_in_b_reg[1][23]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y102 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_matmul_axi_slave/m_in_b_reg[1][23]/Q + net (fo=1, routed) 0.302 -0.231 u_matmul_axi_slave/mult_inst[1].u_mult/Q[23] + SLICE_X59Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.927 -0.381 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk + SLICE_X59Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/C + clock pessimism 0.040 -0.341 + SLICE_X59Y98 FDRE (Hold_fdre_C_D) 0.070 -0.271 u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23] + ------------------------------------------------------------------- + required time 0.271 + arrival time -0.231 + ------------------------------------------------------------------- + slack 0.040 + +Slack (MET) : 0.042ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.412ns (logic 0.187ns (45.442%) route 0.225ns (54.558%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.413ns + Source Clock Delay (SCD): -0.639ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6314,13 +9022,14 @@ Slack (MET) : 0.079ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.696 -0.566 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk - SLICE_X18Y50 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK + net (fo=35652, routed) 0.623 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X82Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C ------------------------------------------------------------------- ------------------- - SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.188 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31 - net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56 - SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D + SLICE_X82Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.498 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/Q + net (fo=3, routed) 0.225 -0.274 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg_n_0_[11] + SLICE_X85Y77 LUT3 (Prop_lut3_I2_O) 0.046 -0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/O + net (fo=1, routed) 0.000 -0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1_n_0 + SLICE_X85Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6332,31 +9041,46 @@ Slack (MET) : 0.079ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.048 -0.260 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk - SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/CLK - clock pessimism 0.037 -0.223 - SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32 + net (fo=35652, routed) 0.895 -0.413 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X85Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/C + clock pessimism 0.037 -0.376 + SLICE_X85Y77 FDCE (Hold_fdce_C_D) 0.107 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] ------------------------------------------------------------------- - required time 0.101 - arrival time -0.023 + required time 0.269 + arrival time -0.228 ------------------------------------------------------------------- - slack 0.079 + slack 0.042 -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I +Slack (MET) : 0.049ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.382ns (logic 0.141ns (36.898%) route 0.241ns (63.102%)) + Logic Levels: 0 + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.487ns + Source Clock Delay (SCD): -0.710ns + Clock Pessimism Removal (CPR): -0.040ns +======= +Slack (MET) : 0.024ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%)) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns +>>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6369,12 +9093,21 @@ Slack (MET) : 0.079ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_axi_uart_controller/uart0/regs/receiver/sys_clk - SLICE_X4Y57 FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.553 -0.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/sys_clk + SLICE_X85Y170 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q - net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I + SLICE_X85Y170 FDCE (Prop_fdce_C_Q) 0.141 -0.569 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/Q + net (fo=14, routed) 0.241 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[9] + SLICE_X81Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D +======= + net (fo=9971, routed) 0.652 -0.610 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X57Y90 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6386,84 +9119,288 @@ Slack (MET) : 0.079ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/CLK - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.378 - arrival time -0.299 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.080ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_axi_uart_controller/uart0/regs/receiver/sys_clk - SLICE_X4Y57 FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q - net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/CLK - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA +<<<<<<< Updated upstream + net (fo=35652, routed) 0.821 -0.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/sys_clk + SLICE_X81Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/C + clock pessimism 0.040 -0.447 + SLICE_X81Y171 FDCE (Hold_fdce_C_D) 0.070 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9] ------------------------------------------------------------------- required time 0.377 - arrival time -0.298 + arrival time -0.328 ------------------------------------------------------------------- - slack 0.080 + slack 0.049 -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C +Slack (MET) : 0.056ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D +======= + net (fo=9971, routed) 0.927 -0.381 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.287 + arrival time -0.263 + ------------------------------------------------------------------- + slack 0.024 + +Slack (MET) : 0.024ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.652 -0.610 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X57Y90 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.927 -0.381 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.287 + arrival time -0.263 + ------------------------------------------------------------------- + slack 0.024 + +Slack (MET) : 0.067ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D +>>>>>>> Stashed changes (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns +<<<<<<< Updated upstream + Data Path Delay: 0.508ns (logic 0.213ns (41.922%) route 0.295ns (58.078%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/sys_clk + SLICE_X112Y55 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/Q + net (fo=5, routed) 0.295 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[8] + SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.049 -0.094 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/O + net (fo=1, routed) 0.000 -0.094 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[8] + SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D +======= + net (fo=9971, routed) 0.559 -0.704 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X82Y130 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[19]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 + SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.063 -0.269 r u_axi_uart_controller/uart0/regs/M_next_carry/O[3] + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.014 -0.294 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/sys_clk + SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/C + clock pessimism 0.037 -0.257 + SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8] + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.056 + +Slack (MET) : 0.061ns (arrival time - required time) + Source: u_confreg/confreg_int_set_reg[11]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[11]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.376ns (logic 0.246ns (65.365%) route 0.130ns (34.635%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.335ns + Source Clock Delay (SCD): -0.494ns + Clock Pessimism Removal (CPR): -0.037ns +======= + net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/C + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.067 + +Slack (MET) : 0.071ns (arrival time - required time) + Source: u_matmul_axi_slave/req_1_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/busy_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.362ns (logic 0.186ns (51.410%) route 0.176ns (48.590%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.448ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.040ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.769 -0.494 u_confreg/sys_clk + SLICE_X8Y49 FDRE r u_confreg/confreg_int_set_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.148 -0.346 r u_confreg/confreg_int_set_reg[11]/Q + net (fo=2, routed) 0.130 -0.215 u_confreg/u_int_ctrl/edge_int_state_reg[31]_0[11] + SLICE_X8Y51 LUT4 (Prop_lut4_I2_O) 0.098 -0.117 r u_confreg/u_int_ctrl/edge_int_state[11]_i_1/O + net (fo=1, routed) 0.000 -0.117 u_confreg/u_int_ctrl/edge_int_state[11]_i_1_n_0 + SLICE_X8Y51 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[11]/D +======= + net (fo=9971, routed) 0.655 -0.607 u_matmul_axi_slave/sys_clk + SLICE_X45Y99 FDRE r u_matmul_axi_slave/req_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r u_matmul_axi_slave/req_1_reg/Q + net (fo=19, routed) 0.176 -0.291 u_matmul_axi_slave/p_5_in[1] + SLICE_X45Y100 LUT6 (Prop_lut6_I2_O) 0.045 -0.246 r u_matmul_axi_slave/busy_i_1/O + net (fo=1, routed) 0.000 -0.246 u_matmul_axi_slave/busy_i_1_n_0 + SLICE_X45Y100 FDRE r u_matmul_axi_slave/busy_reg/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.973 -0.335 u_confreg/u_int_ctrl/sys_clk + SLICE_X8Y51 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[11]/C + clock pessimism 0.037 -0.298 + SLICE_X8Y51 FDCE (Hold_fdce_C_D) 0.120 -0.178 u_confreg/u_int_ctrl/edge_int_state_reg[11] + ------------------------------------------------------------------- + required time 0.178 + arrival time -0.117 + ------------------------------------------------------------------- + slack 0.061 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D +======= + net (fo=9971, routed) 0.860 -0.448 u_matmul_axi_slave/sys_clk + SLICE_X45Y100 FDRE r u_matmul_axi_slave/busy_reg/C + clock pessimism 0.040 -0.408 + SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.091 -0.317 u_matmul_axi_slave/busy_reg + ------------------------------------------------------------------- + required time 0.317 + arrival time -0.246 + ------------------------------------------------------------------- + slack 0.071 + +Slack (MET) : 0.073ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.393ns (logic 0.227ns (57.716%) route 0.166ns (42.284%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.453ns + Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6477,12 +9414,14 @@ Slack (MET) : 0.083ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.630 -0.633 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y102 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C + net (fo=9971, routed) 0.650 -0.612 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/sys_clk + SLICE_X63Y98 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q - net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D + SLICE_X63Y98 FDRE (Prop_fdre_C_Q) 0.128 -0.484 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/Q + net (fo=7, routed) 0.166 -0.318 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[1] + SLICE_X62Y100 LUT6 (Prop_lut6_I1_O) 0.099 -0.219 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/O + net (fo=1, routed) 0.000 -0.219 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/p_1_in[2] + SLICE_X62Y100 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6494,29 +9433,473 @@ Slack (MET) : 0.083ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/C - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49] + net (fo=9971, routed) 0.855 -0.453 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/sys_clk + SLICE_X62Y100 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/C + clock pessimism 0.040 -0.413 + SLICE_X62Y100 FDRE (Hold_fdre_C_D) 0.121 -0.292 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2] ------------------------------------------------------------------- - required time 0.228 - arrival time -0.145 + required time 0.292 + arrival time -0.219 + ------------------------------------------------------------------- + slack 0.073 + +Slack (MET) : 0.073ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.437ns (logic 0.189ns (43.230%) route 0.248ns (56.770%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.257ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.486ns + Source Clock Delay (SCD): -0.703ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk + SLICE_X87Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q + net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] + SLICE_X82Y126 LUT4 (Prop_lut4_I2_O) 0.048 -0.266 r u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/O + net (fo=1, routed) 0.000 -0.266 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[19] + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.822 -0.486 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/C + clock pessimism 0.040 -0.446 + SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.107 -0.339 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19] + ------------------------------------------------------------------- + required time 0.339 + arrival time -0.266 + ------------------------------------------------------------------- + slack 0.073 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D +>>>>>>> Stashed changes + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.526ns (logic 0.210ns (39.912%) route 0.316ns (60.088%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): -0.037ns +======= + Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/sys_clk + SLICE_X112Y53 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y53 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/Q + net (fo=5, routed) 0.316 -0.122 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[10] + SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.046 -0.076 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/O + net (fo=1, routed) 0.000 -0.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[10] + SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D +======= + net (fo=9971, routed) 0.559 -0.704 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X82Y130 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) + 0.070 -0.262 r u_axi_uart_controller/uart0/regs/M_next_carry/O[0] + net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.014 -0.294 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/sys_clk + SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/C + clock pessimism 0.037 -0.257 + SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10] + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.076 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.076ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) + Logic Levels: 0 + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.313ns + Source Clock Delay (SCD): -0.546ns + Clock Pessimism Removal (CPR): 0.192ns +======= + net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/C + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.262 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.425ns (logic 0.209ns (49.172%) route 0.216ns (50.828%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.259ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.486ns + Source Clock Delay (SCD): -0.705ns + Clock Pessimism Removal (CPR): -0.040ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.716 -0.546 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X4Y67 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 +======= + net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk + SLICE_X84Y128 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y128 FDRE (Prop_fdre_C_Q) 0.164 -0.541 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/Q + net (fo=23, routed) 0.216 -0.325 u_Axi_CDC/wFifo/Q[19] + SLICE_X82Y126 LUT6 (Prop_lut6_I3_O) 0.045 -0.280 r u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/O + net (fo=1, routed) 0.000 -0.280 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[3] + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.995 -0.313 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK + clock pessimism -0.192 -0.505 + SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.120 + ------------------------------------------------------------------- + slack 0.076 + +Slack (MET) : 0.076ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) + Logic Levels: 0 + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.313ns + Source Clock Delay (SCD): -0.546ns + Clock Pessimism Removal (CPR): 0.192ns +======= + net (fo=9971, routed) 0.822 -0.486 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/C + clock pessimism 0.040 -0.446 + SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.092 -0.354 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3] + ------------------------------------------------------------------- + required time 0.354 + arrival time -0.280 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.080ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/ier_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.436ns (logic 0.209ns (47.943%) route 0.227ns (52.057%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.476ns + Source Clock Delay (SCD): -0.700ns + Clock Pessimism Removal (CPR): -0.040ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.716 -0.546 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X4Y67 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 +======= + net (fo=9971, routed) 0.563 -0.700 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X84Y133 FDRE r u_axi_uart_controller/uart0/regs/ier_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/ier_reg[3]/Q + net (fo=3, routed) 0.227 -0.309 u_axi_uart_controller/uart0/regs/transmitter/Q[0] + SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.264 r u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/O + net (fo=1, routed) 0.000 -0.264 u_axi_uart_controller/uart0/regs/transmitter_n_1 + SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.995 -0.313 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK + clock pessimism -0.192 -0.505 + SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.120 + ------------------------------------------------------------------- + slack 0.076 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 +======= + net (fo=9971, routed) 0.832 -0.476 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/C + clock pessimism 0.040 -0.436 + SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ms_int_pnd_reg + ------------------------------------------------------------------- + required time 0.344 + arrival time -0.264 + ------------------------------------------------------------------- + slack 0.080 + +Slack (MET) : 0.081ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.465ns (logic 0.186ns (40.004%) route 0.279ns (59.996%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.705ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk + SLICE_X85Y128 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X85Y128 FDRE (Prop_fdre_C_Q) 0.141 -0.564 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/Q + net (fo=20, routed) 0.279 -0.285 u_Axi_CDC/wFifo/Q[14] + SLICE_X80Y128 LUT5 (Prop_lut5_I4_O) 0.045 -0.240 r u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/O + net (fo=1, routed) 0.000 -0.240 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[14] + SLICE_X80Y128 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk + SLICE_X80Y128 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/C + clock pessimism 0.040 -0.441 + SLICE_X80Y128 FDRE (Hold_fdre_C_D) 0.120 -0.321 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14] + ------------------------------------------------------------------- + required time 0.321 + arrival time -0.240 + ------------------------------------------------------------------- + slack 0.081 + +Slack (MET) : 0.083ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/ier_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.439ns (logic 0.209ns (47.634%) route 0.230ns (52.366%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.476ns + Source Clock Delay (SCD): -0.700ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.563 -0.700 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X84Y133 FDRE r u_axi_uart_controller/uart0/regs/ier_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/ier_reg[0]/Q + net (fo=6, routed) 0.230 -0.306 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/Q[0] + SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.261 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/O + net (fo=1, routed) 0.000 -0.261 u_axi_uart_controller/uart0/regs/receiver_n_1 + SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.832 -0.476 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/C + clock pessimism 0.040 -0.436 + SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ti_int_pnd_reg + ------------------------------------------------------------------- + required time 0.344 + arrival time -0.261 ------------------------------------------------------------------- slack 0.083 -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%)) + Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.626ns + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6530,12 +9913,12 @@ Slack (MET) : 0.085ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.636 -0.626 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/sys_clk - SLICE_X62Y75 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C + net (fo=9971, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X43Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q - net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5] - RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] + SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q + net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/Q[7] + RAMB18_X2Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6547,30 +9930,1097 @@ Slack (MET) : 0.085ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.951 -0.357 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/sys_clk - RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK - clock pessimism -0.213 -0.570 - RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10]) - 0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg + net (fo=9971, routed) 0.962 -0.346 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/sys_clk + RAMB18_X2Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK + clock pessimism -0.213 -0.559 + RAMB18_X2Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg ------------------------------------------------------------------- - required time 0.387 - arrival time -0.302 + required time 0.376 + arrival time -0.292 ------------------------------------------------------------------- - slack 0.085 + slack 0.084 -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%)) + Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.568ns + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X43Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q + net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/Q[7] + RAMB18_X2Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.962 -0.346 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/sys_clk + RAMB18_X2Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK + clock pessimism -0.213 -0.559 + RAMB18_X2Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.292 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 +>>>>>>> Stashed changes + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.339ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): 0.192ns +======= + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.693 -0.569 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X15Y61 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 +======= + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.969 -0.339 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK + clock pessimism -0.192 -0.531 + SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.221 + arrival time -0.135 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 +======= + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 +>>>>>>> Stashed changes + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.339ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): 0.192ns +======= + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.693 -0.569 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X15Y61 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 +======= + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.969 -0.339 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK + clock pessimism -0.192 -0.531 + SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.221 + arrival time -0.135 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) +======= + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) +>>>>>>> Stashed changes + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns +======= + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 +======= + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) +======= + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) +>>>>>>> Stashed changes + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns +======= + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 +======= + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) +======= + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) +>>>>>>> Stashed changes + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns +======= + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 +======= + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) +======= + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) +>>>>>>> Stashed changes + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns +======= + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 +======= + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) +======= + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) +>>>>>>> Stashed changes + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns +======= + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 +======= + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) +======= + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) +>>>>>>> Stashed changes + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns +======= + Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): 0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 + SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK + SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK + clock pessimism -0.210 -0.687 + SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.291 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.434ns (logic 0.186ns (42.838%) route 0.248ns (57.162%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.257ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.486ns + Source Clock Delay (SCD): -0.703ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk + SLICE_X87Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q + net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] + SLICE_X82Y126 LUT5 (Prop_lut5_I2_O) 0.045 -0.269 r u_Axi_CDC/wFifo/reg_datai_32[11]_i_1/O + net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[11] + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.822 -0.486 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk + SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11]/C + clock pessimism 0.040 -0.446 + SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.091 -0.355 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[11] + ------------------------------------------------------------------- + required time 0.355 + arrival time -0.269 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_matmul_axi_slave/req_0_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/req_0_reg_rep__0/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.378ns (logic 0.186ns (49.193%) route 0.192ns (50.807%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.199ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.448ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.655 -0.607 u_matmul_axi_slave/sys_clk + SLICE_X45Y99 FDRE r u_matmul_axi_slave/req_0_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r u_matmul_axi_slave/req_0_reg/Q + net (fo=96, routed) 0.192 -0.274 u_matmul_axi_slave/p_5_in[0] + SLICE_X45Y100 LUT6 (Prop_lut6_I4_O) 0.045 -0.229 r u_matmul_axi_slave/req_0_rep_i_1__0/O + net (fo=1, routed) 0.000 -0.229 u_matmul_axi_slave/req_0_rep_i_1__0_n_0 + SLICE_X45Y100 FDRE r u_matmul_axi_slave/req_0_reg_rep__0/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.860 -0.448 u_matmul_axi_slave/sys_clk + SLICE_X45Y100 FDRE r u_matmul_axi_slave/req_0_reg_rep__0/C + clock pessimism 0.040 -0.408 + SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.092 -0.316 u_matmul_axi_slave/req_0_reg_rep__0 + ------------------------------------------------------------------- + required time 0.316 + arrival time -0.229 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/enable_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.186ns (42.057%) route 0.256ns (57.943%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.478ns + Source Clock Delay (SCD): -0.701ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.562 -0.701 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X86Y132 FDRE r u_axi_uart_controller/uart0/regs/enable_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y132 FDRE (Prop_fdre_C_Q) 0.141 -0.560 r u_axi_uart_controller/uart0/regs/enable_reg/Q + net (fo=12, routed) 0.256 -0.304 u_axi_uart_controller/uart0/regs/enable + SLICE_X83Y133 LUT4 (Prop_lut4_I1_O) 0.045 -0.259 r u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1/O + net (fo=1, routed) 0.000 -0.259 u_axi_uart_controller/uart0/regs/sclk_en_reg_i_1_n_0 + SLICE_X83Y133 FDRE r u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.830 -0.478 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X83Y133 FDRE r u_axi_uart_controller/uart0/regs/sclk_en_reg_reg/C + clock pessimism 0.040 -0.438 + SLICE_X83Y133 FDRE (Hold_fdre_C_D) 0.092 -0.346 u_axi_uart_controller/uart0/regs/sclk_en_reg_reg + ------------------------------------------------------------------- + required time 0.346 + arrival time -0.259 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 +======= + net (fo=9971, routed) 0.652 -0.610 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X57Y90 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.128 -0.482 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.236 -0.246 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_confreg/int_out_or_q1_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/int_out_or_q2_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.480ns (logic 0.141ns (29.360%) route 0.339ns (70.640%)) + Logic Levels: 0 + Clock Path Skew: 0.316ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.260ns + Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6584,13 +11034,12 @@ Slack (MET) : 0.096ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk - SLICE_X20Y50 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X4Y50 FDRE r u_confreg/int_out_or_q1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.190 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31 - net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55 - SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D + SLICE_X4Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/int_out_or_q1_reg/Q + net (fo=1, routed) 0.339 -0.059 u_confreg/int_out_or_q1 + SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6602,30 +11051,190 @@ Slack (MET) : 0.096ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.046 -0.262 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk - SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/CLK - clock pessimism 0.037 -0.225 - SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32 + net (fo=35652, routed) 1.048 -0.260 u_confreg/sys_clk + SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/C + clock pessimism 0.037 -0.223 + SLICE_X9Y47 FDRE (Hold_fdre_C_D) 0.075 -0.148 u_confreg/int_out_or_q2_reg ------------------------------------------------------------------- - required time 0.103 - arrival time -0.008 + required time 0.148 + arrival time -0.059 ------------------------------------------------------------------- - slack 0.096 + slack 0.089 -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%)) + Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.633ns + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X103Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q + net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[2] + RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.961 -0.347 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/sys_clk + RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK + clock pessimism -0.212 -0.559 + RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X103Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q + net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[2] + RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.961 -0.347 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/sys_clk + RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK + clock pessimism -0.212 -0.559 + RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.097ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.141ns (31.804%) route 0.302ns (68.196%)) + Logic Levels: 0 + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.644 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X157Y150 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C + ------------------------------------------------------------------- ------------------- + SLICE_X157Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/Q + net (fo=14, routed) 0.302 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[13] + SLICE_X159Y138 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X159Y138 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/C + clock pessimism 0.045 -0.343 + SLICE_X159Y138 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13] + ------------------------------------------------------------------- + required time 0.273 + arrival time -0.176 + ------------------------------------------------------------------- + slack 0.097 + +Slack (MET) : 0.098ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns + Source Clock Delay (SCD): -0.701ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6639,12 +11248,14 @@ Slack (MET) : 0.101ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.630 -0.633 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y102 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C + net (fo=35652, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X83Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q - net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D + SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q + net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 + SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/O + net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1_n_0 + SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6656,29 +11267,84 @@ Slack (MET) : 0.101ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/C - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51] + net (fo=35652, routed) 0.833 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/C + clock pessimism 0.040 -0.435 + SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.092 -0.343 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4] ------------------------------------------------------------------- - required time 0.229 - arrival time -0.128 + required time 0.343 + arrival time -0.245 ------------------------------------------------------------------- - slack 0.101 + slack 0.098 + +Slack (MET) : 0.099ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns + Source Clock Delay (SCD): -0.701ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X83Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + ------------------------------------------------------------------- ------------------- + SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q + net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 + SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/O + net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1_n_0 + SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.833 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/C + clock pessimism 0.040 -0.435 + SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.091 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3] + ------------------------------------------------------------------- + required time 0.344 + arrival time -0.245 + ------------------------------------------------------------------- + slack 0.099 Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C + Source: u_matmul_axi_slave/m_in_a_reg[1][28]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%)) + Data Path Delay: 0.496ns (logic 0.164ns (33.088%) route 0.332ns (66.911%)) Logic Levels: 0 Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.634ns + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.675ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6692,12 +11358,12 @@ Slack (MET) : 0.101ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.629 -0.634 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y104 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C + net (fo=35652, routed) 0.588 -0.675 u_matmul_axi_slave/sys_clk + SLICE_X44Y105 FDRE r u_matmul_axi_slave/m_in_a_reg[1][28]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q - net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D + SLICE_X44Y105 FDRE (Prop_fdre_C_Q) 0.164 -0.511 r u_matmul_axi_slave/m_in_a_reg[1][28]/Q + net (fo=1, routed) 0.332 -0.179 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[28] + SLICE_X56Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6709,30 +11375,30 @@ Slack (MET) : 0.101ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/C - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59] + net (fo=35652, routed) 0.929 -0.379 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk + SLICE_X56Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/C + clock pessimism 0.040 -0.339 + SLICE_X56Y98 FDRE (Hold_fdre_C_D) 0.059 -0.280 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28] ------------------------------------------------------------------- - required time 0.226 - arrival time -0.125 + required time 0.280 + arrival time -0.179 ------------------------------------------------------------------- slack 0.101 -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%)) + Data Path Delay: 0.451ns (logic 0.141ns (31.244%) route 0.310ns (68.756%)) Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6745,12 +11411,12 @@ Slack (MET) : 0.106ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.629 -0.634 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y104 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C + net (fo=35652, routed) 0.644 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X157Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q - net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/Q + net (fo=15, routed) 0.310 -0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[18] + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6762,30 +11428,191 @@ Slack (MET) : 0.106ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/C - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57] + net (fo=35652, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/C + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.070 -0.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18] ------------------------------------------------------------------- - required time 0.233 - arrival time -0.127 + required time 0.272 + arrival time -0.168 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X102Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q + net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[4] + RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.961 -0.347 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/sys_clk + RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK + clock pessimism -0.212 -0.559 + RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.270 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X102Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q + net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[4] + RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.961 -0.347 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/sys_clk + RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK + clock pessimism -0.212 -0.559 + RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.270 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.449ns (logic 0.141ns (31.381%) route 0.308ns (68.619%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.644 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X157Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C + ------------------------------------------------------------------- ------------------- + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/Q + net (fo=15, routed) 0.308 -0.170 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[17] + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/C + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.066 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17] + ------------------------------------------------------------------- + required time 0.276 + arrival time -0.170 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C + Source: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/buf_addr_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Data Path Delay: 0.425ns (logic 0.186ns (43.780%) route 0.239ns (56.220%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6798,12 +11625,14 @@ Slack (MET) : 0.108ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/sys_clk + SLICE_X13Y45 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 + SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/Q + net (fo=13, routed) 0.239 -0.115 u_Axi_CDC/arFifo/_zz_ram_port1[2] + SLICE_X16Y51 LUT5 (Prop_lut5_I1_O) 0.045 -0.070 r u_Axi_CDC/arFifo/buf_addr[2]_i_1/O + net (fo=1, routed) 0.000 -0.070 u_confreg/buf_addr_reg[15]_0[2] + SLICE_X16Y51 FDRE r u_confreg/buf_addr_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6815,31 +11644,30 @@ Slack (MET) : 0.108ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA + net (fo=35652, routed) 0.972 -0.336 u_confreg/sys_clk + SLICE_X16Y51 FDRE r u_confreg/buf_addr_reg[2]/C + clock pessimism 0.037 -0.299 + SLICE_X16Y51 FDRE (Hold_fdre_C_D) 0.121 -0.178 u_confreg/buf_addr_reg[2] ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 + required time 0.178 + arrival time -0.070 ------------------------------------------------------------------- slack 0.108 -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_confreg/digital_data_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) + Data Path Delay: 0.353ns (logic 0.141ns (39.954%) route 0.212ns (60.046%)) Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6852,12 +11680,12 @@ Slack (MET) : 0.108ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C + net (fo=35652, routed) 0.798 -0.465 u_confreg/sys_clk + SLICE_X0Y49 FDRE r u_confreg/digital_data_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 + SLICE_X0Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.324 r u_confreg/digital_data_reg[1]/Q + net (fo=2, routed) 0.212 -0.112 u_confreg/u_digitaltube_controller/dpy1_data_reg[3]_0[1] + SLICE_X0Y54 FDRE r u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6869,31 +11697,30 @@ Slack (MET) : 0.108ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 + net (fo=35652, routed) 1.002 -0.306 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y54 FDRE r u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/C + clock pessimism 0.037 -0.269 + SLICE_X0Y54 FDRE (Hold_fdre_C_D) 0.047 -0.222 u_confreg/u_digitaltube_controller/dpy0_data_reg[1] ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 + required time 0.222 + arrival time -0.112 ------------------------------------------------------------------- - slack 0.108 + slack 0.111 -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Data Path Delay: 0.410ns (logic 0.209ns (50.949%) route 0.201ns (49.051%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.192ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.371ns + Source Clock Delay (SCD): -0.527ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6906,12 +11733,14 @@ Slack (MET) : 0.108ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C + net (fo=35652, routed) 0.736 -0.527 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/sys_clk + SLICE_X116Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 + SLICE_X116Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.363 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/Q + net (fo=5, routed) 0.201 -0.162 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[3] + SLICE_X118Y50 LUT3 (Prop_lut3_I2_O) 0.045 -0.117 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/O + net (fo=1, routed) 0.000 -0.117 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[3] + SLICE_X118Y50 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6923,300 +11752,29 @@ Slack (MET) : 0.108ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB + net (fo=35652, routed) 0.937 -0.371 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/sys_clk + SLICE_X118Y50 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/C + clock pessimism 0.037 -0.334 + SLICE_X118Y50 FDRE (Hold_fdre_C_D) 0.107 -0.227 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3] ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 + required time 0.227 + arrival time -0.117 ------------------------------------------------------------------- - slack 0.108 + slack 0.111 -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) + Data Path Delay: 0.428ns (logic 0.141ns (32.928%) route 0.287ns (67.072%)) Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.490ns + Source Clock Delay (SCD): -0.711ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7230,12 +11788,12 @@ Slack (MET) : 0.108ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.630 -0.633 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y102 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C + net (fo=35652, routed) 0.552 -0.711 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/sys_clk + SLICE_X85Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q - net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D + SLICE_X85Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/Q + net (fo=14, routed) 0.287 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[12] + SLICE_X81Y173 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7247,30 +11805,1733 @@ Slack (MET) : 0.108ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/C - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48] + net (fo=35652, routed) 0.817 -0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/sys_clk + SLICE_X81Y173 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/C + clock pessimism 0.040 -0.450 + SLICE_X81Y173 FDCE (Hold_fdce_C_D) 0.055 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12] ------------------------------------------------------------------- - required time 0.232 - arrival time -0.124 + required time 0.395 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.112 + +Slack (MET) : 0.114ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.488ns (logic 0.231ns (47.314%) route 0.257ns (52.686%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.399ns + Source Clock Delay (SCD): -0.629ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.633 -0.629 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/sys_clk + SLICE_X83Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C + ------------------------------------------------------------------- ------------------- + SLICE_X83Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.501 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/Q + net (fo=118, routed) 0.257 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10_n_0 + SLICE_X85Y98 LUT2 (Prop_lut2_I0_O) 0.103 -0.141 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/O + net (fo=1, routed) 0.000 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1_n_0 + SLICE_X85Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.909 -0.399 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/sys_clk + SLICE_X85Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/C + clock pessimism 0.037 -0.362 + SLICE_X85Y98 FDCE (Hold_fdce_C_D) 0.107 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360] + ------------------------------------------------------------------- + required time 0.255 + arrival time -0.141 + ------------------------------------------------------------------- + slack 0.114 + +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/confreg_int_edge_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.798 -0.465 u_confreg/sys_clk + SLICE_X2Y49 FDRE r u_confreg/confreg_int_edge_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 r u_confreg/confreg_int_edge_reg[3]/Q + net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] + SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O + net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 + SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.003 -0.305 u_confreg/u_int_ctrl/sys_clk + SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/C + clock pessimism 0.037 -0.268 + SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] + ------------------------------------------------------------------- + required time 0.177 + arrival time -0.063 + ------------------------------------------------------------------- + slack 0.115 + +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.387ns (logic 0.141ns (36.445%) route 0.246ns (63.555%)) + Logic Levels: 0 + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.798 -0.465 u_confreg/u_int_ctrl/sys_clk + SLICE_X1Y49 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/Q + net (fo=3, routed) 0.246 -0.078 u_confreg/u_int_ctrl/int_in_sync_d2[5] + SLICE_X3Y51 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.003 -0.305 u_confreg/u_int_ctrl/sys_clk + SLICE_X3Y51 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/C + clock pessimism 0.037 -0.268 + SLICE_X3Y51 FDCE (Hold_fdce_C_D) 0.075 -0.193 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] + ------------------------------------------------------------------- + required time 0.193 + arrival time -0.078 + ------------------------------------------------------------------- + slack 0.115 + +Slack (MET) : 0.116ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.465ns (logic 0.141ns (30.326%) route 0.324ns (69.674%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.644 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X157Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/Q + net (fo=15, routed) 0.324 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[19] + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/C + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.072 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19] + ------------------------------------------------------------------- + required time 0.270 + arrival time -0.154 + ------------------------------------------------------------------- + slack 0.116 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 +======= + net (fo=9971, routed) 0.927 -0.381 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.255 -0.342 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.342 + arrival time -0.246 +>>>>>>> Stashed changes + ------------------------------------------------------------------- + slack 0.096 + +<<<<<<< Updated upstream +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.118ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.475ns (logic 0.209ns (44.013%) route 0.266ns (55.987%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.420ns + Source Clock Delay (SCD): -0.640ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.623 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X144Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + ------------------------------------------------------------------- ------------------- + SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q + net (fo=127, routed) 0.266 -0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 + SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.165 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/O + net (fo=1, routed) 0.000 -0.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1_n_0 + SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.887 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/C + clock pessimism 0.045 -0.375 + SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.092 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8] + ------------------------------------------------------------------- + required time 0.283 + arrival time -0.165 + ------------------------------------------------------------------- + slack 0.118 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.475ns (logic 0.209ns (44.040%) route 0.266ns (55.960%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.403ns + Source Clock Delay (SCD): -0.630ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.632 -0.630 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk + SLICE_X84Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y61 FDRE (Prop_fdre_C_Q) 0.164 -0.466 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/Q + net (fo=6, routed) 0.266 -0.201 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][14]__0_0[7] + SLICE_X82Y61 LUT6 (Prop_lut6_I3_O) 0.045 -0.156 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/O + net (fo=1, routed) 0.000 -0.156 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_re[7] + SLICE_X82Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.905 -0.403 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk + SLICE_X82Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/C + clock pessimism 0.037 -0.366 + SLICE_X82Y61 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7] + ------------------------------------------------------------------- + required time 0.274 + arrival time -0.156 + ------------------------------------------------------------------- + slack 0.119 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +======= +Slack (MET) : 0.096ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +>>>>>>> Stashed changes + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) + Logic Levels: 0 +<<<<<<< Updated upstream + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.418ns + Source Clock Delay (SCD): -0.645ns + Clock Pessimism Removal (CPR): 0.227ns +======= + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.610ns + Clock Pessimism Removal (CPR): 0.216ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.618 -0.645 u_matmul_axi_slave/mult_inst[3].u_mult/sys_clk + SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y105 FDRE (Prop_fdre_C_Q) 0.141 -0.504 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/Q + net (fo=1, routed) 0.056 -0.448 u_matmul_axi_slave/mult_inst[3].u_mult/prod[59] + SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D +======= + net (fo=9971, routed) 0.652 -0.610 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X57Y90 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.128 -0.482 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.236 -0.246 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.890 -0.418 u_matmul_axi_slave/mult_inst[3].u_mult/sys_clk + SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/C + clock pessimism -0.227 -0.645 + SLICE_X39Y105 FDRE (Hold_fdre_C_D) 0.078 -0.567 u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59] + ------------------------------------------------------------------- + required time 0.567 + arrival time -0.448 + ------------------------------------------------------------------- + slack 0.119 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.476ns (logic 0.209ns (43.921%) route 0.267ns (56.079%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.420ns + Source Clock Delay (SCD): -0.640ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.623 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X144Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + ------------------------------------------------------------------- ------------------- + SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q + net (fo=127, routed) 0.267 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 + SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.164 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/O + net (fo=1, routed) 0.000 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1_n_0 + SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.887 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/C + clock pessimism 0.045 -0.375 + SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.091 -0.284 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6] + ------------------------------------------------------------------- + required time 0.284 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.120 +======= + net (fo=9971, routed) 0.927 -0.381 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK + clock pessimism -0.216 -0.597 + SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.255 -0.342 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.342 + arrival time -0.246 + ------------------------------------------------------------------- + slack 0.096 +>>>>>>> Stashed changes + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_a_reg[1][14]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.368ns (logic 0.141ns (38.301%) route 0.227ns (61.699%)) + Logic Levels: 0 +<<<<<<< Updated upstream + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.234ns +======= + Clock Path Skew: 0.198ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.411ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): -0.040ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X9Y43 FDCE (Prop_fdce_C_Q) 0.141 -0.354 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q + net (fo=1, routed) 0.056 -0.298 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D +======= + net (fo=9971, routed) 0.693 -0.569 u_matmul_axi_slave/sys_clk + SLICE_X23Y99 FDRE r u_matmul_axi_slave/m_in_a_reg[1][14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X23Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.428 r u_matmul_axi_slave/m_in_a_reg[1][14]/Q + net (fo=1, routed) 0.227 -0.201 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[14] + SLICE_X23Y107 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.234 -0.495 + SLICE_X9Y43 FDCE (Hold_fdce_C_D) 0.076 -0.419 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.419 + arrival time -0.298 + ------------------------------------------------------------------- + slack 0.121 +======= + net (fo=9971, routed) 0.897 -0.411 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk + SLICE_X23Y107 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14]/C + clock pessimism 0.040 -0.371 + SLICE_X23Y107 FDRE (Hold_fdre_C_D) 0.070 -0.301 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[14] + ------------------------------------------------------------------- + required time 0.301 + arrival time -0.201 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.453ns (logic 0.186ns (41.032%) route 0.267ns (58.968%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.262ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.480ns + Source Clock Delay (SCD): -0.702ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk + SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/Q + net (fo=20, routed) 0.267 -0.294 u_Axi_CDC/wFifo/Q[6] + SLICE_X81Y129 LUT6 (Prop_lut6_I5_O) 0.045 -0.249 r u_Axi_CDC/wFifo/reg_datai_32[6]_i_1/O + net (fo=1, routed) 0.000 -0.249 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[6] + SLICE_X81Y129 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.828 -0.480 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk + SLICE_X81Y129 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6]/C + clock pessimism 0.040 -0.440 + SLICE_X81Y129 FDRE (Hold_fdre_C_D) 0.091 -0.349 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[6] + ------------------------------------------------------------------- + required time 0.349 + arrival time -0.249 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.102ns (arrival time - required time) + Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.455ns (logic 0.186ns (40.841%) route 0.269ns (59.159%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.482ns + Source Clock Delay (SCD): -0.703ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk + SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/Q + net (fo=20, routed) 0.269 -0.293 u_Axi_CDC/wFifo/Q[0] + SLICE_X79Y127 LUT6 (Prop_lut6_I5_O) 0.045 -0.248 r u_Axi_CDC/wFifo/reg_datai_32[0]_i_1/O + net (fo=1, routed) 0.000 -0.248 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[0] + SLICE_X79Y127 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.826 -0.482 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk + SLICE_X79Y127 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0]/C + clock pessimism 0.040 -0.442 + SLICE_X79Y127 FDRE (Hold_fdre_C_D) 0.092 -0.350 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[0] + ------------------------------------------------------------------- + required time 0.350 + arrival time -0.248 + ------------------------------------------------------------------- + slack 0.102 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1 + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1 + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1 + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/CLK + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.105ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.452ns (logic 0.141ns (31.171%) route 0.311ns (68.829%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.311 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/ADDRD0 + SLICE_X70Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK + clock pessimism -0.192 -0.579 + SLICE_X70Y97 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1 + ------------------------------------------------------------------- + required time 0.269 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.105 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.240ns (logic 0.186ns (77.466%) route 0.054ns (22.534%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.456ns + Source Clock Delay (SCD): -0.682ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.581 -0.682 u_cdma_matmul_bridge/sys_clk + SLICE_X63Y110 FDRE r u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/C + ------------------------------------------------------------------- ------------------- + SLICE_X63Y110 FDRE (Prop_fdre_C_Q) 0.141 -0.541 r u_cdma_matmul_bridge/bank_dst_addr_reg[1][20]/Q + net (fo=1, routed) 0.054 -0.487 u_cdma_matmul_bridge/bank_dst_addr_reg[1]_3[20] + SLICE_X62Y110 LUT6 (Prop_lut6_I0_O) 0.045 -0.442 r u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1/O + net (fo=1, routed) 0.000 -0.442 u_cdma_matmul_bridge/cdma_wr_req_dst[20]_i_1_n_0 + SLICE_X62Y110 FDRE r u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.852 -0.456 u_cdma_matmul_bridge/sys_clk + SLICE_X62Y110 FDRE r u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20]/C + clock pessimism -0.213 -0.669 + SLICE_X62Y110 FDRE (Hold_fdre_C_D) 0.121 -0.548 u_cdma_matmul_bridge/cdma_wr_req_dst_reg[20] + ------------------------------------------------------------------- + required time 0.548 + arrival time -0.442 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.540ns (logic 0.186ns (34.444%) route 0.354ns (65.556%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.340ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.683ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.580 -0.683 u_Axi_CDC/arFifo/sys_clk + SLICE_X71Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C + ------------------------------------------------------------------- ------------------- + SLICE_X71Y100 FDRE (Prop_fdre_C_Q) 0.141 -0.542 r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/Q + net (fo=8, routed) 0.354 -0.188 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/_zz_ram_port1_reg[49][1] + SLICE_X63Y97 LUT6 (Prop_lut6_I5_O) 0.045 -0.143 r u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_6/cmdArbiter/ar_id_reg[1]_i_1/O + net (fo=2, routed) 0.000 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/I172[3] + SLICE_X63Y97 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X63Y97 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1]/C + clock pessimism 0.040 -0.343 + SLICE_X63Y97 FDRE (Hold_fdre_C_D) 0.092 -0.251 u_fft_mlkem_axi_slave/u_fft_controller/ar_id_reg_reg[1] + ------------------------------------------------------------------- + required time 0.251 + arrival time -0.143 ------------------------------------------------------------------- slack 0.108 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C +Slack (MET) : 0.110ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.478ns (logic 0.292ns (61.119%) route 0.186ns (38.881%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.481ns + Source Clock Delay (SCD): -0.704ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.559 -0.704 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X82Y130 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[16]/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q + net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] + SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O + net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 + SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[1]) + 0.106 -0.226 r u_axi_uart_controller/uart0/regs/M_next_carry/O[1] + net (fo=1, routed) 0.000 -0.226 u_axi_uart_controller/uart0/regs/M_next[1] + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[1]/C + clock pessimism 0.040 -0.441 + SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[1] + ------------------------------------------------------------------- + required time 0.336 + arrival time -0.226 + ------------------------------------------------------------------- + slack 0.110 + +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) + Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7283,12 +13544,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk - SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7300,31 +13561,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK + clock pessimism -0.213 -0.599 + SLICE_X68Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 + required time 0.289 + arrival time -0.178 ------------------------------------------------------------------- - slack 0.117 + slack 0.112 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) + Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7337,12 +13598,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk - SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7354,31 +13615,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + clock pessimism -0.213 -0.599 + SLICE_X68Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1 ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 + required time 0.289 + arrival time -0.178 ------------------------------------------------------------------- - slack 0.117 + slack 0.112 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) + Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7391,12 +13652,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk - SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7408,85 +13669,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB/CLK + clock pessimism -0.213 -0.599 + SLICE_X68Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 + required time 0.289 + arrival time -0.178 ------------------------------------------------------------------- - slack 0.117 + slack 0.112 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk - SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7499,12 +13706,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7516,31 +13723,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK + clock pessimism -0.213 -0.599 + SLICE_X68Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB_D1 ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.289 + arrival time -0.178 ------------------------------------------------------------------- - slack 0.117 + slack 0.112 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7553,12 +13760,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7570,31 +13777,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC/CLK + clock pessimism -0.213 -0.599 + SLICE_X68Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.289 + arrival time -0.178 ------------------------------------------------------------------- - slack 0.117 + slack 0.112 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7607,12 +13814,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7624,193 +13831,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK + clock pessimism -0.213 -0.599 + SLICE_X68Y97 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC_D1 ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.289 + arrival time -0.178 ------------------------------------------------------------------- - slack 0.117 + slack 0.112 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7823,12 +13868,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 + SLICE_X68Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7840,31 +13885,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X68Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD/CLK + clock pessimism -0.213 -0.599 + SLICE_X68Y97 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.289 + arrival time -0.178 ------------------------------------------------------------------- - slack 0.117 + slack 0.112 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.439ns (logic 0.141ns (32.128%) route 0.298ns (67.872%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.616ns + Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7877,12 +13922,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=9971, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X69Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 + SLICE_X69Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q + net (fo=60, routed) 0.298 -0.178 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/ADDRD0 + SLICE_X68Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7894,31 +13939,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 + net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X68Y97 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD_D1/CLK + clock pessimism -0.213 -0.599 + SLICE_X68Y97 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD_D1 ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.289 + arrival time -0.178 ------------------------------------------------------------------- - slack 0.117 + slack 0.112 -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/dl_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Data Path Delay: 0.455ns (logic 0.164ns (36.056%) route 0.291ns (63.944%)) Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns + Clock Path Skew: 0.270ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.707ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7931,12 +13976,12 @@ Slack (MET) : 0.121ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + net (fo=9971, routed) 0.556 -0.707 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk + SLICE_X80Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D + SLICE_X80Y126 FDRE (Prop_fdre_C_Q) 0.164 -0.543 r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_reg[2]/Q + net (fo=10, routed) 0.291 -0.252 u_axi_uart_controller/uart0/regs/infrared_reg_0[2] + SLICE_X85Y133 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7948,865 +13993,17 @@ Slack (MET) : 0.121ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] + net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X85Y133 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[10]/C + clock pessimism 0.040 -0.437 + SLICE_X85Y133 FDRE (Hold_fdre_C_D) 0.070 -0.367 u_axi_uart_controller/uart0/regs/dl_reg[10] ------------------------------------------------------------------- - required time 0.496 - arrival time -0.375 + required time 0.367 + arrival time -0.252 ------------------------------------------------------------------- - slack 0.121 + slack 0.115 -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.960 -0.348 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0 - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.999 -0.309 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.232 -0.541 - SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.466 - arrival time -0.344 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.539ns - Clock Pessimism Removal (CPR): 0.231ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0 - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/C - clock pessimism -0.231 -0.539 - SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0] - ------------------------------------------------------------------- - required time 0.464 - arrival time -0.342 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.603ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.659 -0.603 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q - net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0] - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C - clock pessimism -0.229 -0.603 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] - ------------------------------------------------------------------- - required time 0.528 - arrival time -0.406 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.675 -0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.227 -0.587 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.512 - arrival time -0.390 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0 - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.229 -0.570 - SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.582 - SLICE_X27Y71 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.569ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.693 -0.569 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.372 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.230 -0.569 - SLICE_X15Y88 FDCE (Hold_fdce_C_D) 0.075 -0.494 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.494 - arrival time -0.372 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.229 -0.570 - SLICE_X15Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): 0.226ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X113Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.226 -0.615 - SLICE_X113Y75 FDCE (Hold_fdce_C_D) 0.075 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.540 - arrival time -0.418 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.589%) route 0.059ns (29.411%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.796 -0.467 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X4Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.326 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.059 -0.267 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.236 -0.467 - SLICE_X4Y49 FDCE (Hold_fdce_C_D) 0.076 -0.391 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.391 - arrival time -0.267 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.125ns (arrival time - required time) +Slack (MET) : 0.119ns (arrival time - required time) Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D @@ -8814,65 +14011,12 @@ Slack (MET) : 0.125ns (arrival time - required time) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.203ns (logic 0.141ns (69.572%) route 0.062ns (30.428%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.796 -0.467 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X4Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.326 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.062 -0.264 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.236 -0.467 - SLICE_X4Y49 FDCE (Hold_fdce_C_D) 0.078 -0.389 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.389 - arrival time -0.264 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.699ns + Clock Pessimism Removal (CPR): 0.222ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -8885,12 +14029,12 @@ Slack (MET) : 0.126ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D + SLICE_X89Y126 FDCE (Prop_fdce_C_Q) 0.141 -0.558 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q + net (fo=1, routed) 0.056 -0.502 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[3] + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -8902,68 +14046,16 @@ Slack (MET) : 0.126ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.071 -0.501 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.222 -0.699 + SLICE_X89Y126 FDCE (Hold_fdce_C_D) 0.078 -0.621 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- - required time 0.501 - arrival time -0.375 + required time 0.621 + arrival time -0.502 ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.960 -0.348 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.071 -0.505 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.505 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.126 + slack 0.119 +>>>>>>> Stashed changes @@ -8977,6152 +14069,311 @@ Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK +<<<<<<< Updated upstream +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X5Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X5Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y28 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y28 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB36_X7Y18 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X5Y11 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X5Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y7 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X5Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X5Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X7Y18 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y68 cdma_axil_b_bridge_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X24Y67 cdma_axil_r_bridge_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y67 cdma_axil_wr_active_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y67 cdma_axil_wr_bridge_hold_reg/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[1]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[5]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[6]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[7]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[9]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[11]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X20Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[13]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[14]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[1]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[2]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[3]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[4]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[5]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[6]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[7]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[9]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[13]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[14]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[15]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[16]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[17]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[18]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[19]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y63 u_cdma_matmul_bridge/load_next_idx_reg[1]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[20]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[21]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[22]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[23]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y69 u_cdma_matmul_bridge/load_next_idx_reg[24]/C +Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X141Y157 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[105][11]/C Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: sys_clk - To Clock: mlkem_clk_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.054ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.054ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 0.067 - arrival time -0.013 - ------------------------------------------------------------------- - slack 0.054 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.056 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.113ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.678ns (logic 0.478ns (70.458%) route 0.200ns (29.542%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O - net (fo=1, routed) 0.200 0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.046 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13] - ------------------------------------------------------------------- - required time 0.014 - arrival time 0.099 - ------------------------------------------------------------------- - slack 0.113 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.641ns (logic 0.394ns (61.457%) route 0.247ns (38.543%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.189 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/O - net (fo=1, routed) 0.247 0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[38] - SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X24Y76 FDRE (Hold_fdre_C_D) -0.007 -0.069 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 0.069 - arrival time 0.058 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.129ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.720ns (logic 0.478ns (66.344%) route 0.242ns (33.656%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/O - net (fo=1, routed) 0.242 0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[37] - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X27Y76 FDRE (Hold_fdre_C_D) 0.070 0.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.008 - arrival time 0.137 - ------------------------------------------------------------------- - slack 0.129 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.629ns (logic 0.394ns (62.601%) route 0.235ns (37.399%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.186 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/O - net (fo=1, routed) 0.235 0.049 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[32] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) -0.027 -0.085 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32] - ------------------------------------------------------------------- - required time 0.085 - arrival time 0.049 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.725ns (logic 0.388ns (53.539%) route 0.337ns (46.461%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/O - net (fo=1, routed) 0.337 0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[39] - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X27Y76 FDRE (Hold_fdre_C_D) 0.066 0.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39] - ------------------------------------------------------------------- - required time -0.004 - arrival time 0.141 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.666ns (logic 0.492ns (73.905%) route 0.174ns (26.095%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X22Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.090 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O - net (fo=1, routed) 0.174 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.006 -0.054 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42] - ------------------------------------------------------------------- - required time 0.054 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.668ns (logic 0.492ns (73.684%) route 0.176ns (26.316%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/O - net (fo=1, routed) 0.176 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[36] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.005 -0.055 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 0.055 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.734ns (logic 0.386ns (52.563%) route 0.348ns (47.437%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.197 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/O - net (fo=1, routed) 0.348 0.151 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[41] - SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X24Y76 FDRE (Hold_fdre_C_D) 0.070 0.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41] - ------------------------------------------------------------------- - required time -0.008 - arrival time 0.151 - ------------------------------------------------------------------- - slack 0.143 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.386ns (52.125%) route 0.355ns (47.875%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/O - net (fo=1, routed) 0.355 0.160 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[35] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.072 0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time -0.012 - arrival time 0.160 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.153ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.670ns (logic 0.394ns (58.792%) route 0.276ns (41.208%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.186 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/O - net (fo=1, routed) 0.276 0.090 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[32] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) -0.003 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32] - ------------------------------------------------------------------- - required time 0.063 - arrival time 0.090 - ------------------------------------------------------------------- - slack 0.153 - -Slack (MET) : 0.157ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.681ns (logic 0.390ns (57.280%) route 0.291ns (42.720%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.193 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/O - net (fo=1, routed) 0.291 0.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[40] - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X27Y76 FDRE (Hold_fdre_C_D) 0.002 -0.060 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40] - ------------------------------------------------------------------- - required time 0.060 - arrival time 0.097 - ------------------------------------------------------------------- - slack 0.157 - -Slack (MET) : 0.167ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.767ns (logic 0.164ns (21.391%) route 0.603ns (78.609%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y87 FDCE (Prop_fdce_C_Q) 0.164 -0.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.603 0.196 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[1] - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.243 - clock uncertainty 0.197 -0.047 - SLICE_X14Y86 FDCE (Hold_fdce_C_D) 0.076 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time -0.029 - arrival time 0.196 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.170ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.754ns (logic 0.141ns (18.697%) route 0.613ns (81.303%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/Q - net (fo=1, routed) 0.613 0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[3] - SLICE_X16Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X16Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.099 -0.243 - clock uncertainty 0.197 -0.047 - SLICE_X16Y86 FDCE (Hold_fdce_C_D) 0.059 0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time -0.012 - arrival time 0.183 - ------------------------------------------------------------------- - slack 0.170 - -Slack (MET) : 0.182ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.775ns (logic 0.478ns (61.697%) route 0.297ns (38.303%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y70 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/O - net (fo=1, routed) 0.297 0.195 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[49] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.071 0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49] - ------------------------------------------------------------------- - required time -0.013 - arrival time 0.195 - ------------------------------------------------------------------- - slack 0.182 - -Slack (MET) : 0.194ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.714ns (logic 0.394ns (55.191%) route 0.320ns (44.809%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X22Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.188 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/O - net (fo=1, routed) 0.320 0.132 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[44] - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X27Y76 FDRE (Hold_fdre_C_D) -0.001 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44] - ------------------------------------------------------------------- - required time 0.063 - arrival time 0.132 - ------------------------------------------------------------------- - slack 0.194 - -Slack (MET) : 0.195ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.388ns (50.735%) route 0.377ns (49.265%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.192 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/O - net (fo=1, routed) 0.377 0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[33] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.047 -0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time 0.011 - arrival time 0.184 - ------------------------------------------------------------------- - slack 0.195 - -Slack (MET) : 0.198ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.768ns (logic 0.141ns (18.369%) route 0.627ns (81.631%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.616ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk - SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.627 0.151 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[1] - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.289 - clock uncertainty 0.197 -0.093 - SLICE_X117Y75 FDCE (Hold_fdce_C_D) 0.046 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.047 - arrival time 0.151 - ------------------------------------------------------------------- - slack 0.198 - -Slack (MET) : 0.205ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.775ns (logic 0.141ns (18.187%) route 0.634ns (81.813%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk - SLICE_X27Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.634 0.193 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[0] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.046 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.012 - arrival time 0.193 - ------------------------------------------------------------------- - slack 0.205 - -Slack (MET) : 0.220ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.738ns (logic 0.128ns (17.350%) route 0.610ns (82.650%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.616ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk - SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.128 -0.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=4, routed) 0.610 0.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[3] - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.099 -0.289 - clock uncertainty 0.197 -0.093 - SLICE_X117Y75 FDCE (Hold_fdce_C_D) -0.006 -0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.099 - arrival time 0.121 - ------------------------------------------------------------------- - slack 0.220 - -Slack (MET) : 0.225ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.748ns (logic 0.390ns (52.130%) route 0.358ns (47.870%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.358 0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[34] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.002 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.168 - ------------------------------------------------------------------- - slack 0.225 - -Slack (MET) : 0.227ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.815ns (logic 0.141ns (17.291%) route 0.674ns (82.709%)) - Logic Levels: 0 - Clock Path Skew: 0.322ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.361ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk - SLICE_X27Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.674 0.231 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[0] - SLICE_X32Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.947 -0.361 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X32Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.262 - clock uncertainty 0.197 -0.066 - SLICE_X32Y74 FDCE (Hold_fdce_C_D) 0.070 0.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time -0.004 - arrival time 0.231 - ------------------------------------------------------------------- - slack 0.227 - -Slack (MET) : 0.228ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.766ns (logic 0.128ns (16.716%) route 0.638ns (83.284%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk - SLICE_X27Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y73 FDCE (Prop_fdce_C_Q) 0.128 -0.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.638 0.181 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y74 FDCE (Hold_fdce_C_D) 0.018 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.047 - arrival time 0.181 - ------------------------------------------------------------------- - slack 0.228 - -Slack (MET) : 0.234ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.781ns (logic 0.148ns (18.960%) route 0.633ns (81.040%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y87 FDCE (Prop_fdce_C_Q) 0.148 -0.422 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.633 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[2] - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.243 - clock uncertainty 0.197 -0.047 - SLICE_X14Y86 FDCE (Hold_fdce_C_D) 0.023 -0.024 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.024 - arrival time 0.210 - ------------------------------------------------------------------- - slack 0.234 - -Slack (MET) : 0.236ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.831ns (logic 0.386ns (46.464%) route 0.445ns (53.536%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/O - net (fo=1, routed) 0.445 0.250 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[35] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.072 0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time -0.014 - arrival time 0.250 - ------------------------------------------------------------------- - slack 0.236 - -Slack (MET) : 0.238ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.827ns (logic 0.141ns (17.044%) route 0.686ns (82.956%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk - SLICE_X27Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.686 0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[1] - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y74 FDCE (Hold_fdce_C_D) 0.070 0.005 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time -0.005 - arrival time 0.243 - ------------------------------------------------------------------- - slack 0.238 - -Slack (MET) : 0.241ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.823ns (logic 0.388ns (47.171%) route 0.435ns (52.829%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.192 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/O - net (fo=1, routed) 0.435 0.242 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[33] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.061 0.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time -0.001 - arrival time 0.242 - ------------------------------------------------------------------- - slack 0.241 - -Slack (MET) : 0.257ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.827ns (logic 0.141ns (17.047%) route 0.686ns (82.953%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X26Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.686 0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[1] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.047 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.013 - arrival time 0.245 - ------------------------------------------------------------------- - slack 0.257 - -Slack (MET) : 0.259ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.857ns (logic 0.164ns (19.129%) route 0.693ns (80.871%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y87 FDCE (Prop_fdce_C_Q) 0.164 -0.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.693 0.287 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[0] - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.243 - clock uncertainty 0.197 -0.047 - SLICE_X14Y86 FDCE (Hold_fdce_C_D) 0.075 0.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time -0.028 - arrival time 0.287 - ------------------------------------------------------------------- - slack 0.259 - -Slack (MET) : 0.259ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.788ns (logic 0.492ns (62.440%) route 0.296ns (37.560%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y68 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O - net (fo=1, routed) 0.296 0.211 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.009 -0.049 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 0.049 - arrival time 0.211 - ------------------------------------------------------------------- - slack 0.259 - -Slack (MET) : 0.262ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.788ns (logic 0.492ns (62.458%) route 0.296ns (37.542%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y70 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.087 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/O - net (fo=1, routed) 0.296 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[48] - SLICE_X26Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X26Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X26Y70 FDRE (Hold_fdre_C_D) 0.004 -0.054 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48] - ------------------------------------------------------------------- - required time 0.054 - arrival time 0.208 - ------------------------------------------------------------------- - slack 0.262 - -Slack (MET) : 0.272ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.793ns (logic 0.492ns (62.032%) route 0.301ns (37.968%)) - Logic Levels: 0 - Clock Path Skew: 0.320ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.358ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.087 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O - net (fo=1, routed) 0.301 0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12] - SLICE_X25Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.950 -0.358 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X25Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/C - clock pessimism 0.099 -0.259 - clock uncertainty 0.197 -0.063 - SLICE_X25Y74 FDRE (Hold_fdre_C_D) 0.004 -0.059 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12] - ------------------------------------------------------------------- - required time 0.059 - arrival time 0.214 - ------------------------------------------------------------------- - slack 0.272 - -Slack (MET) : 0.287ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.856ns (logic 0.141ns (16.478%) route 0.715ns (83.522%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.616ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk - SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.715 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[0] - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.290 - clock uncertainty 0.197 -0.094 - SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.046 -0.048 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.048 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.287 - -Slack (MET) : 0.289ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.861ns (logic 0.141ns (16.382%) route 0.720ns (83.618%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk - SLICE_X27Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.720 0.278 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[1] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.047 -0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.011 - arrival time 0.278 - ------------------------------------------------------------------- - slack 0.289 - -Slack (MET) : 0.319ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.916ns (logic 0.478ns (52.162%) route 0.438ns (47.838%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X22Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.104 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/O - net (fo=1, routed) 0.438 0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[43] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.075 0.015 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43] - ------------------------------------------------------------------- - required time -0.015 - arrival time 0.334 - ------------------------------------------------------------------- - slack 0.319 - -Slack (MET) : 0.351ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.933ns (logic 0.478ns (51.242%) route 0.455ns (48.758%)) - Logic Levels: 0 - Clock Path Skew: 0.319ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/O - net (fo=1, routed) 0.455 0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[49] - SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X31Y76 FDRE (Hold_fdre_C_D) 0.066 0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49] - ------------------------------------------------------------------- - required time -0.002 - arrival time 0.353 - ------------------------------------------------------------------- - slack 0.351 - -Slack (MET) : 0.363ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.879ns (logic 0.128ns (14.560%) route 0.751ns (85.440%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X26Y72 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.751 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[2] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.067 - arrival time 0.297 - ------------------------------------------------------------------- - slack 0.363 - -Slack (MET) : 0.364ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.953ns (logic 0.388ns (40.695%) route 0.565ns (59.305%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O - net (fo=1, routed) 0.565 0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.070 0.010 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time -0.010 - arrival time 0.374 - ------------------------------------------------------------------- - slack 0.364 - -Slack (MET) : 0.389ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.957ns (logic 0.141ns (14.730%) route 0.816ns (85.270%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X26Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.816 0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[0] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.046 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.014 - arrival time 0.375 - ------------------------------------------------------------------- - slack 0.389 - -Slack (MET) : 0.405ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.922ns (logic 0.128ns (13.878%) route 0.794ns (86.122%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk - SLICE_X27Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y77 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.794 0.340 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) -0.007 -0.065 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.065 - arrival time 0.340 - ------------------------------------------------------------------- - slack 0.405 - -Slack (MET) : 0.464ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.033ns (logic 0.141ns (13.645%) route 0.892ns (86.355%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.616ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk - SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=2, routed) 0.892 0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[2] - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.290 - clock uncertainty 0.197 -0.094 - SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.047 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.047 - arrival time 0.417 - ------------------------------------------------------------------- - slack 0.464 - -Slack (MET) : 0.480ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.000ns (logic 0.492ns (49.207%) route 0.508ns (50.793%)) - Logic Levels: 0 - Clock Path Skew: 0.319ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.087 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O - net (fo=1, routed) 0.508 0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48] - SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X31Y76 FDRE (Hold_fdre_C_D) 0.004 -0.060 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48] - ------------------------------------------------------------------- - required time 0.060 - arrival time 0.420 - ------------------------------------------------------------------- - slack 0.480 - -Slack (MET) : 0.497ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.967ns (logic 0.394ns (40.759%) route 0.573ns (59.241%)) - Logic Levels: 0 - Clock Path Skew: 0.283ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.400ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/O - net (fo=1, routed) 0.573 0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[2] - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.908 -0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/C - clock pessimism 0.099 -0.301 - clock uncertainty 0.197 -0.105 - SLICE_X76Y67 FDRE (Hold_fdre_C_D) -0.010 -0.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2] - ------------------------------------------------------------------- - required time 0.115 - arrival time 0.382 - ------------------------------------------------------------------- - slack 0.497 - -Slack (MET) : 0.502ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.108ns (logic 0.386ns (34.837%) route 0.722ns (65.163%)) - Logic Levels: 0 - Clock Path Skew: 0.339ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.387ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 0.722 0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[11] - SLICE_X110Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X110Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/C - clock pessimism 0.099 -0.288 - clock uncertainty 0.197 -0.092 - SLICE_X110Y72 FDRE (Hold_fdre_C_D) 0.070 -0.022 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11] - ------------------------------------------------------------------- - required time 0.022 - arrival time 0.481 - ------------------------------------------------------------------- - slack 0.502 - -Slack (MET) : 0.533ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.124ns (logic 0.388ns (34.515%) route 0.736ns (65.485%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 0.736 0.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[9] - SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X100Y72 FDRE (Hold_fdre_C_D) 0.063 -0.037 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9] - ------------------------------------------------------------------- - required time 0.037 - arrival time 0.497 - ------------------------------------------------------------------- - slack 0.533 - -Slack (MET) : 0.632ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.187ns (logic 0.386ns (32.521%) route 0.801ns (67.479%)) - Logic Levels: 0 - Clock Path Skew: 0.282ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.400ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.197 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/O - net (fo=1, routed) 0.801 0.604 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[11] - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.908 -0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/C - clock pessimism 0.099 -0.301 - clock uncertainty 0.197 -0.105 - SLICE_X76Y67 FDRE (Hold_fdre_C_D) 0.076 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11] - ------------------------------------------------------------------- - required time 0.029 - arrival time 0.604 - ------------------------------------------------------------------- - slack 0.632 - -Slack (MET) : 0.642ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.159ns (logic 0.394ns (33.980%) route 0.765ns (66.020%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.765 0.532 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[8] - SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X100Y72 FDRE (Hold_fdre_C_D) -0.010 -0.110 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 0.110 - arrival time 0.532 - ------------------------------------------------------------------- - slack 0.642 - -Slack (MET) : 0.658ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.258ns (logic 0.386ns (30.689%) route 0.872ns (69.311%)) - Logic Levels: 0 - Clock Path Skew: 0.340ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.385ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.240 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.872 0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[35] - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/C - clock pessimism 0.099 -0.286 - clock uncertainty 0.197 -0.090 - SLICE_X116Y77 FDRE (Hold_fdre_C_D) 0.063 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.631 - ------------------------------------------------------------------- - slack 0.658 - -Slack (MET) : 0.705ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.170ns (logic 0.390ns (33.342%) route 0.780ns (66.658%)) - Logic Levels: 0 - Clock Path Skew: 0.283ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.400ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 0.780 0.585 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[4] - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.908 -0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/C - clock pessimism 0.099 -0.301 - clock uncertainty 0.197 -0.105 - SLICE_X76Y67 FDRE (Hold_fdre_C_D) -0.015 -0.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 0.120 - arrival time 0.585 - ------------------------------------------------------------------- - slack 0.705 - - - - - ---------------------------------------------------------------------------------------------------- -From Clock: mlkem_clk_clk_pll - To Clock: sys_clk - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.032ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.032ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.053 - arrival time -0.021 - ------------------------------------------------------------------- - slack 0.032 - -Slack (MET) : 0.042ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 0.061 - arrival time -0.019 - ------------------------------------------------------------------- - slack 0.042 - -Slack (MET) : 0.066ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.915 -0.393 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.020 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] - SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.002 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.087ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.089 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] - SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.029 - ------------------------------------------------------------------- - slack 0.087 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.119 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.081 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 0.025 - arrival time 0.096 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.656ns (logic 0.492ns (75.032%) route 0.164ns (24.968%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O - net (fo=1, routed) 0.164 0.078 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) 0.004 -0.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 0.050 - arrival time 0.078 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.130ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.648ns (logic 0.394ns (60.840%) route 0.254ns (39.160%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.187 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O - net (fo=1, routed) 0.254 0.066 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) -0.007 -0.064 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32] - ------------------------------------------------------------------- - required time 0.064 - arrival time 0.066 - ------------------------------------------------------------------- - slack 0.130 - -Slack (MET) : 0.142ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.739ns (logic 0.478ns (64.724%) route 0.261ns (35.276%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.146 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 0.261 0.114 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.072 -0.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25] - ------------------------------------------------------------------- - required time 0.028 - arrival time 0.114 - ------------------------------------------------------------------- - slack 0.142 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.492ns (73.994%) route 0.173ns (26.006%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.399ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 0.173 0.038 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] - SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.909 -0.399 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C - clock pessimism 0.099 -0.300 - clock uncertainty 0.197 -0.104 - SLICE_X62Y76 FDRE (Hold_fdre_C_D) -0.007 -0.111 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18] - ------------------------------------------------------------------- - required time 0.111 - arrival time 0.038 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.172ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.699ns (logic 0.390ns (55.761%) route 0.309ns (44.239%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 0.309 0.075 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.003 -0.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28] - ------------------------------------------------------------------- - required time 0.097 - arrival time 0.075 - ------------------------------------------------------------------- - slack 0.172 - -Slack (MET) : 0.172ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.141ns (19.033%) route 0.600ns (80.967%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.600 0.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[1] - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.290 - clock uncertainty 0.197 -0.094 - SLICE_X113Y75 FDCE (Hold_fdce_C_D) 0.047 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.047 - arrival time 0.125 - ------------------------------------------------------------------- - slack 0.172 - -Slack (MET) : 0.173ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.390ns (56.076%) route 0.305ns (43.924%)) - Logic Levels: 0 - Clock Path Skew: 0.322ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK - SLICE_X22Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 0.305 0.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] - SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X28Y72 FDRE (Hold_fdre_C_D) 0.004 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.115 - ------------------------------------------------------------------- - slack 0.173 - -Slack (MET) : 0.178ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.141ns (18.448%) route 0.623ns (81.552%)) - Logic Levels: 0 - Clock Path Skew: 0.329ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=3, routed) 0.623 0.193 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.242 - clock uncertainty 0.197 -0.046 - SLICE_X15Y87 FDCE (Hold_fdce_C_D) 0.061 0.015 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time -0.015 - arrival time 0.193 - ------------------------------------------------------------------- - slack 0.178 - -Slack (MET) : 0.180ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.709ns (logic 0.390ns (55.003%) route 0.319ns (44.997%)) - Logic Levels: 0 - Clock Path Skew: 0.330ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.236 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 0.319 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.002 -0.098 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16] - ------------------------------------------------------------------- - required time 0.098 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.180 - -Slack (MET) : 0.187ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.766ns (logic 0.164ns (21.399%) route 0.602ns (78.601%)) - Logic Levels: 0 - Clock Path Skew: 0.337ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.612ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X112Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X112Y71 FDCE (Prop_fdce_C_Q) 0.164 -0.448 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q - net (fo=2, routed) 0.602 0.154 u_fft_mlkem_axi_slave/mlkem_intr_m - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - clock pessimism 0.099 -0.275 - clock uncertainty 0.197 -0.079 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.046 -0.033 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0] - ------------------------------------------------------------------- - required time 0.033 - arrival time 0.154 - ------------------------------------------------------------------- - slack 0.187 - -Slack (MET) : 0.189ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.758ns (logic 0.141ns (18.596%) route 0.617ns (81.404%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/Q - net (fo=1, routed) 0.617 0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[3] - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.099 -0.289 - clock uncertainty 0.197 -0.093 - SLICE_X114Y76 FDCE (Hold_fdce_C_D) 0.047 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.143 - ------------------------------------------------------------------- - slack 0.189 - -Slack (MET) : 0.199ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.767ns (logic 0.141ns (18.390%) route 0.626ns (81.610%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.626 0.151 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[0] - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.290 - clock uncertainty 0.197 -0.094 - SLICE_X113Y75 FDCE (Hold_fdce_C_D) 0.046 -0.048 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.048 - arrival time 0.151 - ------------------------------------------------------------------- - slack 0.199 - -Slack (MET) : 0.200ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.721ns (logic 0.390ns (54.106%) route 0.331ns (45.894%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 0.331 0.093 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.915 -0.393 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) -0.009 -0.107 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22] - ------------------------------------------------------------------- - required time 0.107 - arrival time 0.093 - ------------------------------------------------------------------- - slack 0.200 - -Slack (MET) : 0.211ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.780ns (logic 0.141ns (18.081%) route 0.639ns (81.919%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.675 -0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X31Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.639 0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[1] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.046 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.019 - arrival time 0.192 - ------------------------------------------------------------------- - slack 0.211 - -Slack (MET) : 0.216ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.790ns (logic 0.141ns (17.837%) route 0.649ns (82.163%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.649 0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.240 - clock uncertainty 0.197 -0.044 - SLICE_X15Y88 FDCE (Hold_fdce_C_D) 0.047 0.003 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time -0.003 - arrival time 0.219 - ------------------------------------------------------------------- - slack 0.216 - -Slack (MET) : 0.221ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.844ns (logic 0.386ns (45.725%) route 0.458ns (54.275%)) - Logic Levels: 0 - Clock Path Skew: 0.361ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.235 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 0.458 0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X29Y76 FDRE (Hold_fdre_C_D) 0.066 0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11] - ------------------------------------------------------------------- - required time -0.002 - arrival time 0.223 - ------------------------------------------------------------------- - slack 0.221 - -Slack (MET) : 0.228ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.822ns (logic 0.388ns (47.208%) route 0.434ns (52.792%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.189 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O - net (fo=1, routed) 0.434 0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.245 - ------------------------------------------------------------------- - slack 0.228 - -Slack (MET) : 0.233ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.802ns (logic 0.141ns (17.574%) route 0.661ns (82.426%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.661 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[1] - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.255 - clock uncertainty 0.197 -0.059 - SLICE_X27Y71 FDCE (Hold_fdce_C_D) 0.046 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.013 - arrival time 0.220 - ------------------------------------------------------------------- - slack 0.233 - -Slack (MET) : 0.234ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.803ns (logic 0.141ns (17.555%) route 0.662ns (82.445%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.675 -0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X31Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.662 0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.047 -0.018 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.018 - arrival time 0.216 - ------------------------------------------------------------------- - slack 0.234 - -Slack (MET) : 0.236ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.807ns (logic 0.141ns (17.466%) route 0.666ns (82.534%)) - Logic Levels: 0 - Clock Path Skew: 0.329ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.666 0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.255 - clock uncertainty 0.197 -0.059 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.046 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.013 - arrival time 0.223 - ------------------------------------------------------------------- - slack 0.236 - -Slack (MET) : 0.238ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.811ns (logic 0.141ns (17.379%) route 0.670ns (82.621%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.670 0.240 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.240 - clock uncertainty 0.197 -0.044 - SLICE_X15Y88 FDCE (Hold_fdce_C_D) 0.046 0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time -0.002 - arrival time 0.240 - ------------------------------------------------------------------- - slack 0.238 - -Slack (MET) : 0.241ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.746ns (logic 0.492ns (65.912%) route 0.254ns (34.088%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 0.254 0.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) -0.019 -0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24] - ------------------------------------------------------------------- - required time 0.119 - arrival time 0.122 - ------------------------------------------------------------------- - slack 0.241 - -Slack (MET) : 0.246ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.850ns (logic 0.388ns (45.663%) route 0.462ns (54.337%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.236 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 0.462 0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.076 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27] - ------------------------------------------------------------------- - required time 0.021 - arrival time 0.225 - ------------------------------------------------------------------- - slack 0.246 - -Slack (MET) : 0.247ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.848ns (logic 0.386ns (45.530%) route 0.462ns (54.470%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 0.462 0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.076 -0.024 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29] - ------------------------------------------------------------------- - required time 0.024 - arrival time 0.223 - ------------------------------------------------------------------- - slack 0.247 - -Slack (MET) : 0.249ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.822ns (logic 0.386ns (46.947%) route 0.436ns (53.053%)) - Logic Levels: 0 - Clock Path Skew: 0.330ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.240 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.436 0.196 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.047 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17] - ------------------------------------------------------------------- - required time 0.053 - arrival time 0.196 - ------------------------------------------------------------------- - slack 0.249 - -Slack (MET) : 0.252ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.824ns (logic 0.141ns (17.122%) route 0.683ns (82.878%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.683 0.240 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.255 - clock uncertainty 0.197 -0.059 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.047 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.012 - arrival time 0.240 - ------------------------------------------------------------------- - slack 0.252 - -Slack (MET) : 0.255ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.845ns (logic 0.478ns (56.587%) route 0.367ns (43.413%)) - Logic Levels: 0 - Clock Path Skew: 0.321ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.103 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 0.367 0.263 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X29Y76 FDRE (Hold_fdre_C_D) 0.072 0.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31] - ------------------------------------------------------------------- - required time -0.008 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.255 - -Slack (MET) : 0.256ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.828ns (logic 0.141ns (17.038%) route 0.687ns (82.962%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.687 0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[1] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.255 - clock uncertainty 0.197 -0.059 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.047 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.012 - arrival time 0.244 - ------------------------------------------------------------------- - slack 0.256 - -Slack (MET) : 0.260ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.829ns (logic 0.141ns (16.998%) route 0.688ns (83.002%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.588ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.674 -0.588 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X33Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.447 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.688 0.241 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] - SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X30Y74 FDCE (Hold_fdce_C_D) 0.046 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.019 - arrival time 0.241 - ------------------------------------------------------------------- - slack 0.260 - -Slack (MET) : 0.261ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.776ns (logic 0.128ns (16.502%) route 0.648ns (83.498%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.128 -0.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.648 0.160 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.289 - clock uncertainty 0.197 -0.093 - SLICE_X114Y76 FDCE (Hold_fdce_C_D) -0.008 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.101 - arrival time 0.160 - ------------------------------------------------------------------- - slack 0.261 - -Slack (MET) : 0.266ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.785ns (logic 0.128ns (16.296%) route 0.657ns (83.704%)) - Logic Levels: 0 - Clock Path Skew: 0.329ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.128 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=5, routed) 0.657 0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.099 -0.242 - clock uncertainty 0.197 -0.046 - SLICE_X15Y87 FDCE (Hold_fdce_C_D) -0.006 -0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.052 - arrival time 0.214 - ------------------------------------------------------------------- - slack 0.266 - -Slack (MET) : 0.268ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.823ns (logic 0.394ns (47.859%) route 0.429ns (52.141%)) - Logic Levels: 0 - Clock Path Skew: 0.360ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.429 0.202 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y75 FDRE (Hold_fdre_C_D) -0.001 -0.066 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 0.066 - arrival time 0.202 - ------------------------------------------------------------------- - slack 0.268 - -Slack (MET) : 0.290ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.868ns (logic 0.478ns (55.096%) route 0.390ns (44.904%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.149 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 0.390 0.240 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.047 -0.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19] - ------------------------------------------------------------------- - required time 0.050 - arrival time 0.240 - ------------------------------------------------------------------- - slack 0.290 - -Slack (MET) : 0.311ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.837ns (logic 0.394ns (47.100%) route 0.443ns (52.900%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 0.443 0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) -0.002 -0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26] - ------------------------------------------------------------------- - required time 0.099 - arrival time 0.212 - ------------------------------------------------------------------- - slack 0.311 - -Slack (MET) : 0.319ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.942ns (logic 0.388ns (41.191%) route 0.554ns (58.809%)) - Logic Levels: 0 - Clock Path Skew: 0.360ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 0.554 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y75 FDRE (Hold_fdre_C_D) 0.066 0.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3] - ------------------------------------------------------------------- - required time -0.001 - arrival time 0.321 - ------------------------------------------------------------------- - slack 0.319 - -Slack (MET) : 0.323ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.955ns (logic 0.388ns (40.612%) route 0.567ns (59.388%)) - Logic Levels: 0 - Clock Path Skew: 0.360ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 0.567 0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y75 FDRE (Hold_fdre_C_D) 0.076 0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9] - ------------------------------------------------------------------- - required time -0.011 - arrival time 0.334 - ------------------------------------------------------------------- - slack 0.323 - -Slack (MET) : 0.346ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.883ns (logic 0.128ns (14.500%) route 0.755ns (85.500%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.755 0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X26Y73 FDCE (Hold_fdce_C_D) 0.016 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.300 - ------------------------------------------------------------------- - slack 0.346 - -Slack (MET) : 0.347ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.851ns (logic 0.394ns (46.280%) route 0.457ns (53.720%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 0.457 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) -0.026 -0.123 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20] - ------------------------------------------------------------------- - required time 0.123 - arrival time 0.224 - ------------------------------------------------------------------- - slack 0.347 - -Slack (MET) : 0.402ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.983ns (logic 0.141ns (14.340%) route 0.842ns (85.660%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.842 0.401 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] - SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X24Y73 FDCE (Hold_fdce_C_D) 0.061 -0.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.001 - arrival time 0.401 - ------------------------------------------------------------------- - slack 0.402 - -Slack (MET) : 0.410ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.005ns (logic 0.388ns (38.609%) route 0.617ns (61.391%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.193 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O - net (fo=1, routed) 0.617 0.424 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.070 0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time -0.013 - arrival time 0.424 - ------------------------------------------------------------------- - slack 0.410 - -Slack (MET) : 0.416ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.986ns (logic 0.492ns (49.918%) route 0.494ns (50.082%)) - Logic Levels: 0 - Clock Path Skew: 0.361ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.129 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 0.494 0.364 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X28Y76 FDRE (Hold_fdre_C_D) 0.012 -0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 0.052 - arrival time 0.364 - ------------------------------------------------------------------- - slack 0.416 - -Slack (MET) : 0.420ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.054ns (logic 0.386ns (36.630%) route 0.668ns (63.370%)) - Logic Levels: 0 - Clock Path Skew: 0.361ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.235 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 0.668 0.432 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X28Y76 FDRE (Hold_fdre_C_D) 0.076 0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5] - ------------------------------------------------------------------- - required time -0.012 - arrival time 0.432 - ------------------------------------------------------------------- - slack 0.420 - - +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y61 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y61 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA_D1/CLK +======= +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X2Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X2Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X2Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X2Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y6 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK +Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I +Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y121 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[34]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y121 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[35]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[36]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[37]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[38]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y122 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[39]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X11Y112 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[3]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[40]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[41]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[42]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X9Y123 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[43]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X69Y104 cdma_axil_b_bridge_reg/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X46Y92 u_matmul_axi_slave/b0_b_reg[0][0]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X72Y108 cdma_axil_r_bridge_reg/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X67Y105 cdma_axil_wr_active_reg/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X69Y105 cdma_axil_wr_bridge_hold_reg/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X12Y105 u_matmul_axi_slave/b0_b_reg[0][10]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y92 u_matmul_axi_slave/b0_b_reg[0][11]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y79 u_matmul_axi_slave/b0_b_reg[0][12]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X4Y86 u_matmul_axi_slave/b0_b_reg[0][13]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X22Y103 u_matmul_axi_slave/b0_b_reg[0][14]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X2Y94 u_matmul_axi_slave/b0_b_reg[0][15]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X4Y86 u_matmul_axi_slave/b0_b_reg[0][16]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X37Y77 u_matmul_axi_slave/b0_b_reg[0][17]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X34Y76 u_matmul_axi_slave/b0_b_reg[0][18]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X47Y74 u_matmul_axi_slave/b0_b_reg[0][19]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y92 u_matmul_axi_slave/b0_b_reg[0][1]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X46Y78 u_matmul_axi_slave/b0_b_reg[0][20]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y69 u_matmul_axi_slave/b0_b_reg[0][21]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X2Y94 u_matmul_axi_slave/b0_b_reg[0][22]/C +Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y77 u_matmul_axi_slave/b0_c_reg_r2_0_15_54_59/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y92 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y97 u_matmul_axi_slave/b0_c_reg_r1_0_15_6_11/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y80 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA_D1/CLK +>>>>>>> Stashed changes @@ -15132,508 +14383,18 @@ From Clock: cpu_clk To Clock: cpu_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.651ns, Total Violation 0.000ns +<<<<<<< Updated upstream +Hold : 0 Failing Endpoints, Worst Slack 0.727ns, Total Violation 0.000ns +======= +Hold : 0 Failing Endpoints, Worst Slack 0.681ns, Total Violation 0.000ns +>>>>>>> Stashed changes --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.885ns (arrival time - required time) +<<<<<<< Updated upstream +Slack (MET) : 0.727ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR @@ -15641,122 +14402,12 @@ Slack (MET) : 0.885ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) + Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns + Destination Clock Delay (DCD): -0.263ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -15768,15 +14419,15 @@ Slack (MET) : 0.936ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -15787,403 +14438,18 @@ Slack (MET) : 0.936ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/bFifo/cpu_clk + SLICE_X11Y39 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.218 -0.481 + SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 + required time 0.573 + arrival time 0.154 ------------------------------------------------------------------- - slack 0.936 + slack 0.727 -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 1.005ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.192 -0.530 - SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.383 - ------------------------------------------------------------------- - slack 1.005 - -Slack (MET) : 1.005ns (arrival time - required time) +Slack (MET) : 0.727ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR @@ -16191,12 +14457,12 @@ Slack (MET) : 1.005ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%)) + Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.263ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16208,15 +14474,15 @@ Slack (MET) : 1.005ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16227,18 +14493,73 @@ Slack (MET) : 1.005ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.192 -0.530 - SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/bFifo/cpu_clk + SLICE_X11Y39 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.218 -0.481 + SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.383 + required time 0.573 + arrival time 0.154 ------------------------------------------------------------------- - slack 1.005 + slack 0.727 -Slack (MET) : 1.005ns (arrival time - required time) +Slack (MET) : 0.765ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.547 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.765 + +Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR @@ -16246,12 +14567,12 @@ Slack (MET) : 1.005ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16263,15 +14584,15 @@ Slack (MET) : 1.005ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16282,73 +14603,18 @@ Slack (MET) : 1.005ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.192 -0.530 - SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.383 + required time 0.547 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.005 + slack 0.765 -Slack (MET) : 1.005ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.192 -0.530 - SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.383 - ------------------------------------------------------------------- - slack 1.005 - -Slack (MET) : 1.012ns (arrival time - required time) +Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR @@ -16356,12 +14622,12 @@ Slack (MET) : 1.012ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16373,15 +14639,15 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16392,73 +14658,18 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 + required time 0.547 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.012 + slack 0.765 -Slack (MET) : 1.012ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.012ns (arrival time - required time) +Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR @@ -16466,12 +14677,12 @@ Slack (MET) : 1.012ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16483,15 +14694,15 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16502,18 +14713,18 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 + required time 0.547 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.012 + slack 0.765 -Slack (MET) : 1.012ns (arrival time - required time) +Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR @@ -16521,12 +14732,12 @@ Slack (MET) : 1.012ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16538,15 +14749,15 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16557,73 +14768,18 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 + required time 0.547 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.012 + slack 0.765 -Slack (MET) : 1.012ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.012ns (arrival time - required time) +Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR @@ -16631,12 +14787,12 @@ Slack (MET) : 1.012ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16648,15 +14804,15 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16667,31 +14823,45 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 + required time 0.547 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.012 + slack 0.765 -Slack (MET) : 1.012ns (arrival time - required time) +Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) +======= +Slack (MET) : 0.681ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) +>>>>>>> Stashed changes Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) +<<<<<<< Updated upstream + Data Path Delay: 0.736ns (logic 0.227ns (30.836%) route 0.509ns (69.164%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.263ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns +======= + Data Path Delay: 0.596ns (logic 0.246ns (41.259%) route 0.350ns (58.741%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns +>>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16703,15 +14873,27 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X19Y59 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.228 0.239 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y39 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.293 -0.089 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X93Y122 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16722,31 +14904,32 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y39 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.196 -0.459 + SLICE_X13Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.551 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 + required time 0.551 + arrival time 0.239 ------------------------------------------------------------------- - slack 1.012 + slack 0.790 -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16758,15 +14941,15 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16777,31 +14960,31 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 + required time 0.572 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.290 + slack 0.790 -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16813,15 +14996,15 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16832,31 +15015,31 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 + required time 0.572 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.290 + slack 0.790 -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16868,15 +15051,15 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16887,31 +15070,31 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 + required time 0.572 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.290 + slack 0.790 -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16923,15 +15106,15 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16942,31 +15125,31 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 + required time 0.572 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.290 + slack 0.790 -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16978,15 +15161,15 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16997,348 +15180,18 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 + required time 0.572 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.290 + slack 0.790 -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.356ns (arrival time - required time) +Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR @@ -17346,12 +15199,12 @@ Slack (MET) : 1.356ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17363,15 +15216,15 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17382,18 +15235,18 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 + required time 0.524 + arrival time 0.329 ------------------------------------------------------------------- - slack 1.356 + slack 0.853 -Slack (MET) : 1.356ns (arrival time - required time) +Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR @@ -17401,12 +15254,12 @@ Slack (MET) : 1.356ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17418,15 +15271,15 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17437,18 +15290,18 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 + required time 0.524 + arrival time 0.329 ------------------------------------------------------------------- - slack 1.356 + slack 0.853 -Slack (MET) : 1.356ns (arrival time - required time) +Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR @@ -17456,12 +15309,12 @@ Slack (MET) : 1.356ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17473,15 +15326,15 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17492,18 +15345,18 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 + required time 0.524 + arrival time 0.329 ------------------------------------------------------------------- - slack 1.356 + slack 0.853 -Slack (MET) : 1.356ns (arrival time - required time) +Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR @@ -17511,12 +15364,12 @@ Slack (MET) : 1.356ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17528,15 +15381,15 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17547,18 +15400,18 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 + required time 0.524 + arrival time 0.329 ------------------------------------------------------------------- - slack 1.356 + slack 0.853 -Slack (MET) : 1.356ns (arrival time - required time) +Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR @@ -17566,12 +15419,12 @@ Slack (MET) : 1.356ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17583,15 +15436,15 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17602,18 +15455,1173 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 + required time 0.524 + arrival time 0.329 ------------------------------------------------------------------- - slack 1.356 + slack 0.853 -Slack (MET) : 1.366ns (arrival time - required time) +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.994ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.967ns (logic 0.227ns (23.471%) route 0.740ns (76.529%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.459 0.470 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.196 -0.457 + SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.470 + ------------------------------------------------------------------- + slack 0.994 + +Slack (MET) : 0.994ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR @@ -17621,12 +16629,427 @@ Slack (MET) : 1.366ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.358ns (logic 0.227ns (16.717%) route 1.131ns (83.283%)) + Data Path Delay: 0.967ns (logic 0.227ns (23.471%) route 0.740ns (76.529%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.059ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.459 0.470 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.196 -0.457 + SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.470 + ------------------------------------------------------------------- + slack 0.994 + +Slack (MET) : 0.994ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.967ns (logic 0.227ns (23.471%) route 0.740ns (76.529%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.459 0.470 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.196 -0.457 + SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.470 + ------------------------------------------------------------------- + slack 0.994 + +Slack (MET) : 0.994ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.967ns (logic 0.227ns (23.471%) route 0.740ns (76.529%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.459 0.470 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C + clock pessimism -0.196 -0.457 + SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.470 + ------------------------------------------------------------------- + slack 0.994 + +Slack (MET) : 1.109ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.559 + ------------------------------------------------------------------- + slack 1.109 + +Slack (MET) : 1.109ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.559 + ------------------------------------------------------------------- + slack 1.109 + +Slack (MET) : 1.109ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.559 + ------------------------------------------------------------------- + slack 1.109 + +Slack (MET) : 1.109ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.559 + ------------------------------------------------------------------- + slack 1.109 + +Slack (MET) : 1.109ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y122 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.209 -0.678 + SLICE_X93Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.770 + arrival time -0.089 + ------------------------------------------------------------------- + slack 0.681 + +Slack (MET) : 0.692ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17639,14 +17062,14 @@ Slack (MET) : 1.366ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.924 0.783 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X6Y74 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17658,30 +17081,965 @@ Slack (MET) : 1.366ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.984 -0.324 u_Axi_CDC/rFifo/cpu_clk - SLICE_X6Y74 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.516 - SLICE_X6Y74 FDCE (Remov_fdce_C_CLR) -0.067 -0.583 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk + SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.189 -0.656 + SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- - required time 0.583 - arrival time 0.783 + required time 0.723 + arrival time -0.031 ------------------------------------------------------------------- - slack 1.366 + slack 0.692 -Slack (MET) : 1.381ns (arrival time - required time) +Slack (MET) : 0.692ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk + SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.189 -0.656 + SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.723 + arrival time -0.031 + ------------------------------------------------------------------- + slack 0.692 + +Slack (MET) : 0.692ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk + SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.189 -0.656 + SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.723 + arrival time -0.031 + ------------------------------------------------------------------- + slack 0.692 + +Slack (MET) : 0.692ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk + SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.189 -0.656 + SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.723 + arrival time -0.031 + ------------------------------------------------------------------- + slack 0.692 + +Slack (MET) : 0.750ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/bFifo/cpu_clk + SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.209 -0.678 + SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 0.770 + arrival time -0.020 + ------------------------------------------------------------------- + slack 0.750 + +Slack (MET) : 0.750ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/bFifo/cpu_clk + SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.209 -0.678 + SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.770 + arrival time -0.020 + ------------------------------------------------------------------- + slack 0.750 + +Slack (MET) : 0.750ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.007ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/bFifo/cpu_clk + SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.209 -0.678 + SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.770 + arrival time -0.020 + ------------------------------------------------------------------- + slack 0.750 + +Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.764ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in + SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.209 -0.670 + SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] + ------------------------------------------------------------------- + required time 0.762 + arrival time 0.002 + ------------------------------------------------------------------- + slack 0.764 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.803ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.209 -0.677 + SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.769 + arrival time 0.034 + ------------------------------------------------------------------- + slack 0.803 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17694,14 +18052,14 @@ Slack (MET) : 1.381ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17713,30 +18071,30 @@ Slack (MET) : 1.381ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.037 -0.310 - SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 0.402 - arrival time 0.978 + required time 0.734 + arrival time 0.074 ------------------------------------------------------------------- - slack 1.381 + slack 0.808 -Slack (MET) : 1.381ns (arrival time - required time) +Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17749,14 +18107,14 @@ Slack (MET) : 1.381ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17768,30 +18126,30 @@ Slack (MET) : 1.381ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.037 -0.310 - SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- - required time 0.402 - arrival time 0.978 + required time 0.734 + arrival time 0.074 ------------------------------------------------------------------- - slack 1.381 + slack 0.808 -Slack (MET) : 1.381ns (arrival time - required time) +Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17804,14 +18162,14 @@ Slack (MET) : 1.381ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17823,789 +18181,2243 @@ Slack (MET) : 1.381ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.037 -0.310 - SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- - required time 0.402 - arrival time 0.978 + required time 0.734 + arrival time 0.074 ------------------------------------------------------------------- - slack 1.381 + slack 0.808 -Slack (MET) : 1.381ns (arrival time - required time) +Slack (MET) : 0.808ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.074 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.074 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.209 -0.667 + SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.074 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.967ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.022ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.474ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.189 -0.663 + SLICE_X90Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.730 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.730 + arrival time 0.237 + ------------------------------------------------------------------- + slack 0.967 + +Slack (MET) : 0.967ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.022ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.474ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.189 -0.663 + SLICE_X90Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.730 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.730 + arrival time 0.237 + ------------------------------------------------------------------- + slack 0.967 + +Slack (MET) : 0.967ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.022ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.474ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.189 -0.663 + SLICE_X90Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.730 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.730 + arrival time 0.237 + ------------------------------------------------------------------- + slack 0.967 + +Slack (MET) : 0.967ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.022ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.474ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.189 -0.663 + SLICE_X90Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.730 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.730 + arrival time 0.237 + ------------------------------------------------------------------- + slack 0.967 + +Slack (MET) : 0.967ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.022ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.474ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.189 -0.663 + SLICE_X90Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.730 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.730 + arrival time 0.237 + ------------------------------------------------------------------- + slack 0.967 + +Slack (MET) : 0.967ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.022ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.474ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X90Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.189 -0.663 + SLICE_X90Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.730 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.730 + arrival time 0.237 + ------------------------------------------------------------------- + slack 0.967 + +Slack (MET) : 0.992ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.022ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.474ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X91Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.189 -0.663 + SLICE_X91Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.755 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.755 + arrival time 0.237 + ------------------------------------------------------------------- + slack 0.992 + +Slack (MET) : 0.992ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.922ns (logic 0.209ns (22.677%) route 0.713ns (77.323%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.022ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.474ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.512 0.237 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X91Y126 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.189 -0.663 + SLICE_X91Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.755 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.755 + arrival time 0.237 + ------------------------------------------------------------------- + slack 0.992 + +Slack (MET) : 1.006ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.940ns (logic 0.209ns (22.242%) route 0.731ns (77.758%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.470ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.530 0.255 u_Axi_CDC/arFifo/p_0_in + SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.189 -0.659 + SLICE_X86Y105 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] + ------------------------------------------------------------------- + required time 0.751 + arrival time 0.255 + ------------------------------------------------------------------- + slack 1.006 + +Slack (MET) : 1.006ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.940ns (logic 0.209ns (22.242%) route 0.731ns (77.758%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.470ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.530 0.255 u_Axi_CDC/arFifo/p_0_in + SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.189 -0.659 + SLICE_X86Y105 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] + ------------------------------------------------------------------- + required time 0.751 + arrival time 0.255 + ------------------------------------------------------------------- + slack 1.006 + +Slack (MET) : 1.006ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.940ns (logic 0.209ns (22.242%) route 0.731ns (77.758%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.470ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.530 0.255 u_Axi_CDC/arFifo/p_0_in + SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.189 -0.659 + SLICE_X86Y105 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] + ------------------------------------------------------------------- + required time 0.751 + arrival time 0.255 + ------------------------------------------------------------------- + slack 1.006 + +Slack (MET) : 1.006ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.940ns (logic 0.209ns (22.242%) route 0.731ns (77.758%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.470ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.530 0.255 u_Axi_CDC/arFifo/p_0_in + SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.189 -0.659 + SLICE_X86Y105 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] + ------------------------------------------------------------------- + required time 0.751 + arrival time 0.255 + ------------------------------------------------------------------- + slack 1.006 + +Slack (MET) : 1.006ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.940ns (logic 0.209ns (22.242%) route 0.731ns (77.758%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.470ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.530 0.255 u_Axi_CDC/arFifo/p_0_in + SLICE_X86Y105 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.189 -0.659 + SLICE_X86Y105 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] + ------------------------------------------------------------------- + required time 0.751 + arrival time 0.255 + ------------------------------------------------------------------- + slack 1.006 + +Slack (MET) : 1.031ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.957ns (logic 0.209ns (21.829%) route 0.748ns (78.171%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.478ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.548 0.272 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.830 -0.478 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.189 -0.667 + SLICE_X89Y125 FDCE (Remov_fdce_C_CLR) -0.092 -0.759 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] + ------------------------------------------------------------------- + required time 0.759 + arrival time 0.272 + ------------------------------------------------------------------- + slack 1.031 + +Slack (MET) : 1.031ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.957ns (logic 0.209ns (21.829%) route 0.748ns (78.171%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.478ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.548 0.272 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.830 -0.478 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.189 -0.667 + SLICE_X89Y125 FDCE (Remov_fdce_C_CLR) -0.092 -0.759 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] + ------------------------------------------------------------------- + required time 0.759 + arrival time 0.272 + ------------------------------------------------------------------- + slack 1.031 + +Slack (MET) : 1.031ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.957ns (logic 0.209ns (21.829%) route 0.748ns (78.171%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.478ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.548 0.272 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.830 -0.478 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + clock pessimism -0.189 -0.667 + SLICE_X89Y125 FDCE (Remov_fdce_C_CLR) -0.092 -0.759 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] + ------------------------------------------------------------------- + required time 0.759 + arrival time 0.272 + ------------------------------------------------------------------- + slack 1.031 + +Slack (MET) : 1.031ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.957ns (logic 0.209ns (21.829%) route 0.748ns (78.171%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.478ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.548 0.272 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.830 -0.478 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.189 -0.667 + SLICE_X89Y125 FDCE (Remov_fdce_C_CLR) -0.092 -0.759 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] + ------------------------------------------------------------------- + required time 0.759 + arrival time 0.272 + ------------------------------------------------------------------- + slack 1.031 + +Slack (MET) : 1.031ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.957ns (logic 0.209ns (21.829%) route 0.748ns (78.171%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.478ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.548 0.272 u_Axi_CDC/wFifo/p_0_in + SLICE_X89Y125 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.830 -0.478 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.189 -0.667 + SLICE_X89Y125 FDCE (Remov_fdce_C_CLR) -0.092 -0.759 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] + ------------------------------------------------------------------- + required time 0.759 + arrival time 0.272 + ------------------------------------------------------------------- + slack 1.031 + +Slack (MET) : 1.060ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.994ns (logic 0.209ns (21.025%) route 0.785ns (78.975%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.470ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.585 0.309 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.189 -0.659 + SLICE_X86Y104 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.751 + arrival time 0.309 + ------------------------------------------------------------------- + slack 1.060 + +Slack (MET) : 1.060ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.994ns (logic 0.209ns (21.025%) route 0.785ns (78.975%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.470ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.585 0.309 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.189 -0.659 + SLICE_X86Y104 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.751 + arrival time 0.309 + ------------------------------------------------------------------- + slack 1.060 + +Slack (MET) : 1.060ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.994ns (logic 0.209ns (21.025%) route 0.785ns (78.975%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.470ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.585 0.309 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.189 -0.659 + SLICE_X86Y104 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.751 + arrival time 0.309 + ------------------------------------------------------------------- + slack 1.060 + +Slack (MET) : 1.060ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.994ns (logic 0.209ns (21.025%) route 0.785ns (78.975%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.470ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.585 0.309 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.189 -0.659 + SLICE_X86Y104 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.751 + arrival time 0.309 + ------------------------------------------------------------------- + slack 1.060 + +Slack (MET) : 1.060ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.994ns (logic 0.209ns (21.025%) route 0.785ns (78.975%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.470ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.585 0.309 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.189 -0.659 + SLICE_X86Y104 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.751 + arrival time 0.309 + ------------------------------------------------------------------- + slack 1.060 + +Slack (MET) : 1.060ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.994ns (logic 0.209ns (21.025%) route 0.785ns (78.975%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.470ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk + SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.585 0.309 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.838 -0.470 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.189 -0.659 + SLICE_X86Y104 FDCE (Remov_fdce_C_CLR) -0.092 -0.751 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.751 + arrival time 0.309 + ------------------------------------------------------------------- + slack 1.060 + +Slack (MET) : 1.090ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.294ns (logic 0.246ns (19.011%) route 1.048ns (80.989%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.271ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.454ns + Source Clock Delay (SCD): -0.685ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O + net (fo=30, routed) 0.991 0.609 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.854 -0.454 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C + clock pessimism 0.040 -0.414 + SLICE_X64Y101 FDCE (Remov_fdce_C_CLR) -0.067 -0.481 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.481 + arrival time 0.609 + ------------------------------------------------------------------- + slack 1.090 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: mlkem_clk + To Clock: mlkem_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : 0 Failing Endpoints, Worst Slack 0.658ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.658ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 0.923ns (logic 0.227ns (24.583%) route 0.696ns (75.417%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.332ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.414 0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X72Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C + clock pessimism 0.040 -0.348 + SLICE_X72Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.415 + arrival time 0.243 + ------------------------------------------------------------------- + slack 0.658 + +Slack (MET) : 0.796ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism 0.040 -0.350 + SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.417 + arrival time 0.379 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.796ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism 0.040 -0.350 + SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.417 + arrival time 0.379 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.796ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism 0.040 -0.350 + SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.417 + arrival time 0.379 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.796ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism 0.040 -0.350 + SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.417 + arrival time 0.379 + ------------------------------------------------------------------- + slack 0.796 + +Slack (MET) : 0.807ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C + clock pessimism 0.040 -0.351 + SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.418 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.807 + +Slack (MET) : 0.807ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.559 + ------------------------------------------------------------------- + slack 1.109 + +Slack (MET) : 1.109ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C + clock pessimism 0.040 -0.351 + SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.418 + arrival time 0.389 + ------------------------------------------------------------------- + slack 0.807 + +Slack (MET) : 0.807ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism 0.037 -0.310 - SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- - required time 0.402 - arrival time 0.978 + required time 0.550 + arrival time 0.559 ------------------------------------------------------------------- - slack 1.381 + slack 1.109 - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: mlkem_clk_clk_pll - To Clock: mlkem_clk_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.613ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.109ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + (clock cpu_clk rise edge) 0.000 0.000 r +======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism 0.040 -0.351 + SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 + required time 0.418 + arrival time 0.389 ------------------------------------------------------------------- - slack 0.613 + slack 0.807 -Slack (MET) : 0.613ns (arrival time - required time) +Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r +>>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r +======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r +>>>>>>> Stashed changes K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.559 + ------------------------------------------------------------------- + slack 1.109 +======= PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism 0.040 -0.351 + SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 + required time 0.418 + arrival time 0.389 ------------------------------------------------------------------- - slack 0.629 + slack 0.807 -Slack (MET) : 0.629ns (arrival time - required time) +Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/C - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/C - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/C - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -18615,17 +20427,17 @@ Slack (MET) : 0.741ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -18635,34 +20447,34 @@ Slack (MET) : 0.741ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/C + clock pessimism 0.040 -0.351 + SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 + required time 0.443 + arrival time 0.389 ------------------------------------------------------------------- - slack 0.741 + slack 0.832 -Slack (MET) : 0.741ns (arrival time - required time) +Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -18672,17 +20484,17 @@ Slack (MET) : 0.741ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -18692,34 +20504,34 @@ Slack (MET) : 0.741ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/C + clock pessimism 0.040 -0.351 + SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 + required time 0.443 + arrival time 0.389 ------------------------------------------------------------------- - slack 0.741 + slack 0.832 -Slack (MET) : 0.741ns (arrival time - required time) +Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -18729,17 +20541,17 @@ Slack (MET) : 0.741ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -18749,34 +20561,34 @@ Slack (MET) : 0.741ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/C + clock pessimism 0.040 -0.351 + SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 + required time 0.443 + arrival time 0.389 ------------------------------------------------------------------- - slack 0.741 + slack 0.832 -Slack (MET) : 0.741ns (arrival time - required time) +Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.329ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.391ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -18786,17 +20598,17 @@ Slack (MET) : 0.741ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] + SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -18806,1402 +20618,34 @@ Slack (MET) : 0.741ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] + net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/C + clock pessimism 0.040 -0.351 + SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 + required time 0.443 + arrival time 0.389 ------------------------------------------------------------------- - slack 0.741 + slack 0.832 -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/C - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/C - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/C - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/C - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X118Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/C - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X118Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/C - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/C - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/C - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/C - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/C - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.824ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/C - clock pessimism -0.192 -0.574 - SLICE_X121Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.824 - -Slack (MET) : 0.827ns (arrival time - required time) +Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20211,17 +20655,17 @@ Slack (MET) : 0.827ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg + SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20231,34 +20675,34 @@ Slack (MET) : 0.827ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1] + net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/C + clock pessimism 0.040 -0.345 + SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 + required time 0.437 + arrival time 0.447 ------------------------------------------------------------------- - slack 0.827 + slack 0.884 -Slack (MET) : 0.827ns (arrival time - required time) +Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20268,17 +20712,17 @@ Slack (MET) : 0.827ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg + SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20288,34 +20732,34 @@ Slack (MET) : 0.827ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2] + net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/C + clock pessimism 0.040 -0.345 + SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 + required time 0.437 + arrival time 0.447 ------------------------------------------------------------------- - slack 0.827 + slack 0.884 -Slack (MET) : 0.827ns (arrival time - required time) +Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20325,17 +20769,17 @@ Slack (MET) : 0.827ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg + SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20345,34 +20789,34 @@ Slack (MET) : 0.827ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] + net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/C + clock pessimism 0.040 -0.345 + SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 + required time 0.437 + arrival time 0.447 ------------------------------------------------------------------- - slack 0.827 + slack 0.884 -Slack (MET) : 0.827ns (arrival time - required time) +Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20382,17 +20826,17 @@ Slack (MET) : 0.827ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk + SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 + SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O + net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg + SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20402,34 +20846,34 @@ Slack (MET) : 0.827ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] + net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/C + clock pessimism 0.040 -0.345 + SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 + required time 0.437 + arrival time 0.447 ------------------------------------------------------------------- - slack 0.827 + slack 0.884 -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.906ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.080ns (logic 0.226ns (20.934%) route 0.854ns (79.066%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20439,17 +20883,17 @@ Slack (MET) : 0.827ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.683 0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20459,34 +20903,34 @@ Slack (MET) : 0.827ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] + net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X93Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/C + clock pessimism 0.040 -0.347 + SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15] ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 + required time 0.506 + arrival time 0.400 ------------------------------------------------------------------- - slack 0.827 + slack 0.906 -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.906ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.080ns (logic 0.226ns (20.934%) route 0.854ns (79.066%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20496,17 +20940,17 @@ Slack (MET) : 0.827ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.683 0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20516,34 +20960,34 @@ Slack (MET) : 0.827ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] + net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X93Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/C + clock pessimism 0.040 -0.347 + SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53] ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 + required time 0.506 + arrival time 0.400 ------------------------------------------------------------------- - slack 0.827 + slack 0.906 -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.927ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20553,17 +20997,17 @@ Slack (MET) : 0.860ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20573,34 +21017,34 @@ Slack (MET) : 0.860ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X118Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/C - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0] + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X100Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/C + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16] ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 + required time 0.475 + arrival time 0.452 ------------------------------------------------------------------- - slack 0.860 + slack 0.927 -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.927ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20610,17 +21054,17 @@ Slack (MET) : 0.860ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20630,34 +21074,34 @@ Slack (MET) : 0.860ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X118Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/C - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X100Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17]/C + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[17] ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 + required time 0.475 + arrival time 0.452 ------------------------------------------------------------------- - slack 0.860 + slack 0.927 -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.927ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20667,17 +21111,17 @@ Slack (MET) : 0.868ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20687,34 +21131,34 @@ Slack (MET) : 0.868ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X122Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/C - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0] + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X100Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18]/C + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[18] ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 + required time 0.475 + arrival time 0.452 ------------------------------------------------------------------- - slack 0.868 + slack 0.927 -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.927ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20724,17 +21168,17 @@ Slack (MET) : 0.868ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20744,73 +21188,54 @@ Slack (MET) : 0.868ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X122Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/C - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1] + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X100Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19]/C + clock pessimism 0.040 -0.341 + SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[19] ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 + required time 0.475 + arrival time 0.452 ------------------------------------------------------------------- - slack 0.868 + slack 0.927 - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: sys_clk - To Clock: mlkem_clk_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 2.861ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 2.861ns (arrival time - required time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.931ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 3.250ns (logic 0.187ns (5.753%) route 3.063ns (94.247%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.351ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.605ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 1.463 2.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in - SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20820,58 +21245,54 @@ Slack (MET) : 2.861ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y79 FDCE (Remov_fdce_C_CLR) -0.158 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg + net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0]/C + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s3_reg[0] ------------------------------------------------------------------- - required time 0.216 - arrival time 2.645 + required time 0.473 + arrival time 0.458 ------------------------------------------------------------------- - slack 2.861 + slack 0.931 -Slack (MET) : 2.861ns (arrival time - required time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.931ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 3.250ns (logic 0.187ns (5.753%) route 3.063ns (94.247%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.351ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.605ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 1.463 2.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in - SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20881,58 +21302,966 @@ Slack (MET) : 2.861ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y79 FDCE (Remov_fdce_C_CLR) -0.158 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg + net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16]/C + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[16] ------------------------------------------------------------------- - required time 0.216 - arrival time 2.645 + required time 0.473 + arrival time 0.458 ------------------------------------------------------------------- - slack 2.861 + slack 0.931 -Slack (MET) : 4.207ns (arrival time - required time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.931ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 4.569ns (logic 0.187ns (4.093%) route 4.382ns (95.907%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.324ns (DCD - SCD - CPR) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17]/C + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[17] + ------------------------------------------------------------------- + required time 0.473 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.931 + +Slack (MET) : 0.931ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18]/C + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[18] + ------------------------------------------------------------------- + required time 0.473 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.931 + +Slack (MET) : 0.931ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19]/C + clock pessimism 0.040 -0.339 + SLICE_X102Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[19] + ------------------------------------------------------------------- + required time 0.473 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.931 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X100Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12]/C + clock pessimism 0.040 -0.341 + SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[12] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.460 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X100Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13]/C + clock pessimism 0.040 -0.341 + SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[13] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.460 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X100Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14]/C + clock pessimism 0.040 -0.341 + SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[14] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.460 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.140ns (logic 0.226ns (19.822%) route 0.914ns (80.178%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.339ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.744 0.460 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X100Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X100Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15]/C + clock pessimism 0.040 -0.341 + SLICE_X100Y97 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[15] + ------------------------------------------------------------------- + required time 0.475 + arrival time 0.460 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.936ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.113ns (logic 0.226ns (20.298%) route 0.887ns (79.702%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.384ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.717 0.433 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X99Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X99Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep/C + clock pessimism 0.040 -0.344 + SLICE_X99Y96 FDCE (Remov_fdce_C_CLR) -0.159 -0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep + ------------------------------------------------------------------- + required time 0.503 + arrival time 0.433 + ------------------------------------------------------------------- + slack 0.936 + +Slack (MET) : 0.936ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.113ns (logic 0.226ns (20.298%) route 0.887ns (79.702%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.384ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.717 0.433 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X99Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X99Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2/C + clock pessimism 0.040 -0.344 + SLICE_X99Y96 FDCE (Remov_fdce_C_CLR) -0.159 -0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_ph_reg[0]_rep__2 + ------------------------------------------------------------------- + required time 0.503 + arrival time 0.433 + ------------------------------------------------------------------- + slack 0.936 + +Slack (MET) : 0.939ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.140ns (logic 0.226ns (19.816%) route 0.914ns (80.184%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.744 0.461 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/delay_reg[1] + SLICE_X98Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk + SLICE_X98Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55]/C + clock pessimism 0.040 -0.345 + SLICE_X98Y91 FDCE (Remov_fdce_C_CLR) -0.134 -0.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[55] + ------------------------------------------------------------------- + required time 0.479 + arrival time 0.461 + ------------------------------------------------------------------- + slack 0.939 + +Slack (MET) : 0.942ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.141ns (logic 0.226ns (19.800%) route 0.915ns (80.200%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.745 0.461 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X92Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X92Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54]/C + clock pessimism 0.040 -0.347 + SLICE_X92Y90 FDCE (Remov_fdce_C_CLR) -0.134 -0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[54] + ------------------------------------------------------------------- + required time 0.481 + arrival time 0.461 + ------------------------------------------------------------------- + slack 0.942 + +Slack (MET) : 0.952ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.148ns (logic 0.226ns (19.693%) route 0.922ns (80.307%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.751 0.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X90Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X90Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25]/C + clock pessimism 0.040 -0.350 + SLICE_X90Y91 FDCE (Remov_fdce_C_CLR) -0.134 -0.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[25] + ------------------------------------------------------------------- + required time 0.484 + arrival time 0.468 + ------------------------------------------------------------------- + slack 0.952 + +Slack (MET) : 0.952ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.148ns (logic 0.226ns (19.693%) route 0.922ns (80.307%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.330ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.390ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.751 0.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X90Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X90Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56]/C + clock pessimism 0.040 -0.350 + SLICE_X90Y91 FDCE (Remov_fdce_C_CLR) -0.134 -0.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[56] + ------------------------------------------------------------------- + required time 0.484 + arrival time 0.468 + ------------------------------------------------------------------- + slack 0.952 + +Slack (MET) : 0.956ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X103Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X103Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12]/C + clock pessimism 0.040 -0.339 + SLICE_X103Y98 FDCE (Remov_fdce_C_CLR) -0.159 -0.498 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[12] + ------------------------------------------------------------------- + required time 0.498 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.956 + +Slack (MET) : 0.956ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X103Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X103Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13]/C + clock pessimism 0.040 -0.339 + SLICE_X103Y98 FDCE (Remov_fdce_C_CLR) -0.159 -0.498 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[13] + ------------------------------------------------------------------- + required time 0.498 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.956 + +Slack (MET) : 0.956ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.138ns (logic 0.226ns (19.862%) route 0.912ns (80.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.341ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.741 0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X103Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X103Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19]/C + clock pessimism 0.040 -0.339 + SLICE_X103Y98 FDCE (Remov_fdce_C_CLR) -0.159 -0.498 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[19] + ------------------------------------------------------------------- + required time 0.498 + arrival time 0.458 + ------------------------------------------------------------------- + slack 0.956 + +Slack (MET) : 0.964ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[4]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns - Source Clock Delay (SCD): -0.605ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 2.782 3.964 pll_clk.u_rst_mlkem/p_0_in - SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[4]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -20942,58 +22271,54 @@ Slack (MET) : 4.207ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.928 -0.380 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C - clock pessimism 0.099 -0.281 - clock uncertainty 0.197 -0.085 - SLICE_X118Y67 FDCE (Remov_fdce_C_CLR) -0.158 -0.243 pll_clk.u_rst_mlkem/delay_reg[0] + net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[4]/C + clock pessimism 0.040 -0.340 + SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[4] ------------------------------------------------------------------- - required time 0.243 - arrival time 3.964 + required time 0.474 + arrival time 0.490 ------------------------------------------------------------------- - slack 4.207 + slack 0.964 -Slack (MET) : 4.207ns (arrival time - required time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.964ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[5]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 4.569ns (logic 0.187ns (4.093%) route 4.382ns (95.907%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.324ns (DCD - SCD - CPR) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.340ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns - Source Clock Delay (SCD): -0.605ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 2.782 3.964 pll_clk.u_rst_mlkem/p_0_in - SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[5]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -21003,55 +22328,34 @@ Slack (MET) : 4.207ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.928 -0.380 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - clock pessimism 0.099 -0.281 - clock uncertainty 0.197 -0.085 - SLICE_X118Y67 FDCE (Remov_fdce_C_CLR) -0.158 -0.243 pll_clk.u_rst_mlkem/delay_reg[1] + net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[5]/C + clock pessimism 0.040 -0.340 + SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[5] ------------------------------------------------------------------- - required time 0.243 - arrival time 3.964 + required time 0.474 + arrival time 0.490 ------------------------------------------------------------------- - slack 4.207 + slack 0.964 - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: mlkem_clk_clk_pll - To Clock: sys_clk - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 2.991ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 2.991ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.964ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[6]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.460ns (logic 0.186ns (5.375%) route 3.274ns (94.625%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.365ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.340ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.380ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -21061,58 +22365,54 @@ Slack (MET) : 2.991ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 2.977 2.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[6]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - clock pessimism 0.099 -0.242 - clock uncertainty 0.197 -0.046 - SLICE_X13Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[6]/C + clock pessimism 0.040 -0.340 + SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[6] ------------------------------------------------------------------- - required time 0.138 - arrival time 2.853 + required time 0.474 + arrival time 0.490 ------------------------------------------------------------------- - slack 2.991 + slack 0.964 -Slack (MET) : 2.991ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.964ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[7]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.460ns (logic 0.186ns (5.375%) route 3.274ns (94.625%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.365ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.340ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.380ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) + (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -21122,35 +22422,321 @@ Slack (MET) : 2.991ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 2.977 2.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[7]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - clock pessimism 0.099 -0.242 - clock uncertainty 0.197 -0.046 - SLICE_X13Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[7]/C + clock pessimism 0.040 -0.340 + SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_est_s4_reg[7] ------------------------------------------------------------------- - required time 0.138 - arrival time 2.853 + required time 0.474 + arrival time 0.490 ------------------------------------------------------------------- - slack 2.991 + slack 0.964 + +Slack (MET) : 0.964ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[10]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.340ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.380ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[10]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[10]/C + clock pessimism 0.040 -0.340 + SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[10] + ------------------------------------------------------------------- + required time 0.474 + arrival time 0.490 + ------------------------------------------------------------------- + slack 0.964 + +Slack (MET) : 0.964ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[11]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.340ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.380ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[11]/C + clock pessimism 0.040 -0.340 + SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[11] + ------------------------------------------------------------------- + required time 0.474 + arrival time 0.490 + ------------------------------------------------------------------- + slack 0.964 + +Slack (MET) : 0.964ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[8]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.340ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.380ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[8]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[8]/C + clock pessimism 0.040 -0.340 + SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[8] + ------------------------------------------------------------------- + required time 0.474 + arrival time 0.490 + ------------------------------------------------------------------- + slack 0.964 + +Slack (MET) : 0.964ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[9]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.170ns (logic 0.226ns (19.314%) route 0.944ns (80.686%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.340ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.380ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.774 0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 + SLICE_X102Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk + SLICE_X102Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[9]/C + clock pessimism 0.040 -0.340 + SLICE_X102Y96 FDCE (Remov_fdce_C_CLR) -0.134 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_rem_s5_reg[9] + ------------------------------------------------------------------- + required time 0.474 + arrival time 0.490 + ------------------------------------------------------------------- + slack 0.964 + +Slack (MET) : 0.964ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[58]/CLR + (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) + Data Path Delay: 1.140ns (logic 0.226ns (19.816%) route 0.914ns (80.184%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.680ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] + SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O + net (fo=15647, routed) 0.744 0.461 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 + SLICE_X99Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[58]/CLR + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk + SLICE_X99Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[58]/C + clock pessimism 0.040 -0.345 + SLICE_X99Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.504 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sigma_r_reg[58] + ------------------------------------------------------------------- + required time 0.504 + arrival time 0.461 + ------------------------------------------------------------------- + slack 0.964 +>>>>>>> Stashed changes @@ -21162,851 +22748,46 @@ From Clock: sys_clk To Clock: sys_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.479ns, Total Violation 0.000ns +<<<<<<< Updated upstream +Hold : 0 Failing Endpoints, Worst Slack 0.761ns, Total Violation 0.000ns +======= +Hold : 0 Failing Endpoints, Worst Slack 0.573ns, Total Violation 0.000ns +>>>>>>> Stashed changes --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.524ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.468ns (logic 0.227ns (48.556%) route 0.241ns (51.444%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.187 -0.103 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X17Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C - clock pessimism -0.192 -0.534 - SLICE_X17Y86 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3] - ------------------------------------------------------------------- - required time 0.626 - arrival time -0.103 - ------------------------------------------------------------------- - slack 0.524 - -Slack (MET) : 0.548ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.227ns (48.316%) route 0.243ns (51.684%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.189 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X15Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X15Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.214 -0.556 - SLICE_X15Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.648 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.648 - arrival time -0.101 - ------------------------------------------------------------------- - slack 0.548 - -Slack (MET) : 0.558ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.214 -0.553 - SLICE_X14Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.620 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.620 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.558 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.650ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.622ns (logic 0.227ns (36.501%) route 0.395ns (63.499%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.341 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X16Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X16Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/C - clock pessimism -0.192 -0.531 - SLICE_X16Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 0.598 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.650 - -Slack (MET) : 0.800ns (arrival time - required time) +<<<<<<< Updated upstream +Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR +======= +Slack (MET) : 0.573ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR +>>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) +<<<<<<< Updated upstream + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns +======= + Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.019ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns +>>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22019,14 +22800,25 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22038,30 +22830,56 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] +<<<<<<< Updated upstream + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time 0.525 + arrival time 0.236 ------------------------------------------------------------------- - slack 0.800 + slack 0.761 -Slack (MET) : 0.800ns (arrival time - required time) +Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR +======= + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.213 -0.600 + SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.667 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.573 + +Slack (MET) : 0.573ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR +>>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) +<<<<<<< Updated upstream + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns +======= + Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.019ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns +>>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22074,14 +22892,25 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22093,30 +22922,56 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] +<<<<<<< Updated upstream + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time 0.525 + arrival time 0.236 ------------------------------------------------------------------- - slack 0.800 + slack 0.761 -Slack (MET) : 0.800ns (arrival time - required time) +Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR +======= + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.213 -0.600 + SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.667 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.573 + +Slack (MET) : 0.573ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR +>>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) +<<<<<<< Updated upstream + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns +======= + Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.019ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns +>>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22129,14 +22984,25 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22148,30 +23014,56 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] +<<<<<<< Updated upstream + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time 0.525 + arrival time 0.236 ------------------------------------------------------------------- - slack 0.800 + slack 0.761 -Slack (MET) : 0.800ns (arrival time - required time) +Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR +======= + net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.213 -0.600 + SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.667 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.573 + +Slack (MET) : 0.837ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR +>>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) +<<<<<<< Updated upstream + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns +======= + Data Path Delay: 0.812ns (logic 0.227ns (27.961%) route 0.585ns (72.039%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.385ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.192ns +>>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22184,14 +23076,25 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.445 0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X64Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22203,17 +23106,348 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] +<<<<<<< Updated upstream + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time 0.525 + arrival time 0.236 ------------------------------------------------------------------- - slack 0.800 + slack 0.761 -Slack (MET) : 0.805ns (arrival time - required time) +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR @@ -22221,12 +23455,12 @@ Slack (MET) : 0.805ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22239,14 +23473,14 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22258,17 +23492,17 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.550 + arrival time 0.310 ------------------------------------------------------------------- - slack 0.805 + slack 0.860 -Slack (MET) : 0.805ns (arrival time - required time) +Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR @@ -22276,12 +23510,12 @@ Slack (MET) : 0.805ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22294,14 +23528,14 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22313,127 +23547,17 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.550 + arrival time 0.310 ------------------------------------------------------------------- - slack 0.805 + slack 0.860 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) +Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR @@ -22441,12 +23565,12 @@ Slack (MET) : 0.805ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22459,14 +23583,14 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22478,17 +23602,17 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.550 + arrival time 0.310 ------------------------------------------------------------------- - slack 0.805 + slack 0.860 -Slack (MET) : 0.805ns (arrival time - required time) +Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR @@ -22496,12 +23620,12 @@ Slack (MET) : 0.805ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22514,14 +23638,14 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22533,17 +23657,89 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.550 + arrival time 0.310 ------------------------------------------------------------------- - slack 0.805 + slack 0.860 -Slack (MET) : 0.805ns (arrival time - required time) +Slack (MET) : 0.871ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR +======= + net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X64Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.192 -0.577 + SLICE_X64Y95 FDCE (Remov_fdce_C_CLR) -0.067 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.644 + arrival time 0.192 + ------------------------------------------------------------------- + slack 0.837 + +Slack (MET) : 0.871ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR +>>>>>>> Stashed changes + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.218 -0.480 + SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.299 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.871ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR @@ -22551,12 +23747,12 @@ Slack (MET) : 0.805ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) + Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22569,14 +23765,14 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22588,17 +23784,1158 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.218 -0.480 + SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.572 + arrival time 0.299 ------------------------------------------------------------------- - slack 0.805 + slack 0.871 -Slack (MET) : 0.805ns (arrival time - required time) +Slack (MET) : 0.872ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.218 -0.479 + SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.301 + ------------------------------------------------------------------- + slack 0.872 + +Slack (MET) : 0.872ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.218 -0.479 + SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.301 + ------------------------------------------------------------------- + slack 0.872 + +Slack (MET) : 0.872ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.218 -0.479 + SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.301 + ------------------------------------------------------------------- + slack 0.872 + +Slack (MET) : 0.890ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.864ns (logic 0.186ns (21.517%) route 0.678ns (78.483%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.380ns + Source Clock Delay (SCD): -0.613ns +======= + Data Path Delay: 0.822ns (logic 0.227ns (27.605%) route 0.595ns (72.395%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.043ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.384ns + Source Clock Delay (SCD): -0.619ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.372 0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.456 0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X65Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/C + clock pessimism -0.192 -0.572 + SLICE_X112Y66 FDCE (Remov_fdce_C_CLR) -0.067 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0] + ------------------------------------------------------------------- + required time 0.639 + arrival time 0.251 + ------------------------------------------------------------------- + slack 0.890 + +Slack (MET) : 0.914ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C +======= + net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X65Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.192 -0.576 + SLICE_X65Y99 FDCE (Remov_fdce_C_CLR) -0.092 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.203 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.871ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.786ns (logic 0.249ns (31.687%) route 0.537ns (68.313%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.377ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns +======= + Data Path Delay: 0.822ns (logic 0.227ns (27.605%) route 0.595ns (72.395%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.043ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.384ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.456 0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X65Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X65Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.192 -0.576 + SLICE_X65Y99 FDCE (Remov_fdce_C_CLR) -0.092 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.203 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.912ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.189 -0.666 + SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.912 + +Slack (MET) : 0.912ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.189 -0.666 + SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.912 + +Slack (MET) : 0.912ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.189 -0.666 + SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.912 + +Slack (MET) : 0.912ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + clock pessimism -0.189 -0.666 + SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.912 + +Slack (MET) : 0.919ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.023ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.209 -0.670 + SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.737 + arrival time 0.182 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.919ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.023ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.209 -0.670 + SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.737 + arrival time 0.182 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.919ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.023ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.209 -0.670 + SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.737 + arrival time 0.182 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.919ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.023ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.209 -0.670 + SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.737 + arrival time 0.182 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.758 + arrival time 0.179 + ------------------------------------------------------------------- + slack 0.937 + +Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR @@ -22606,12 +24943,12 @@ Slack (MET) : 0.805ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) + Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.027ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.477ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22624,14 +24961,14 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22643,250 +24980,141 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] + net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.189 -0.666 + SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.758 + arrival time 0.179 ------------------------------------------------------------------- - slack 0.805 + slack 0.937 -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 1.001ns (arrival time - required time) +Slack (MET) : 0.971ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.933ns (logic 0.227ns (24.323%) route 0.706ns (75.677%)) + Data Path Delay: 0.922ns (logic 0.227ns (24.621%) route 0.695ns (75.379%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.556 0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X66Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.213 -0.601 + SLICE_X66Y91 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.303 + ------------------------------------------------------------------- + slack 0.971 + +Slack (MET) : 0.971ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.922ns (logic 0.227ns (24.621%) route 0.695ns (75.379%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.556 0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X66Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/C + clock pessimism -0.213 -0.601 + SLICE_X66Y91 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.303 + ------------------------------------------------------------------- + slack 0.971 + +Slack (MET) : 0.982ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.939ns (logic 0.246ns (26.196%) route 0.693ns (73.804%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.024ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns +>>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22899,14 +25127,25 @@ Slack (MET) : 1.001ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.653 0.363 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X30Y80 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.371 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X125Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR +======= + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.407 0.246 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y112 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22918,30 +25157,218 @@ Slack (MET) : 1.001ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X30Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.546 - SLICE_X30Y80 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0] +<<<<<<< Updated upstream + net (fo=35652, routed) 0.931 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X125Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/C + clock pessimism -0.192 -0.569 + SLICE_X125Y65 FDCE (Remov_fdce_C_CLR) -0.165 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253] ------------------------------------------------------------------- - required time 0.638 - arrival time 0.363 + required time 0.734 + arrival time 0.179 ------------------------------------------------------------------- - slack 1.001 + slack 0.914 -Slack (MET) : 1.001ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.918ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR + Destination: u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.933ns (logic 0.227ns (24.323%) route 0.706ns (75.677%)) + Data Path Delay: 1.021ns (logic 0.246ns (24.092%) route 0.775ns (75.908%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.489 0.526 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X11Y53 FDCE f u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.972 -0.336 u_Axi_CDC/wFifo/sys_clk + SLICE_X11Y53 FDCE r u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/C + clock pessimism 0.037 -0.299 + SLICE_X11Y53 FDCE (Remov_fdce_C_CLR) -0.092 -0.391 u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.391 + arrival time 0.526 + ------------------------------------------------------------------- + slack 0.918 + +Slack (MET) : 0.928ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y44 FDCE r u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.357 + ------------------------------------------------------------------- + slack 0.928 + +Slack (MET) : 0.928ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y44 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.357 + ------------------------------------------------------------------- + slack 0.928 + +Slack (MET) : 0.928ns (arrival time - required time) +======= + net (fo=9971, routed) 0.848 -0.460 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y112 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.209 -0.669 + SLICE_X92Y112 FDCE (Remov_fdce_C_CLR) -0.067 -0.736 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.736 + arrival time 0.246 + ------------------------------------------------------------------- + slack 0.982 + +Slack (MET) : 0.982ns (arrival time - required time) +>>>>>>> Stashed changes + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns +======= + Data Path Delay: 0.939ns (logic 0.246ns (26.196%) route 0.693ns (73.804%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.024ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns +>>>>>>> Stashed changes Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22954,14 +25381,25 @@ Slack (MET) : 1.001ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.653 0.363 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X30Y80 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR +======= + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.407 0.246 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X92Y112 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22973,85 +25411,48 @@ Slack (MET) : 1.001ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X30Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.192 -0.546 - SLICE_X30Y80 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2] +<<<<<<< Updated upstream + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y44 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- - required time 0.638 - arrival time 0.363 + required time 0.571 + arrival time 0.357 ------------------------------------------------------------------- - slack 1.001 + slack 0.928 -Slack (MET) : 1.086ns (arrival time - required time) +Slack (MET) : 0.928ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.001ns (logic 0.227ns (22.676%) route 0.774ns (77.324%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.007ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.491 0.460 u_Axi_CDC/awFifo/buffers_1_reg - SLICE_X15Y64 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.966 -0.342 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y64 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.534 - SLICE_X15Y64 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/awFifo/popCC_popPtr_reg[1] + Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR +======= + net (fo=9971, routed) 0.848 -0.460 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y112 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.209 -0.669 + SLICE_X92Y112 FDCE (Remov_fdce_C_CLR) -0.067 -0.736 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- - required time 0.626 - arrival time 0.460 + required time 0.736 + arrival time 0.246 ------------------------------------------------------------------- - slack 1.086 + slack 0.982 -Slack (MET) : 1.139ns (arrival time - required time) +Slack (MET) : 0.987ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR +>>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) +<<<<<<< Updated upstream + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -23064,14 +25465,14 @@ Slack (MET) : 1.139ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23083,29 +25484,36 @@ Slack (MET) : 1.139ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0] + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y44 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 + required time 0.571 + arrival time 0.357 ------------------------------------------------------------------- - slack 1.139 + slack 0.928 -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.932ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) + Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.389ns + Source Clock Delay (SCD): -0.606ns +======= + Data Path Delay: 0.940ns (logic 0.227ns (24.146%) route 0.713ns (75.854%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns + Clock Path Skew: 0.045ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.382ns + Source Clock Delay (SCD): -0.619ns +>>>>>>> Stashed changes Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23119,14 +25527,25 @@ Slack (MET) : 1.139ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X112Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.574 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X54Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23138,524 +25557,54 @@ Slack (MET) : 1.139ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1] +<<<<<<< Updated upstream + net (fo=35652, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X112Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/C + clock pessimism -0.192 -0.581 + SLICE_X112Y75 FDCE (Remov_fdce_C_CLR) -0.140 -0.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10] ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 + required time 0.721 + arrival time 0.210 ------------------------------------------------------------------- - slack 1.139 + slack 0.932 -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0] + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR +======= + net (fo=9971, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.192 -0.574 + SLICE_X54Y89 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 + required time 0.666 + arrival time 0.321 ------------------------------------------------------------------- - slack 1.139 + slack 0.987 -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 - ------------------------------------------------------------------- - slack 1.139 - -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 - ------------------------------------------------------------------- - slack 1.139 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.256ns (arrival time - required time) +Slack (MET) : 0.987ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR +>>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.188ns (logic 0.227ns (19.107%) route 0.961ns (80.893%)) +<<<<<<< Updated upstream + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.024ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.570ns + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns +======= + Data Path Delay: 0.940ns (logic 0.227ns (24.146%) route 0.713ns (75.854%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.045ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.382ns + Source Clock Delay (SCD): -0.619ns +>>>>>>> Stashed changes Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23669,14 +25618,25 @@ Slack (MET) : 1.256ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.908 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y71 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.574 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X54Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23688,29 +25648,43 @@ Slack (MET) : 1.256ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.192 -0.546 - SLICE_X27Y71 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] +<<<<<<< Updated upstream + net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0] ------------------------------------------------------------------- required time 0.638 - arrival time 0.618 + arrival time 0.297 ------------------------------------------------------------------- - slack 1.256 + slack 0.935 -Slack (MET) : 1.256ns (arrival time - required time) +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C +======= + net (fo=9971, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.192 -0.574 + SLICE_X54Y89 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.666 + arrival time 0.321 + ------------------------------------------------------------------- + slack 0.987 + +Slack (MET) : 0.987ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.188ns (logic 0.227ns (19.107%) route 0.961ns (80.893%)) + Data Path Delay: 0.940ns (logic 0.227ns (24.146%) route 0.713ns (75.854%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.024ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.570ns + Clock Path Skew: 0.045ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.382ns + Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23724,14 +25698,14 @@ Slack (MET) : 1.256ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.908 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y71 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.574 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X54Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23743,29 +25717,184 @@ Slack (MET) : 1.256ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.192 -0.546 - SLICE_X27Y71 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] + net (fo=9971, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.192 -0.574 + SLICE_X54Y89 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.666 + arrival time 0.321 + ------------------------------------------------------------------- + slack 0.987 + +Slack (MET) : 0.987ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.940ns (logic 0.227ns (24.146%) route 0.713ns (75.854%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.045ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.382ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.574 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X54Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.192 -0.574 + SLICE_X54Y89 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.666 + arrival time 0.321 + ------------------------------------------------------------------- + slack 0.987 + +Slack (MET) : 0.987ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns +======= + Data Path Delay: 0.940ns (logic 0.227ns (24.146%) route 0.713ns (75.854%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.045ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.382ns + Source Clock Delay (SCD): -0.619ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.574 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X54Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1] ------------------------------------------------------------------- required time 0.638 - arrival time 0.618 + arrival time 0.297 ------------------------------------------------------------------- - slack 1.256 + slack 0.935 -Slack (MET) : 1.359ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popCC_popPtr_reg[0]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR +======= + net (fo=9971, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.192 -0.574 + SLICE_X54Y89 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.666 + arrival time 0.321 + ------------------------------------------------------------------- + slack 0.987 + +Slack (MET) : 0.987ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR +>>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.294ns (logic 0.227ns (17.540%) route 1.067ns (82.460%)) +<<<<<<< Updated upstream + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.002ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.541ns + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns +======= + Data Path Delay: 0.940ns (logic 0.227ns (24.146%) route 0.713ns (75.854%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.045ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.382ns + Source Clock Delay (SCD): -0.619ns +>>>>>>> Stashed changes Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23779,14 +25908,25 @@ Slack (MET) : 1.359ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.785 0.753 u_Axi_CDC/arFifo/buffers_0_reg[2] - SLICE_X12Y69 FDCE f u_Axi_CDC/arFifo/popCC_popPtr_reg[0]/CLR + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.574 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X54Y89 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23798,29 +25938,214 @@ Slack (MET) : 1.359ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk - SLICE_X12Y69 FDCE r u_Axi_CDC/arFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.539 - SLICE_X12Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.606 u_Axi_CDC/arFifo/popCC_popPtr_reg[0] +<<<<<<< Updated upstream + net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2] ------------------------------------------------------------------- - required time 0.606 - arrival time 0.753 + required time 0.638 + arrival time 0.297 ------------------------------------------------------------------- - slack 1.359 + slack 0.935 -Slack (MET) : 1.359ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popCC_popPtr_reg[1]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR +======= + net (fo=9971, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.192 -0.574 + SLICE_X54Y89 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.666 + arrival time 0.321 + ------------------------------------------------------------------- + slack 0.987 + +Slack (MET) : 1.004ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR +>>>>>>> Stashed changes (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.294ns (logic 0.227ns (17.540%) route 1.067ns (82.460%)) +<<<<<<< Updated upstream + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.002ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.541ns + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.192ns +======= + Data Path Delay: 0.955ns (logic 0.227ns (23.771%) route 0.728ns (76.229%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.589 0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] + SLICE_X68Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.638 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.944ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR +======= + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X68Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C + clock pessimism -0.213 -0.601 + SLICE_X68Y92 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.336 + ------------------------------------------------------------------- + slack 1.004 + +Slack (MET) : 1.014ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR +>>>>>>> Stashed changes + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns +======= + Data Path Delay: 0.976ns (logic 0.246ns (25.203%) route 0.730ns (74.797%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR +======= + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.444 0.283 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y127 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X127Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/C + clock pessimism -0.192 -0.570 + SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.208 + ------------------------------------------------------------------- + slack 0.944 + +Slack (MET) : 0.944ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23834,14 +26159,14 @@ Slack (MET) : 1.359ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.785 0.753 u_Axi_CDC/arFifo/buffers_0_reg[2] - SLICE_X12Y69 FDCE f u_Axi_CDC/arFifo/popCC_popPtr_reg[1]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23853,29 +26178,29 @@ Slack (MET) : 1.359ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk - SLICE_X12Y69 FDCE r u_Axi_CDC/arFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.539 - SLICE_X12Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.606 u_Axi_CDC/arFifo/popCC_popPtr_reg[1] + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X127Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/C + clock pessimism -0.192 -0.570 + SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223] ------------------------------------------------------------------- - required time 0.606 - arrival time 0.753 + required time 0.735 + arrival time 0.208 ------------------------------------------------------------------- - slack 1.359 + slack 0.944 -Slack (MET) : 1.359ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popCC_popPtr_reg[2]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.294ns (logic 0.227ns (17.540%) route 1.067ns (82.460%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.002ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23889,14 +26214,14 @@ Slack (MET) : 1.359ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.785 0.753 u_Axi_CDC/arFifo/buffers_0_reg[2] - SLICE_X12Y69 FDCE f u_Axi_CDC/arFifo/popCC_popPtr_reg[2]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23908,15 +26233,1642 @@ Slack (MET) : 1.359ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk - SLICE_X12Y69 FDCE r u_Axi_CDC/arFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.192 -0.539 - SLICE_X12Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.606 u_Axi_CDC/arFifo/popCC_popPtr_reg[2] + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/C + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233] ------------------------------------------------------------------- - required time 0.606 - arrival time 0.753 + required time 0.735 + arrival time 0.213 ------------------------------------------------------------------- - slack 1.359 + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/C + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/C + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/C + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/C + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.952ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.822ns (logic 0.249ns (30.308%) route 0.573ns (69.692%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.035ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.407 0.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X125Y67 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X125Y67 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/C + clock pessimism -0.192 -0.571 + SLICE_X125Y67 FDCE (Remov_fdce_C_CLR) -0.165 -0.736 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37] + ------------------------------------------------------------------- + required time 0.736 + arrival time 0.215 + ------------------------------------------------------------------- + slack 0.952 + +Slack (MET) : 0.955ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR +======= + net (fo=9971, routed) 0.833 -0.475 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y127 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.189 -0.664 + SLICE_X88Y127 FDCE (Remov_fdce_C_CLR) -0.067 -0.731 u_Axi_CDC/wFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.731 + arrival time 0.283 + ------------------------------------------------------------------- + slack 1.014 + +Slack (MET) : 1.014ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR +>>>>>>> Stashed changes + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns +======= + Data Path Delay: 0.976ns (logic 0.246ns (25.203%) route 0.730ns (74.797%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR +======= + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.444 0.283 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y127 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X12Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.196 -0.458 + SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.430 + ------------------------------------------------------------------- + slack 0.955 + +Slack (MET) : 0.955ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR +======= + net (fo=9971, routed) 0.833 -0.475 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y127 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.189 -0.664 + SLICE_X88Y127 FDCE (Remov_fdce_C_CLR) -0.067 -0.731 u_Axi_CDC/wFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 0.731 + arrival time 0.283 + ------------------------------------------------------------------- + slack 1.014 + +Slack (MET) : 1.014ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR +>>>>>>> Stashed changes + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns +======= + Data Path Delay: 0.976ns (logic 0.246ns (25.203%) route 0.730ns (74.797%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR +======= + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.444 0.283 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y127 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X12Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.196 -0.458 + SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.430 + ------------------------------------------------------------------- + slack 0.955 + +Slack (MET) : 0.957ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR +======= + net (fo=9971, routed) 0.833 -0.475 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y127 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.189 -0.664 + SLICE_X88Y127 FDCE (Remov_fdce_C_CLR) -0.067 -0.731 u_Axi_CDC/wFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.731 + arrival time 0.283 + ------------------------------------------------------------------- + slack 1.014 + +Slack (MET) : 1.014ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR +>>>>>>> Stashed changes + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.389ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X113Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/C + clock pessimism -0.192 -0.581 + SLICE_X113Y75 FDCE (Remov_fdce_C_CLR) -0.165 -0.746 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5] + ------------------------------------------------------------------- + required time 0.746 + arrival time 0.210 + ------------------------------------------------------------------- + slack 0.957 + +Slack (MET) : 0.957ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.932 -0.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X131Y64 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/C + clock pessimism -0.192 -0.568 + SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.224 + ------------------------------------------------------------------- + slack 0.957 + +Slack (MET) : 0.957ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.932 -0.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X131Y64 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/C + clock pessimism -0.192 -0.568 + SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.224 + ------------------------------------------------------------------- + slack 0.957 + +Slack (MET) : 0.960ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.192ns +======= + Data Path Delay: 0.976ns (logic 0.246ns (25.203%) route 0.730ns (74.797%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.029ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.189ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X113Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR +======= + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.444 0.283 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X88Y127 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X113Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/C + clock pessimism -0.192 -0.571 + SLICE_X113Y65 FDCE (Remov_fdce_C_CLR) -0.092 -0.663 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2] + ------------------------------------------------------------------- + required time 0.663 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.960 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR +======= + net (fo=9971, routed) 0.833 -0.475 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y127 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/C + clock pessimism -0.189 -0.664 + SLICE_X88Y127 FDCE (Remov_fdce_C_CLR) -0.067 -0.731 u_Axi_CDC/wFifo/popCC_popPtr_reg[3] + ------------------------------------------------------------------- + required time 0.731 + arrival time 0.283 + ------------------------------------------------------------------- + slack 1.014 + +Slack (MET) : 1.025ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR +>>>>>>> Stashed changes + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns +======= + Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/C + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR +======= + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.213 -0.601 + SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.356 + ------------------------------------------------------------------- + slack 1.025 + +Slack (MET) : 1.025ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR +>>>>>>> Stashed changes + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns +======= + Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/C + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR +======= + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.213 -0.601 + SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.356 + ------------------------------------------------------------------- + slack 1.025 + +Slack (MET) : 1.025ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR +>>>>>>> Stashed changes + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns +======= + Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/C + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR +======= + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.213 -0.601 + SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.356 + ------------------------------------------------------------------- + slack 1.025 + +Slack (MET) : 1.025ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR +>>>>>>> Stashed changes + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns +======= + Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/C + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR +======= + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.213 -0.601 + SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.356 + ------------------------------------------------------------------- + slack 1.025 + +Slack (MET) : 1.025ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR +>>>>>>> Stashed changes + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) +<<<<<<< Updated upstream + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns +======= + Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR +======= + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/C + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 +======= + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.213 -0.601 + SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.356 + ------------------------------------------------------------------- + slack 1.025 + +Slack (MET) : 1.025ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.213 -0.601 + SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.356 + ------------------------------------------------------------------- + slack 1.025 + +Slack (MET) : 1.025ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.213 -0.601 + SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.356 + ------------------------------------------------------------------- + slack 1.025 + +Slack (MET) : 1.025ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.976ns (logic 0.227ns (23.261%) route 0.749ns (76.739%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.018ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk + SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 + SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=30, routed) 0.609 0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X66Y90 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.213 -0.601 + SLICE_X66Y90 FDCE (Remov_fdce_C_CLR) -0.067 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.668 + arrival time 0.356 + ------------------------------------------------------------------- + slack 1.025 + +Slack (MET) : 1.058ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 1.017ns (logic 0.246ns (24.197%) route 0.771ns (75.803%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.484 0.324 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X92Y110 FDCE f u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.850 -0.458 u_Axi_CDC/awFifo/sys_clk + SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.209 -0.667 + SLICE_X92Y110 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.324 + ------------------------------------------------------------------- + slack 1.058 + +Slack (MET) : 1.058ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 1.017ns (logic 0.246ns (24.197%) route 0.771ns (75.803%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.484 0.324 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X92Y110 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.850 -0.458 u_Axi_CDC/awFifo/sys_clk + SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.209 -0.667 + SLICE_X92Y110 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.324 + ------------------------------------------------------------------- + slack 1.058 + +Slack (MET) : 1.058ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 1.017ns (logic 0.246ns (24.197%) route 0.771ns (75.803%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.484 0.324 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X92Y110 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.850 -0.458 u_Axi_CDC/awFifo/sys_clk + SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.209 -0.667 + SLICE_X92Y110 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.324 + ------------------------------------------------------------------- + slack 1.058 + +Slack (MET) : 1.058ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 1.017ns (logic 0.246ns (24.197%) route 0.771ns (75.803%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.484 0.324 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X92Y110 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.850 -0.458 u_Axi_CDC/awFifo/sys_clk + SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.209 -0.667 + SLICE_X92Y110 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.324 + ------------------------------------------------------------------- + slack 1.058 + +Slack (MET) : 1.083ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 1.017ns (logic 0.246ns (24.197%) route 0.771ns (75.803%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.026ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.693ns + Clock Pessimism Removal (CPR): 0.209ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O + net (fo=43, routed) 0.484 0.324 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X93Y110 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.850 -0.458 u_Axi_CDC/awFifo/sys_clk + SLICE_X93Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.209 -0.667 + SLICE_X93Y110 FDCE (Remov_fdce_C_CLR) -0.092 -0.759 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.759 + arrival time 0.324 + ------------------------------------------------------------------- + slack 1.083 +>>>>>>> Stashed changes @@ -23935,21 +27887,36 @@ Min Delay 59 Endpoints Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf - Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Source: u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cpu/u_csr/csr_estat_reg[3]/D +<<<<<<< Updated upstream + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.686ns (logic 0.418ns (60.951%) route 0.268ns (39.049%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.018ns + Data Path Delay: 0.735ns (logic 0.467ns (63.560%) route 0.268ns (36.440%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.110ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns +======= + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.669ns (logic 0.518ns (77.393%) route 0.151ns (22.607%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.396ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.301ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -23964,12 +27931,25 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/awFifo/sys_clk - SLICE_X16Y69 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 1.718 -2.110 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X49Y58 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X16Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.268 -1.332 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[0] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + SLICE_X49Y58 FDRE (Prop_fdre_C_Q) 0.367 -1.743 r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/Q + net (fo=3, routed) 0.268 -1.476 u_snix_axil_cdma_mux_8ch/ch_done_reg[2]_0 + SLICE_X49Y56 LUT5 (Prop_lut5_I0_O) 0.100 -1.376 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O + net (fo=1, routed) 0.000 -1.376 u_cpu/u_csr/interrupt[1] + SLICE_X49Y56 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D +======= + net (fo=9971, routed) 1.527 -2.301 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X74Y119 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y119 FDRE (Prop_fdre_C_Q) 0.418 -1.883 r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/Q + net (fo=3, routed) 0.151 -1.732 u_snix_axil_cdma_mux_8ch/ch_done_reg[2]_0 + SLICE_X75Y119 LUT5 (Prop_lut5_I1_O) 0.100 -1.632 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O + net (fo=1, routed) 0.000 -1.632 u_cpu/u_csr/interrupt[1] + SLICE_X75Y119 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -23980,9 +27960,10 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.935 -2.407 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.847 -2.495 u_cpu/u_csr/cpu_clk + SLICE_X49Y56 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C @@ -23991,11 +27972,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.622ns (logic 0.367ns (58.974%) route 0.255ns (41.026%)) + Data Path Delay: 0.555ns (logic 0.418ns (75.283%) route 0.137ns (24.717%)) Logic Levels: 0 - Clock Path Skew: -0.391ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.335ns - Source Clock Delay (SCD): -1.943ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24014,12 +27995,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C + net (fo=35652, routed) 1.998 -1.831 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.367 -1.576 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=2, routed) 0.255 -1.321 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=2, routed) 0.137 -1.275 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24030,9 +28011,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.007 -2.335 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C @@ -24041,11 +28022,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.623ns (logic 0.367ns (58.905%) route 0.256ns (41.095%)) + Data Path Delay: 0.559ns (logic 0.418ns (74.744%) route 0.141ns (25.256%)) Logic Levels: 0 - Clock Path Skew: -0.391ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.335ns - Source Clock Delay (SCD): -1.943ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24064,12 +28045,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C + net (fo=35652, routed) 1.998 -1.831 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.367 -1.576 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.256 -1.320 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.141 -1.271 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24080,322 +28061,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.007 -2.335 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf - Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.720ns (logic 0.337ns (46.825%) route 0.383ns (53.175%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.337 -1.681 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.383 -1.299 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.935 -2.407 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.743ns (logic 0.367ns (49.384%) route 0.376ns (50.616%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.406ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/arFifo/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.367 -1.651 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.376 -1.275 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.936 -2.406 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.842ns (logic 0.418ns (49.650%) route 0.424ns (50.350%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/awFifo/sys_clk - SLICE_X16Y69 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X16Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.424 -1.176 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.935 -2.407 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.843ns (logic 0.337ns (39.996%) route 0.506ns (60.004%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.406ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/arFifo/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.337 -1.681 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.506 -1.176 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.936 -2.406 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.782ns (logic 0.367ns (46.956%) route 0.415ns (53.044%)) - Logic Levels: 0 - Clock Path Skew: -0.391ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.335ns - Source Clock Delay (SCD): -1.943ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.367 -1.576 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.415 -1.162 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.007 -2.335 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.630ns (logic 0.367ns (58.287%) route 0.263ns (41.713%)) - Logic Levels: 0 - Clock Path Skew: -0.564ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.316ns - Source Clock Delay (SCD): -1.752ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.385 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q - net (fo=1, routed) 0.263 -1.122 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.026 -2.316 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.632ns (logic 0.367ns (58.089%) route 0.265ns (41.911%)) + Data Path Delay: 0.644ns (logic 0.367ns (56.976%) route 0.277ns (43.024%)) Logic Levels: 0 Clock Path Skew: -0.377ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.129ns - Source Clock Delay (SCD): -1.752ns + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24414,12 +28095,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.385 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.265 -1.120 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.277 -1.188 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[0] + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24430,59 +28111,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.922ns (logic 0.367ns (39.803%) route 0.555ns (60.197%)) - Logic Levels: 0 - Clock Path Skew: -0.379ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.367 -1.650 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.555 -1.095 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C @@ -24491,11 +28122,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.888ns (logic 0.337ns (37.964%) route 0.551ns (62.036%)) + Data Path Delay: 0.656ns (logic 0.385ns (58.677%) route 0.271ns (41.323%)) Logic Levels: 0 - Clock Path Skew: -0.393ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.337ns - Source Clock Delay (SCD): -1.943ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24514,12 +28145,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C + net (fo=35652, routed) 1.998 -1.831 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.337 -1.606 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=4, routed) 0.551 -1.056 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.385 -1.446 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=4, routed) 0.271 -1.175 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24530,78 +28161,39 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C +======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.005 -2.337 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - -Slack: inf - Source: u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[3]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.075ns (logic 0.518ns (48.184%) route 0.557ns (51.816%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.382ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.498ns - Source Clock Delay (SCD): -2.115ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 -2.115 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X56Y62 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X56Y62 FDRE (Prop_fdre_C_Q) 0.418 -1.697 r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/Q - net (fo=3, routed) 0.557 -1.140 u_snix_axil_cdma_mux_8ch/ch_done_reg[2]_0 - SLICE_X57Y58 LUT5 (Prop_lut5_I3_O) 0.100 -1.040 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O - net (fo=1, routed) 0.000 -1.040 u_cpu/u_csr/interrupt[1] - SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.844 -2.498 u_cpu/u_csr/cpu_clk - SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C + net (fo=6484, routed) 1.645 -2.697 u_cpu/u_csr/cpu_clk + SLICE_X75Y119 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C +>>>>>>> Stashed changes Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.742ns (logic 0.367ns (49.468%) route 0.375ns (50.532%)) +<<<<<<< Updated upstream + Data Path Delay: 0.673ns (logic 0.418ns (62.094%) route 0.255ns (37.906%)) Logic Levels: 0 - Clock Path Skew: -0.377ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.129ns - Source Clock Delay (SCD): -1.752ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns +======= + Data Path Delay: 0.682ns (logic 0.418ns (61.288%) route 0.264ns (38.712%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.694ns + Source Clock Delay (SCD): -2.300ns +>>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -24616,12 +28208,21 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.385 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.375 -1.010 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q + net (fo=1, routed) 0.255 -1.159 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D +======= + net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.418 -1.882 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q + net (fo=1, routed) 0.264 -1.618 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24632,76 +28233,49 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.025ns (logic 0.337ns (32.867%) route 0.688ns (67.133%)) + Data Path Delay: 0.675ns (logic 0.418ns (61.898%) route 0.257ns (38.102%)) Logic Levels: 0 - Clock Path Skew: -0.379ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.017ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.337 -1.680 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.688 -0.992 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.073ns (logic 0.367ns (34.191%) route 0.706ns (65.809%)) + Data Path Delay: 0.672ns (logic 0.418ns (62.183%) route 0.254ns (37.817%)) Logic Levels: 0 - Clock Path Skew: -0.379ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.017ns + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.685ns + Source Clock Delay (SCD): -2.290ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -24716,12 +28290,21 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 1.998 -1.831 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.367 -1.650 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.706 -0.944 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.257 -1.155 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D +======= + net (fo=9971, routed) 1.538 -2.290 u_Axi_CDC/bFifo/sys_clk + SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.418 -1.872 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.254 -1.618 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24732,9 +28315,10 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C @@ -24743,11 +28327,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.147ns (logic 0.367ns (31.992%) route 0.780ns (68.008%)) + Data Path Delay: 0.686ns (logic 0.418ns (60.908%) route 0.268ns (39.092%)) Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.406ns - Source Clock Delay (SCD): -2.018ns + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24766,12 +28350,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/arFifo/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/arFifo/sys_clk + SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.367 -1.651 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.780 -0.871 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.268 -1.145 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24782,22 +28366,273 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.698ns (logic 0.385ns (55.120%) route 0.313ns (44.880%)) + Logic Levels: 0 + Clock Path Skew: -0.377ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.834ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.995 -1.834 u_Axi_CDC/bFifo/sys_clk + SLICE_X8Y40 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y40 FDCE (Prop_fdce_C_Q) 0.385 -1.449 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.313 -1.135 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.715ns (logic 0.418ns (58.464%) route 0.297ns (41.536%)) + Logic Levels: 0 + Clock Path Skew: -0.377ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.834ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.995 -1.834 u_Axi_CDC/bFifo/sys_clk + SLICE_X8Y40 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y40 FDCE (Prop_fdce_C_Q) 0.418 -1.416 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.297 -1.119 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C +======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.936 -2.406 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + net (fo=6484, routed) 1.657 -2.685 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C +>>>>>>> Stashed changes Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) +<<<<<<< Updated upstream + Data Path Delay: 0.760ns (logic 0.385ns (50.673%) route 0.375ns (49.327%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns +======= + Data Path Delay: 0.776ns (logic 0.385ns (49.618%) route 0.391ns (50.382%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.694ns + Source Clock Delay (SCD): -2.300ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.385 -1.447 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.375 -1.072 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D +======= + net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.385 -1.915 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.391 -1.524 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] + SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.043ns (logic 0.337ns (32.302%) route 0.706ns (67.698%)) + Data Path Delay: 0.798ns (logic 0.367ns (46.017%) route 0.431ns (53.983%)) Logic Levels: 0 - Clock Path Skew: -0.564ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.316ns - Source Clock Delay (SCD): -1.752ns + Clock Path Skew: -0.377ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.832ns +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.803ns (logic 0.418ns (52.045%) route 0.385ns (47.955%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.280ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.431 -1.034 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D +======= + net (fo=9971, routed) 1.548 -2.280 u_Axi_CDC/awFifo/sys_clk + SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y110 FDCE (Prop_fdce_C_Q) 0.418 -1.862 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.385 -1.477 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[0] + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.815ns (logic 0.385ns (47.225%) route 0.430ns (52.775%)) + Logic Levels: 0 + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24816,12 +28651,196 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/arFifo/sys_clk + SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.337 -1.415 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.706 -0.708 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.385 -1.447 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.430 -1.016 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.828ns (logic 0.418ns (50.501%) route 0.410ns (49.499%)) + Logic Levels: 0 + Clock Path Skew: -0.377ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.834ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.995 -1.834 u_Axi_CDC/bFifo/sys_clk + SLICE_X8Y40 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y40 FDCE (Prop_fdce_C_Q) 0.418 -1.416 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.410 -1.006 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C +>>>>>>> Stashed changes + +Slack: inf + Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D +<<<<<<< Updated upstream + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.826ns (logic 0.418ns (50.576%) route 0.408ns (49.424%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.837ns (logic 0.418ns (49.921%) route 0.419ns (50.079%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.694ns + Source Clock Delay (SCD): -2.300ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.408 -1.005 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D +======= + net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.418 -1.882 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.419 -1.463 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.838ns (logic 0.418ns (49.893%) route 0.420ns (50.107%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.280ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.548 -2.280 u_Axi_CDC/awFifo/sys_clk + SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X92Y110 FDCE (Prop_fdce_C_Q) 0.418 -1.862 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.420 -1.442 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24833,8 +28852,402 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.026 -2.316 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C +>>>>>>> Stashed changes + +Slack: inf + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D +<<<<<<< Updated upstream + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.890ns (logic 0.367ns (41.256%) route 0.523ns (58.744%)) + Logic Levels: 0 + Clock Path Skew: -0.377ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.857ns (logic 0.367ns (42.833%) route 0.490ns (57.167%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.280ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.523 -0.942 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D +======= + net (fo=9971, routed) 1.548 -2.280 u_Axi_CDC/awFifo/sys_clk + SLICE_X93Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X93Y110 FDCE (Prop_fdce_C_Q) 0.367 -1.913 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.490 -1.423 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C +>>>>>>> Stashed changes + +Slack: inf + Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D +<<<<<<< Updated upstream + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.950ns (logic 0.418ns (44.008%) route 0.532ns (55.992%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.968ns (logic 0.418ns (43.176%) route 0.550ns (56.824%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.694ns + Source Clock Delay (SCD): -2.300ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.532 -0.882 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D +======= + net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.418 -1.882 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.550 -1.332 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.959ns (logic 0.418ns (43.591%) route 0.541ns (56.409%)) + Logic Levels: 0 + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.007ns (logic 0.385ns (38.250%) route 0.622ns (61.750%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.685ns + Source Clock Delay (SCD): -2.290ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/arFifo/sys_clk + SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.541 -0.873 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D +======= + net (fo=9971, routed) 1.538 -2.290 u_Axi_CDC/bFifo/sys_clk + SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.385 -1.905 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.622 -1.283 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.657 -2.685 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.033ns (logic 0.418ns (40.449%) route 0.615ns (59.551%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.685ns + Source Clock Delay (SCD): -2.290ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.538 -2.290 u_Axi_CDC/bFifo/sys_clk + SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.418 -1.872 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.615 -1.256 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.657 -2.685 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.901ns (logic 0.337ns (37.384%) route 0.564ns (62.616%)) + Logic Levels: 0 + Clock Path Skew: -0.556ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.692ns + Source Clock Delay (SCD): -2.135ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.693 -2.135 u_Axi_CDC/arFifo/sys_clk + SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.337 -1.798 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.564 -1.234 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.650 -2.692 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C +>>>>>>> Stashed changes + +Slack: inf + Source: u_confreg/int_out_or_q2_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cpu/u_csr/csr_estat_reg[2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) +<<<<<<< Updated upstream + Data Path Delay: 1.250ns (logic 0.337ns (26.970%) route 0.913ns (73.030%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.219ns + Source Clock Delay (SCD): -1.831ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.998 -1.831 u_confreg/sys_clk + SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X9Y47 FDRE (Prop_fdre_C_Q) 0.337 -1.494 r u_confreg/int_out_or_q2_reg/Q + net (fo=1, routed) 0.913 -0.581 u_cpu/u_csr/interrupt[0] + SLICE_X9Y33 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.123 -2.219 u_cpu/u_csr/cpu_clk + SLICE_X9Y33 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C Slack: inf Source: u_matmul_axi_slave/done_reg/C @@ -24843,11 +29256,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.754ns (logic 0.418ns (23.829%) route 1.336ns (76.171%)) + Data Path Delay: 2.161ns (logic 0.367ns (16.979%) route 1.794ns (83.021%)) Logic Levels: 0 - Clock Path Skew: -0.104ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.228ns - Source Clock Delay (SCD): -2.123ns + Clock Path Skew: -0.457ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.494ns + Source Clock Delay (SCD): -2.036ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24866,12 +29279,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 -2.123 u_matmul_axi_slave/sys_clk - SLICE_X46Y72 FDRE r u_matmul_axi_slave/done_reg/C + net (fo=35652, routed) 1.792 -2.036 u_matmul_axi_slave/sys_clk + SLICE_X41Y78 FDRE r u_matmul_axi_slave/done_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X46Y72 FDRE (Prop_fdre_C_Q) 0.418 -1.705 r u_matmul_axi_slave/done_reg/Q - net (fo=12, routed) 1.336 -0.369 u_cpu/u_csr/interrupt[2] - SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D + SLICE_X41Y78 FDRE (Prop_fdre_C_Q) 0.367 -1.669 r u_matmul_axi_slave/done_reg/Q + net (fo=11, routed) 1.794 0.125 u_cpu/u_csr/interrupt[2] + SLICE_X47Y52 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24882,110 +29295,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.114 -2.228 u_cpu/u_csr/cpu_clk - SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C - -Slack: inf - Source: u_confreg/int_out_or_q2_reg/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[2]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.063ns (logic 0.367ns (17.786%) route 1.696ns (82.214%)) - Logic Levels: 0 - Clock Path Skew: -0.223ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.231ns - Source Clock Delay (SCD): -2.007ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.821 -2.007 u_confreg/sys_clk - SLICE_X11Y58 FDRE r u_confreg/int_out_or_q2_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X11Y58 FDRE (Prop_fdre_C_Q) 0.367 -1.640 r u_confreg/int_out_or_q2_reg/Q - net (fo=1, routed) 1.696 0.056 u_cpu/u_csr/interrupt[0] - SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.111 -2.231 u_cpu/u_csr/cpu_clk - SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.149ns (logic 1.078ns (50.163%) route 1.071ns (49.837%)) - Logic Levels: 0 - Clock Path Skew: -0.371ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.394ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.944 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O - net (fo=1, routed) 1.071 0.127 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] - SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.948 -2.394 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.848 -2.494 u_cpu/u_csr/cpu_clk + SLICE_X47Y52 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK @@ -24994,15 +29306,22 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.153ns (logic 1.062ns (49.332%) route 1.091ns (50.668%)) + Data Path Delay: 2.190ns (logic 1.062ns (48.490%) route 1.128ns (51.510%)) Logic Levels: 0 - Clock Path Skew: -0.376ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.398ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: -0.210ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.218ns + Source Clock Delay (SCD): -2.007ns +======= + Data Path Delay: 1.082ns (logic 0.367ns (33.922%) route 0.715ns (66.078%)) + Logic Levels: 0 + Clock Path Skew: -0.389ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.691ns + Source Clock Delay (SCD): -2.302ns +>>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25017,13 +29336,22 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X16Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK +<<<<<<< Updated upstream + net (fo=35652, routed) 1.821 -2.007 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.959 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O - net (fo=1, routed) 1.091 0.131 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] - SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D + SLICE_X16Y54 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -0.945 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O + net (fo=1, routed) 1.128 0.183 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] + SLICE_X16Y34 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D +======= + net (fo=9971, routed) 1.526 -2.302 u_confreg/sys_clk + SLICE_X78Y141 FDRE r u_confreg/int_out_or_q2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y141 FDRE (Prop_fdre_C_Q) 0.367 -1.935 r u_confreg/int_out_or_q2_reg/Q + net (fo=1, routed) 0.715 -1.220 u_cpu/u_csr/interrupt[0] + SLICE_X84Y149 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -25034,111 +29362,10 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.944 -2.398 u_Axi_CDC/rFifo/cpu_clk - SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.174ns (logic 1.056ns (48.570%) route 1.118ns (51.430%)) - Logic Levels: 0 - Clock Path Skew: -0.183ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.208ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.968 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 1.118 0.150 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.202ns (logic 1.078ns (48.964%) route 1.124ns (51.036%)) - Logic Levels: 0 - Clock Path Skew: -0.185ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.946 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 1.124 0.177 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.124 -2.218 u_Axi_CDC/rFifo/cpu_clk + SLICE_X16Y34 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK @@ -25147,15 +29374,37 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.203ns (logic 1.083ns (49.171%) route 1.120ns (50.829%)) + Data Path Delay: 2.232ns (logic 1.083ns (48.530%) route 1.149ns (51.470%)) Logic Levels: 0 - Clock Path Skew: -0.183ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.208ns - Source Clock Delay (SCD): -2.024ns + Clock Path Skew: -0.216ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.224ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.651 -2.691 u_cpu/u_csr/cpu_clk + SLICE_X84Y149 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.927ns (logic 0.367ns (39.581%) route 0.560ns (60.419%)) + Logic Levels: 0 + Clock Path Skew: -0.556ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.692ns + Source Clock Delay (SCD): -2.135ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25170,13 +29419,22 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK +<<<<<<< Updated upstream + net (fo=35652, routed) 1.821 -2.007 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.941 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O - net (fo=1, routed) 1.120 0.178 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D + SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -0.924 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O + net (fo=1, routed) 1.149 0.224 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D +======= + net (fo=9971, routed) 1.693 -2.135 u_Axi_CDC/arFifo/sys_clk + SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.367 -1.768 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.560 -1.208 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -25187,77 +29445,49 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.208ns (logic 1.083ns (49.047%) route 1.125ns (50.953%)) + Data Path Delay: 2.343ns (logic 1.056ns (45.069%) route 1.287ns (54.931%)) Logic Levels: 0 - Clock Path Skew: -0.370ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.395ns - Source Clock Delay (SCD): -2.024ns + Clock Path Skew: -0.220ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.228ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.941 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 1.125 0.184 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] - SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.947 -2.395 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C + net (fo=6484, routed) 1.650 -2.692 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.216ns (logic 1.078ns (48.649%) route 1.138ns (51.351%)) + Data Path Delay: 0.999ns (logic 0.418ns (41.855%) route 0.581ns (58.145%)) Logic Levels: 0 - Clock Path Skew: -0.372ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.394ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: -0.558ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25272,13 +29502,22 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK +<<<<<<< Updated upstream + net (fo=35652, routed) 1.821 -2.007 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.943 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 1.138 0.195 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] - SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.951 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 1.287 0.336 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D +======= + net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk + SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.418 -1.697 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=2, routed) 0.581 -1.117 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -25289,26 +29528,31 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.114 -2.228 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C +======= BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.948 -2.394 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.231ns (logic 1.056ns (47.336%) route 1.175ns (52.664%)) + Data Path Delay: 1.010ns (logic 0.418ns (41.371%) route 0.592ns (58.629%)) Logic Levels: 0 - Clock Path Skew: -0.185ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.024ns + Clock Path Skew: -0.558ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25323,13 +29567,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk + SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.968 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 1.175 0.207 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.418 -1.697 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.592 -1.105 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -25341,25 +29584,25 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.300ns (logic 1.056ns (45.907%) route 1.244ns (54.093%)) + Data Path Delay: 1.033ns (logic 0.367ns (35.528%) route 0.666ns (64.472%)) Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns + Clock Path Skew: -0.556ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.692ns + Source Clock Delay (SCD): -2.135ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25374,13 +29617,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + net (fo=9971, routed) 1.693 -2.135 u_Axi_CDC/arFifo/sys_clk + SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.966 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 1.244 0.278 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D + SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.367 -1.768 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.666 -1.102 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -25392,25 +29634,25 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C + net (fo=6484, routed) 1.650 -2.692 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.329ns (logic 1.084ns (46.543%) route 1.245ns (53.457%)) + Data Path Delay: 1.099ns (logic 0.385ns (35.032%) route 0.714ns (64.968%)) Logic Levels: 0 - Clock Path Skew: -0.369ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.394ns - Source Clock Delay (SCD): -2.024ns + Clock Path Skew: -0.558ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25425,13 +29667,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK + net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk + SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.940 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 1.245 0.305 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] - SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D + SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.385 -1.730 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=4, routed) 0.714 -1.016 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -25443,25 +29684,25 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.948 -2.394 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.337ns (logic 1.059ns (45.323%) route 1.278ns (54.677%)) + Data Path Delay: 1.234ns (logic 0.418ns (33.873%) route 0.816ns (66.127%)) Logic Levels: 0 - Clock Path Skew: -0.373ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.395ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: -0.558ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.674ns + Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25476,13 +29717,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk + SLICE_X62Y94 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.962 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 1.278 0.315 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] - SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D + SLICE_X62Y94 FDCE (Prop_fdce_C_Q) 0.418 -1.697 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.816 -0.881 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -25494,25 +29734,126 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.947 -2.395 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C + net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cpu/u_csr/csr_estat_reg[5]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.609ns (logic 0.385ns (23.934%) route 1.224ns (76.066%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.670ns + Source Clock Delay (SCD): -2.276ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.552 -2.276 u_fft_mlkem_axi_slave/sys_clk + SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X96Y110 FDCE (Prop_fdce_C_Q) 0.385 -1.891 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/Q + net (fo=1, routed) 1.224 -0.667 u_cpu/u_csr/interrupt[3] + SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.672 -2.670 u_cpu/u_csr/cpu_clk + SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.478ns (logic 0.388ns (26.258%) route 1.090ns (73.742%)) + Logic Levels: 0 + Clock Path Skew: 0.146ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.614ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.648 -0.614 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X62Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X62Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.226 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O + net (fo=1, routed) 1.090 0.863 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.340ns (logic 1.059ns (45.262%) route 1.281ns (54.738%)) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.522ns (logic 0.386ns (25.368%) route 1.136ns (74.632%)) Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns + Clock Path Skew: 0.112ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25521,49 +29862,49 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.963 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 1.281 0.317 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.386 -0.193 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O + net (fo=1, routed) 1.136 0.942 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.340ns (logic 1.056ns (45.123%) route 1.284ns (54.877%)) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.546ns (logic 0.394ns (25.488%) route 1.152ns (74.512%)) Logic Levels: 0 - Clock Path Skew: -0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: 0.100ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25572,49 +29913,59 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.965 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O - net (fo=1, routed) 1.284 0.319 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.177 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O + net (fo=1, routed) 1.152 0.974 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C +>>>>>>> Stashed changes Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) +<<<<<<< Updated upstream Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.349ns (logic 1.084ns (46.148%) route 1.265ns (53.852%)) + Data Path Delay: 2.348ns (logic 1.084ns (46.168%) route 1.264ns (53.832%)) Logic Levels: 0 - Clock Path Skew: -0.183ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.208ns - Source Clock Delay (SCD): -2.024ns + Clock Path Skew: -0.220ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.228ns + Source Clock Delay (SCD): -2.007ns +======= + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.695ns (logic 0.478ns (28.202%) route 1.217ns (71.798%)) + Logic Levels: 0 + Clock Path Skew: 0.137ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.608ns +>>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25623,49 +29974,133 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) +<<<<<<< Updated upstream -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK + net (fo=35652, routed) 1.821 -2.007 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.940 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 1.265 0.325 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D + SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -0.923 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O + net (fo=1, routed) 1.264 0.341 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D +======= + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.654 -0.608 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X46Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y95 RAMD32 (Prop_ramd32_CLK_O) + 0.478 -0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 1.217 1.087 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) +<<<<<<< Updated upstream -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.114 -2.228 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C +======= + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.713ns (logic 0.386ns (22.535%) route 1.327ns (77.465%)) + Logic Levels: 0 + Clock Path Skew: 0.100ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.386 -0.185 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O + net (fo=1, routed) 1.327 1.142 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C +>>>>>>> Stashed changes + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +<<<<<<< Updated upstream + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.406ns (logic 1.084ns (45.052%) route 1.322ns (54.948%)) + Logic Levels: 0 + Clock Path Skew: -0.208ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.223ns + Source Clock Delay (SCD): -2.014ns +======= Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.378ns (logic 1.083ns (45.550%) route 1.295ns (54.450%)) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.735ns (logic 0.394ns (22.711%) route 1.341ns (77.289%)) Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns + Clock Path Skew: 0.111ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.579ns +>>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25674,202 +30109,69 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) +<<<<<<< Updated upstream -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + net (fo=35652, routed) 1.814 -2.014 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.939 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 1.295 0.355 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -0.930 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 1.322 0.392 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] + SLICE_X17Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D +======= + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.185 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O + net (fo=1, routed) 1.341 1.155 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) +<<<<<<< Updated upstream -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.380ns (logic 1.062ns (44.630%) route 1.318ns (55.370%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.960 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 1.318 0.357 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.383ns (logic 1.062ns (44.564%) route 1.321ns (55.436%)) - Logic Levels: 0 - Clock Path Skew: -0.186ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.208ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.959 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 1.321 0.362 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.393ns (logic 1.062ns (44.383%) route 1.331ns (55.617%)) - Logic Levels: 0 - Clock Path Skew: -0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.959 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 1.331 0.372 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.119 -2.223 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C +======= + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.414ns (logic 1.083ns (44.858%) route 1.331ns (55.142%)) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.743ns (logic 0.394ns (22.610%) route 1.349ns (77.390%)) Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns + Clock Path Skew: 0.108ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25878,49 +30180,49 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.939 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 1.331 0.392 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.185 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O + net (fo=1, routed) 1.349 1.163 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.434ns (logic 1.062ns (43.637%) route 1.372ns (56.363%)) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.741ns (logic 0.390ns (22.398%) route 1.351ns (77.602%)) Logic Levels: 0 - Clock Path Skew: -0.185ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.024ns + Clock Path Skew: 0.104ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25929,49 +30231,303 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.962 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 1.372 0.409 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O + net (fo=1, routed) 1.351 1.170 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.785ns (logic 0.492ns (27.569%) route 1.293ns (72.431%)) + Logic Levels: 0 + Clock Path Skew: 0.139ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.608ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.654 -0.608 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X46Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y95 RAMD32 (Prop_ramd32_CLK_O) + 0.492 -0.116 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O + net (fo=1, routed) 1.293 1.176 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.793ns (logic 0.394ns (21.978%) route 1.399ns (78.022%)) + Logic Levels: 0 + Clock Path Skew: 0.137ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.608ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.654 -0.608 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X46Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y95 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.214 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O + net (fo=1, routed) 1.399 1.184 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C + +Slack: inf + Source: u_matmul_axi_slave/done_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cpu/u_csr/csr_estat_reg[4]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.792ns (logic 0.141ns (7.867%) route 1.651ns (92.133%)) + Logic Levels: 0 + Clock Path Skew: 0.151ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.456ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.655 -0.607 u_matmul_axi_slave/sys_clk + SLICE_X45Y98 FDRE r u_matmul_axi_slave/done_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X45Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r u_matmul_axi_slave/done_reg/Q + net (fo=10, routed) 1.651 1.185 u_cpu/u_csr/interrupt[2] + SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.852 -0.456 u_cpu/u_csr/cpu_clk + SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.798ns (logic 0.388ns (21.581%) route 1.410ns (78.419%)) + Logic Levels: 0 + Clock Path Skew: 0.112ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.579ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.191 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O + net (fo=1, routed) 1.410 1.218 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.801ns (logic 0.388ns (21.541%) route 1.413ns (78.459%)) + Logic Levels: 0 + Clock Path Skew: 0.112ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.467ns + Source Clock Delay (SCD): -0.579ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.191 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O + net (fo=1, routed) 1.413 1.222 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y120 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.441ns (logic 1.078ns (44.167%) route 1.363ns (55.833%)) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.823ns (logic 0.390ns (21.395%) route 1.433ns (78.605%)) Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns + Clock Path Skew: 0.108ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -25980,49 +30536,49 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.944 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 1.363 0.418 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.189 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O + net (fo=1, routed) 1.433 1.243 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.491ns (logic 1.083ns (43.479%) route 1.408ns (56.521%)) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.874ns (logic 0.394ns (21.025%) route 1.480ns (78.975%)) Logic Levels: 0 - Clock Path Skew: -0.190ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.212ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: 0.101ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -26031,32 +30587,320 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.692 -0.570 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.176 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O + net (fo=1, routed) 1.480 1.304 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.931ns (logic 0.492ns (25.483%) route 1.439ns (74.517%)) + Logic Levels: 0 + Clock Path Skew: 0.108ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.579ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.492 -0.087 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 1.439 1.351 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.927ns (logic 0.394ns (20.444%) route 1.533ns (79.556%)) + Logic Levels: 0 + Clock Path Skew: 0.102ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.177 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O + net (fo=1, routed) 1.533 1.356 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.930ns (logic 0.478ns (24.771%) route 1.452ns (75.229%)) + Logic Levels: 0 + Clock Path Skew: 0.101ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.570ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.692 -0.570 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 0.478 -0.092 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 1.452 1.359 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.952ns (logic 0.478ns (24.493%) route 1.474ns (75.507%)) + Logic Levels: 0 + Clock Path Skew: 0.108ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.579ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.478 -0.101 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O + net (fo=1, routed) 1.474 1.372 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C +>>>>>>> Stashed changes + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D +<<<<<<< Updated upstream + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.432ns (logic 1.056ns (43.427%) route 1.376ns (56.573%)) + Logic Levels: 0 + Clock Path Skew: -0.210ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.224ns + Source Clock Delay (SCD): -2.013ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.962ns (logic 0.478ns (24.362%) route 1.484ns (75.638%)) + Logic Levels: 0 + Clock Path Skew: 0.110ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.579ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 +<<<<<<< Updated upstream K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK + net (fo=35652, routed) 1.815 -2.013 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.938 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 1.408 0.470 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.957 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 1.376 0.418 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D +======= + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.478 -0.101 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 1.484 1.383 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 +<<<<<<< Updated upstream K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK @@ -26065,66 +30909,41 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.529ns (logic 1.056ns (41.755%) route 1.473ns (58.245%)) + Data Path Delay: 2.459ns (logic 1.056ns (42.943%) route 1.403ns (57.057%)) Logic Levels: 0 - Clock Path Skew: -0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: -0.209ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.224ns + Source Clock Delay (SCD): -2.014ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.965 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 1.473 0.508 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +======= + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.538ns (logic 1.084ns (42.711%) route 1.454ns (57.289%)) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.964ns (logic 0.386ns (19.656%) route 1.578ns (80.344%)) Logic Levels: 0 - Clock Path Skew: -0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: 0.108ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.579ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -26133,49 +30952,49 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.937 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 1.454 0.517 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.386 -0.193 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O + net (fo=1, routed) 1.578 1.384 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.565ns (logic 1.078ns (42.030%) route 1.487ns (57.970%)) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.955ns (logic 0.390ns (19.946%) route 1.565ns (80.054%)) Logic Levels: 0 - Clock Path Skew: -0.190ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.212ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: 0.099ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -26184,45 +31003,595 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.692 -0.570 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.943 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O - net (fo=1, routed) 1.487 0.544 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.180 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O + net (fo=1, routed) 1.565 1.385 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.992ns (logic 0.390ns (19.580%) route 1.602ns (80.420%)) + Logic Levels: 0 + Clock Path Skew: 0.108ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.579ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.189 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O + net (fo=1, routed) 1.602 1.412 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.992ns (logic 0.492ns (24.697%) route 1.500ns (75.303%)) + Logic Levels: 0 + Clock Path Skew: 0.108ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.579ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.492 -0.087 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/O + net (fo=1, routed) 1.500 1.413 u_Axi_CDC/rFifo/_zz_ram_port10__2[18] + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.048ns (logic 0.388ns (18.950%) route 1.660ns (81.050%)) + Logic Levels: 0 + Clock Path Skew: 0.113ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O + net (fo=1, routed) 1.660 1.476 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] + SLICE_X93Y111 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y111 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.130ns (logic 0.388ns (18.217%) route 1.742ns (81.783%)) + Logic Levels: 0 + Clock Path Skew: 0.102ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O + net (fo=1, routed) 1.742 1.559 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.166ns (logic 0.386ns (17.825%) route 1.780ns (82.175%)) + Logic Levels: 0 + Clock Path Skew: 0.102ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.570ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.692 -0.570 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 0.386 -0.184 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O + net (fo=1, routed) 1.780 1.595 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.172ns (logic 0.388ns (17.864%) route 1.784ns (82.136%)) + Logic Levels: 0 + Clock Path Skew: 0.099ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.471ns + Source Clock Delay (SCD): -0.570ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.692 -0.570 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.182 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O + net (fo=1, routed) 1.784 1.602 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/rFifo/cpu_clk + SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.196ns (logic 0.386ns (17.576%) route 1.810ns (82.424%)) + Logic Levels: 0 + Clock Path Skew: 0.102ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.469ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) + 0.386 -0.185 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O + net (fo=1, routed) 1.810 1.625 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.201ns (logic 0.390ns (17.720%) route 1.811ns (82.280%)) + Logic Levels: 0 + Clock Path Skew: 0.103ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.468ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O + net (fo=1, routed) 1.811 1.629 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/rFifo/cpu_clk + SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: sys_clk + To Clock: mlkem_clk + +Max Delay 0 Endpoints +Min Delay 112 Endpoints +-------------------------------------------------------------------------------------- + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.570ns (logic 1.084ns (42.178%) route 1.486ns (57.822%)) + Data Path Delay: 0.629ns (logic 0.367ns (58.312%) route 0.262ns (41.688%)) Logic Levels: 0 - Clock Path Skew: -0.189ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.212ns - Source Clock Delay (SCD): -2.022ns + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.112ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.814 -2.014 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.958 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 1.403 0.445 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r +======= + net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk + SLICE_X54Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y91 FDCE (Prop_fdce_C_Q) 0.367 -1.745 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.262 -1.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[2] + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.660ns (logic 0.337ns (51.055%) route 0.323ns (48.945%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.504ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk + SLICE_X51Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y83 FDCE (Prop_fdce_C_Q) 0.337 -1.780 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.323 -1.457 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C +>>>>>>> Stashed changes + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) +<<<<<<< Updated upstream + Data Path Delay: 2.501ns (logic 1.059ns (42.335%) route 1.442ns (57.665%)) + Logic Levels: 0 + Clock Path Skew: -0.210ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.224ns + Source Clock Delay (SCD): -2.013ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -26241,13 +31610,13 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK + net (fo=35652, routed) 1.815 -2.013 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.938 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 1.486 0.548 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -0.954 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O + net (fo=1, routed) 1.442 0.488 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -26258,9 +31627,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK @@ -26268,12 +31637,12 @@ Slack: inf Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.131ns (logic 0.386ns (34.129%) route 0.745ns (65.871%)) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.513ns (logic 1.059ns (42.141%) route 1.454ns (57.859%)) Logic Levels: 0 - Clock Path Skew: 0.317ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.579ns + Clock Path Skew: -0.209ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.222ns + Source Clock Delay (SCD): -2.012ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -26286,49 +31655,56 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.816 -2.012 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.193 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.745 0.552 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] - SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -0.953 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O + net (fo=1, routed) 1.454 0.501 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] + SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.120 -2.222 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.175ns (logic 0.386ns (32.837%) route 0.789ns (67.163%)) + Data Path Delay: 1.094ns (logic 0.394ns (36.013%) route 0.700ns (63.987%)) Logic Levels: 0 - Clock Path Skew: 0.314ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.263ns - Source Clock Delay (SCD): -0.577ns + Clock Path Skew: 0.299ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.272ns + Source Clock Delay (SCD): -0.571ns +======= + Data Path Delay: 0.672ns (logic 0.385ns (57.253%) route 0.287ns (42.747%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.511ns + Source Clock Delay (SCD): -2.125ns +>>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -26337,45 +31713,59 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) +<<<<<<< Updated upstream -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.191 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 0.789 0.598 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.177 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O + net (fo=1, routed) 0.700 0.523 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] + SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D +======= + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.703 -2.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X74Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y96 FDCE (Prop_fdce_C_Q) 0.385 -1.740 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.287 -1.453 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock mlkem_clk rise edge) + 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 +<<<<<<< Updated upstream K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.036 -0.272 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.178ns (logic 0.394ns (33.456%) route 0.784ns (66.544%)) + Data Path Delay: 1.095ns (logic 0.390ns (35.601%) route 0.705ns (64.399%)) Logic Levels: 0 - Clock Path Skew: 0.315ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.577ns + Clock Path Skew: 0.293ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.278ns + Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -26394,13 +31784,13 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 0.784 0.600 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O + net (fo=1, routed) 0.705 0.524 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -26411,22 +31801,73 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.030 -0.278 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.549ns (logic 1.083ns (42.493%) route 1.466ns (57.507%)) + Logic Levels: 0 + Clock Path Skew: -0.209ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.222ns + Source Clock Delay (SCD): -2.012ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.816 -2.012 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -0.929 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O + net (fo=1, routed) 1.466 0.536 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] + SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.120 -2.222 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.182ns (logic 0.386ns (32.666%) route 0.796ns (67.334%)) + Data Path Delay: 1.116ns (logic 0.390ns (34.953%) route 0.726ns (65.047%)) Logic Levels: 0 - Clock Path Skew: 0.317ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.263ns - Source Clock Delay (SCD): -0.580ns + Clock Path Skew: 0.297ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.275ns + Source Clock Delay (SCD): -0.572ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -26445,13 +31886,13 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.194 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.796 0.601 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.182 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O + net (fo=1, routed) 0.726 0.543 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -26462,9 +31903,3298 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.033 -0.275 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.116ns (logic 0.390ns (34.933%) route 0.726ns (65.067%)) + Logic Levels: 0 + Clock Path Skew: 0.295ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.276ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O + net (fo=1, routed) 0.726 0.545 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] + SLICE_X14Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.565ns (logic 1.056ns (41.172%) route 1.509ns (58.828%)) + Logic Levels: 0 + Clock Path Skew: -0.210ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.225ns + Source Clock Delay (SCD): -2.014ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.814 -2.014 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.958 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 1.509 0.551 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.567ns (logic 1.059ns (41.247%) route 1.508ns (58.753%)) + Logic Levels: 0 + Clock Path Skew: -0.209ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.224ns + Source Clock Delay (SCD): -2.014ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.814 -2.014 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -0.955 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O + net (fo=1, routed) 1.508 0.553 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.129ns (logic 0.388ns (34.373%) route 0.741ns (65.627%)) + Logic Levels: 0 + Clock Path Skew: 0.300ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.272ns + Source Clock Delay (SCD): -0.572ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.184 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O + net (fo=1, routed) 0.741 0.556 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] + SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.036 -0.272 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.135ns (logic 0.394ns (34.715%) route 0.741ns (65.285%)) + Logic Levels: 0 + Clock Path Skew: 0.297ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.274ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.177 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O + net (fo=1, routed) 0.741 0.564 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.034 -0.274 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.148ns (logic 0.386ns (33.633%) route 0.762ns (66.367%)) + Logic Levels: 0 + Clock Path Skew: 0.297ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.274ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.386 -0.185 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O + net (fo=1, routed) 0.762 0.576 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.034 -0.274 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.151ns (logic 0.390ns (33.893%) route 0.761ns (66.107%)) + Logic Levels: 0 + Clock Path Skew: 0.299ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.273ns + Source Clock Delay (SCD): -0.572ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.182 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O + net (fo=1, routed) 0.761 0.578 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.035 -0.273 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.151ns (logic 0.394ns (34.237%) route 0.757ns (65.763%)) + Logic Levels: 0 + Clock Path Skew: 0.295ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.277ns + Source Clock Delay (SCD): -0.572ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.178 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O + net (fo=1, routed) 0.757 0.578 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] + SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk + SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.153ns (logic 0.388ns (33.638%) route 0.765ns (66.362%)) + Logic Levels: 0 + Clock Path Skew: 0.294ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.277ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O + net (fo=1, routed) 0.765 0.582 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] + SLICE_X15Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk + SLICE_X15Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.182ns (logic 0.388ns (32.831%) route 0.794ns (67.169%)) + Logic Levels: 0 + Clock Path Skew: 0.294ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.277ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O + net (fo=1, routed) 0.794 0.610 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] + SLICE_X14Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.224ns (logic 0.390ns (31.861%) route 0.834ns (68.139%)) + Logic Levels: 0 + Clock Path Skew: 0.293ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.278ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O + net (fo=1, routed) 0.834 0.653 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.030 -0.278 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.266ns (logic 0.388ns (30.652%) route 0.878ns (69.348%)) + Logic Levels: 0 + Clock Path Skew: 0.293ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.278ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O + net (fo=1, routed) 0.878 0.694 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.030 -0.278 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.273ns (logic 0.492ns (38.660%) route 0.781ns (61.340%)) + Logic Levels: 0 + Clock Path Skew: 0.297ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.275ns + Source Clock Delay (SCD): -0.572ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.492 -0.080 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.781 0.700 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.033 -0.275 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.727ns (logic 1.056ns (38.721%) route 1.671ns (61.279%)) + Logic Levels: 0 + Clock Path Skew: -0.210ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.223ns + Source Clock Delay (SCD): -2.012ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.816 -2.012 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.956 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O + net (fo=1, routed) 1.671 0.715 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] + SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.119 -2.223 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.291ns (logic 0.492ns (38.120%) route 0.799ns (61.880%)) + Logic Levels: 0 + Clock Path Skew: 0.294ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.277ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.492 -0.079 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 0.799 0.719 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] + SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk + SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.292ns (logic 0.492ns (38.091%) route 0.800ns (61.909%)) + Logic Levels: 0 + Clock Path Skew: 0.298ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.273ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.492 -0.079 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 0.800 0.720 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.035 -0.273 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C +======= + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.831 -2.511 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C +>>>>>>> Stashed changes + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) +<<<<<<< Updated upstream + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.331ns (logic 0.394ns (29.608%) route 0.937ns (70.392%)) + Logic Levels: 0 + Clock Path Skew: 0.294ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.278ns + Source Clock Delay (SCD): -0.572ns +======= + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.673ns (logic 0.418ns (62.094%) route 0.255ns (37.906%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.506ns + Source Clock Delay (SCD): -2.120ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) +<<<<<<< Updated upstream + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.178 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O + net (fo=1, routed) 0.937 0.758 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] + SLICE_X17Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D +======= + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X68Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y92 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.255 -1.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[3] + SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 +<<<<<<< Updated upstream + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.030 -0.278 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C +======= + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.672ns (logic 0.367ns (54.616%) route 0.305ns (45.384%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.504ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk + SLICE_X51Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y83 FDCE (Prop_fdce_C_Q) 0.367 -1.750 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.305 -1.445 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[1] + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.680ns (logic 0.385ns (56.580%) route 0.295ns (43.420%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk + SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.385 -1.735 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=4, routed) 0.295 -1.440 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[3] + SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.722ns (logic 0.418ns (57.896%) route 0.304ns (42.104%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk + SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.304 -1.398 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[0] + SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.760ns (logic 0.385ns (50.673%) route 0.375ns (49.327%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.506ns + Source Clock Delay (SCD): -2.119ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X66Y93 FDCE (Prop_fdce_C_Q) 0.385 -1.734 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.375 -1.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[2] + SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.756ns (logic 0.367ns (48.571%) route 0.389ns (51.429%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.500ns + Source Clock Delay (SCD): -2.112ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk + SLICE_X54Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y91 FDCE (Prop_fdce_C_Q) 0.367 -1.745 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.389 -1.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[1] + SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.842 -2.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.784ns (logic 0.418ns (53.295%) route 0.366ns (46.705%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.505ns + Source Clock Delay (SCD): -2.119ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X66Y93 FDCE (Prop_fdce_C_Q) 0.418 -1.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/Q + net (fo=1, routed) 0.366 -1.335 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[1] + SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.788ns (logic 0.367ns (46.589%) route 0.421ns (53.411%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.504ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk + SLICE_X51Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y83 FDCE (Prop_fdce_C_Q) 0.367 -1.750 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.421 -1.330 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[0] + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.801ns (logic 0.418ns (52.179%) route 0.383ns (47.821%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.511ns + Source Clock Delay (SCD): -2.125ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.703 -2.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X74Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y96 FDCE (Prop_fdce_C_Q) 0.418 -1.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.383 -1.324 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[1] + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.831 -2.511 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.794ns (logic 0.367ns (46.198%) route 0.427ns (53.802%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.112ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk + SLICE_X54Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y91 FDCE (Prop_fdce_C_Q) 0.367 -1.745 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.427 -1.318 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[0] + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.924ns (logic 0.418ns (45.244%) route 0.506ns (54.756%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk + SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=2, routed) 0.506 -1.196 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[2] + SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.948ns (logic 0.418ns (44.102%) route 0.530ns (55.898%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.513ns + Source Clock Delay (SCD): -2.125ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.703 -2.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk + SLICE_X74Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y96 FDCE (Prop_fdce_C_Q) 0.418 -1.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.530 -1.177 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[0] + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.829 -2.513 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.961ns (logic 0.418ns (43.489%) route 0.543ns (56.511%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk + SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.543 -1.159 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[1] + SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk + SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.504ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK + SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.033 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/O + net (fo=1, routed) 0.162 -0.871 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[30] + SLICE_X49Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.314ns (logic 1.062ns (80.806%) route 0.252ns (19.194%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.119ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.057 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/O + net (fo=1, routed) 0.252 -0.805 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[21] + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.326ns (logic 0.418ns (31.525%) route 0.908ns (68.475%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.506ns + Source Clock Delay (SCD): -2.119ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X66Y93 FDCE (Prop_fdce_C_Q) 0.418 -1.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.908 -0.793 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[0] + SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk + SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.332ns (logic 1.062ns (79.740%) route 0.270ns (20.260%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.059 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/O + net (fo=1, routed) 0.270 -0.789 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[39] + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.335ns (logic 1.083ns (81.113%) route 0.252ns (18.887%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.038 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/O + net (fo=1, routed) 0.252 -0.786 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[38] + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.338ns (logic 1.084ns (81.023%) route 0.254ns (18.977%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.119ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.035 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/O + net (fo=1, routed) 0.254 -0.781 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[18] + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.336ns (logic 1.059ns (79.280%) route 0.277ns (20.720%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X64Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y97 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.056 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/O + net (fo=1, routed) 0.277 -0.779 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[35] + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.338ns (logic 1.062ns (79.382%) route 0.276ns (20.618%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.116ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.712 -2.116 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X64Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.054 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/O + net (fo=1, routed) 0.276 -0.778 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[9] + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.344ns (logic 1.056ns (78.582%) route 0.288ns (21.418%)) + Logic Levels: 0 + Clock Path Skew: -0.382ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.504ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X70Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y98 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.065 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/O + net (fo=1, routed) 0.288 -0.777 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[43] + SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.338ns (logic 1.078ns (80.540%) route 0.260ns (19.460%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.037 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/O + net (fo=1, routed) 0.260 -0.777 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[4] + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.349ns (logic 1.062ns (78.741%) route 0.287ns (21.259%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.505ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK + SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.055 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/O + net (fo=1, routed) 0.287 -0.769 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[33] + SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.358ns (logic 1.083ns (79.749%) route 0.275ns (20.251%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.506ns + Source Clock Delay (SCD): -2.119ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.036 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/O + net (fo=1, routed) 0.275 -0.761 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[20] + SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.359ns (logic 1.078ns (79.297%) route 0.281ns (20.703%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X64Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y97 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.037 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/O + net (fo=1, routed) 0.281 -0.756 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[34] + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.364ns (logic 1.083ns (79.398%) route 0.281ns (20.602%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.034 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/O + net (fo=1, routed) 0.281 -0.753 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[8] + SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.364ns (logic 1.083ns (79.398%) route 0.281ns (20.602%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X64Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y97 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.032 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/O + net (fo=1, routed) 0.281 -0.751 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[32] + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.370ns (logic 1.084ns (79.141%) route 0.286ns (20.859%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.508ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK + SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.036 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 0.286 -0.751 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[12] + SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.365ns (logic 1.084ns (79.431%) route 0.281ns (20.569%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.499ns + Source Clock Delay (SCD): -2.112ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK + SLICE_X56Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X56Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.028 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/O + net (fo=1, routed) 0.281 -0.748 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[48] + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.375ns (logic 1.083ns (78.791%) route 0.292ns (21.209%)) + Logic Levels: 0 + Clock Path Skew: -0.382ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.504ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X70Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y98 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.038 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/O + net (fo=1, routed) 0.292 -0.747 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[44] + SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.372ns (logic 1.084ns (78.983%) route 0.288ns (21.017%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.116ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.712 -2.116 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X52Y84 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.032 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/O + net (fo=1, routed) 0.288 -0.744 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[0] + SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X53Y84 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.425ns (logic 1.056ns (74.089%) route 0.369ns (25.911%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.059 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/O + net (fo=1, routed) 0.369 -0.690 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[1] + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.427ns (logic 1.056ns (73.983%) route 0.371ns (26.017%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.505ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK + SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.061 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 0.371 -0.690 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[31] + SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X51Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.434ns (logic 1.059ns (73.825%) route 0.375ns (26.175%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.508ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK + SLICE_X46Y79 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.061 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/O + net (fo=1, routed) 0.375 -0.686 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[11] + SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.444ns (logic 1.062ns (73.543%) route 0.382ns (26.457%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.053 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/O + net (fo=1, routed) 0.382 -0.671 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[3] + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.451ns (logic 1.056ns (72.768%) route 0.395ns (27.232%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.504ns + Source Clock Delay (SCD): -2.118ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.710 -2.118 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y97 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/O + net (fo=1, routed) 0.395 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[49] + SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.458ns (logic 1.056ns (72.406%) route 0.402ns (27.594%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.506ns + Source Clock Delay (SCD): -2.119ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.063 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/O + net (fo=1, routed) 0.402 -0.661 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[19] + SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.462ns (logic 1.059ns (72.423%) route 0.403ns (27.577%)) + Logic Levels: 0 + Clock Path Skew: -0.382ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.504ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/O + net (fo=1, routed) 0.403 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[41] + SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X68Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.461ns (logic 1.056ns (72.257%) route 0.405ns (27.743%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK + SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.064 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 0.405 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[13] + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.454ns (logic 1.078ns (74.152%) route 0.376ns (25.848%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.499ns + Source Clock Delay (SCD): -2.112ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X56Y92 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X56Y92 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.034 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O + net (fo=1, routed) 0.376 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.457ns (logic 1.062ns (72.891%) route 0.395ns (27.109%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X64Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y97 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.053 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/O + net (fo=1, routed) 0.395 -0.658 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[33] + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.463ns (logic 1.062ns (72.614%) route 0.401ns (27.386%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.508ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK + SLICE_X46Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y80 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.058 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/O + net (fo=1, routed) 0.401 -0.658 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[15] + SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.467ns (logic 1.062ns (72.395%) route 0.405ns (27.605%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.508ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK + SLICE_X46Y79 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.058 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/O + net (fo=1, routed) 0.405 -0.653 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[9] + SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.834 -2.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X50Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.463ns (logic 1.059ns (72.373%) route 0.404ns (27.627%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.116ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.712 -2.116 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X64Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.057 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/O + net (fo=1, routed) 0.404 -0.653 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[11] + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.470ns (logic 1.078ns (73.317%) route 0.392ns (26.683%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.043 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/O + net (fo=1, routed) 0.392 -0.651 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[40] + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D + (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.471ns (logic 1.059ns (71.992%) route 0.412ns (28.008%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.505ns + Source Clock Delay (SCD): -2.119ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.060 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/O + net (fo=1, routed) 0.412 -0.648 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[23] + SLICE_X50Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X50Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/C +>>>>>>> Stashed changes @@ -26476,12 +35206,91 @@ From Clock: cpu_clk To Clock: sys_clk Max Delay 0 Endpoints -Min Delay 162 Endpoints +Min Delay 154 Endpoints -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- +Slack: inf +<<<<<<< Updated upstream + Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.503ns (logic 0.367ns (72.947%) route 0.136ns (27.053%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.831ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.514ns (logic 0.367ns (71.372%) route 0.147ns (28.628%)) + Logic Levels: 0 + Clock Path Skew: -0.396ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.688ns + Source Clock Delay (SCD): -2.292ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y43 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.136 -1.328 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[3] + SLICE_X12Y43 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/bFifo/cpu_clk + SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y122 FDCE (Prop_fdce_C_Q) 0.367 -1.925 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.147 -1.778 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[1] + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 2.133 -2.209 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X12Y43 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) @@ -26489,15 +35298,96 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.597ns (logic 0.337ns (56.456%) route 0.260ns (43.544%)) + Data Path Delay: 0.609ns (logic 0.337ns (55.331%) route 0.272ns (44.669%)) Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.008ns + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.213ns + Source Clock Delay (SCD): -1.833ns +======= + net (fo=9971, routed) 1.654 -2.688 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.611ns (logic 0.337ns (55.112%) route 0.274ns (44.888%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.302ns +>>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.996 -1.833 u_Axi_CDC/bFifo/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y40 FDCE (Prop_fdce_C_Q) 0.337 -1.496 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.272 -1.224 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[2] + SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y125 FDCE (Prop_fdce_C_Q) 0.337 -1.965 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=5, routed) 0.274 -1.690 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[3] + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 2.129 -2.213 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C +======= + net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.665ns (logic 0.385ns (57.882%) route 0.280ns (42.118%)) + Logic Levels: 0 + Clock Path Skew: -0.400ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.688ns + Source Clock Delay (SCD): -2.288ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -26512,12 +35402,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C + net (fo=6484, routed) 1.540 -2.288 u_Axi_CDC/bFifo/cpu_clk + SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X17Y58 FDCE (Prop_fdce_C_Q) 0.337 -1.671 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.260 -1.411 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[2] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + SLICE_X96Y122 FDCE (Prop_fdce_C_Q) 0.385 -1.903 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.280 -1.623 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[2] + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -26529,8 +35419,78 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + net (fo=9971, routed) 1.654 -2.688 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C +>>>>>>> Stashed changes + +Slack: inf + Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) +<<<<<<< Updated upstream + Data Path Delay: 0.622ns (logic 0.367ns (58.987%) route 0.255ns (41.013%)) + Logic Levels: 0 + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.831ns +======= + Data Path Delay: 0.672ns (logic 0.418ns (62.186%) route 0.254ns (37.814%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.675ns + Source Clock Delay (SCD): -2.281ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y43 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/Q + net (fo=1, routed) 0.255 -1.209 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[1] + SLICE_X12Y42 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.418 -1.863 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.254 -1.609 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[3] + SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X12Y42 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C @@ -26539,65 +35499,31 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.617ns (logic 0.337ns (54.608%) route 0.280ns (45.392%)) + Data Path Delay: 0.642ns (logic 0.337ns (52.522%) route 0.305ns (47.478%)) Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.403ns - Source Clock Delay (SCD): -2.014ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 -2.014 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y66 FDCE (Prop_fdce_C_Q) 0.337 -1.677 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.280 -1.397 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.831ns +======= + net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf - Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.634ns (logic 0.367ns (57.910%) route 0.267ns (42.090%)) + Data Path Delay: 0.738ns (logic 0.337ns (45.657%) route 0.401ns (54.343%)) Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.403ns - Source Clock Delay (SCD): -2.014ns + Clock Path Skew: -0.402ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.700ns + Source Clock Delay (SCD): -2.298ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -26612,12 +35538,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 -2.014 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C + net (fo=6484, routed) 1.530 -2.298 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X17Y66 FDCE (Prop_fdce_C_Q) 0.367 -1.647 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.267 -1.381 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[0] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + SLICE_X86Y105 FDCE (Prop_fdce_C_Q) 0.337 -1.961 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.401 -1.560 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -26629,25 +35555,26 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + net (fo=9971, routed) 1.642 -2.700 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk + SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf - Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.654ns (logic 0.385ns (58.892%) route 0.269ns (41.108%)) + Data Path Delay: 0.779ns (logic 0.367ns (47.087%) route 0.412ns (52.913%)) Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.018ns + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.302ns +>>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -26661,13 +35588,23 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/arFifo/cpu_clk + SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.385 -1.633 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.269 -1.365 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + SLICE_X17Y47 FDCE (Prop_fdce_C_Q) 0.337 -1.494 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.305 -1.189 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y125 FDCE (Prop_fdce_C_Q) 0.367 -1.935 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=3, routed) 0.412 -1.522 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[2] + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -26679,108 +35616,9 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.621ns (logic 0.337ns (54.306%) route 0.284ns (45.694%)) - Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.337ns - Source Clock Delay (SCD): -1.946ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.337 -1.609 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.284 -1.326 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[2] - SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.005 -2.337 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk - SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.736ns (logic 0.367ns (49.854%) route 0.369ns (50.146%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.008ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/bFifo/cpu_clk - SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y58 FDCE (Prop_fdce_C_Q) 0.367 -1.641 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.369 -1.272 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[0] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 2.131 -2.211 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk + SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C @@ -26789,11 +35627,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.740ns (logic 0.367ns (49.584%) route 0.373ns (50.416%)) + Data Path Delay: 0.684ns (logic 0.418ns (61.129%) route 0.266ns (38.871%)) Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.008ns + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.213ns + Source Clock Delay (SCD): -1.833ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -26811,13 +35649,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.996 -1.833 u_Axi_CDC/bFifo/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X17Y58 FDCE (Prop_fdce_C_Q) 0.367 -1.641 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.373 -1.268 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[1] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + SLICE_X10Y40 FDCE (Prop_fdce_C_Q) 0.418 -1.415 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.266 -1.149 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[1] + SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -26829,258 +35667,8 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.792ns (logic 0.367ns (46.311%) route 0.425ns (53.689%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.403ns - Source Clock Delay (SCD): -2.014ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 -2.014 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y66 FDCE (Prop_fdce_C_Q) 0.367 -1.647 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.425 -1.222 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[1] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.817ns (logic 0.418ns (51.164%) route 0.399ns (48.836%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.399 -1.201 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[0] - SLICE_X13Y69 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.935 -2.407 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.833ns (logic 0.418ns (50.157%) route 0.415ns (49.843%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.415 -1.185 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[1] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.793ns (logic 0.367ns (46.283%) route 0.426ns (53.717%)) - Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.337ns - Source Clock Delay (SCD): -1.946ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.367 -1.579 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/Q - net (fo=1, routed) 0.426 -1.153 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[3] - SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.005 -2.337 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk - SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.632ns (logic 0.337ns (53.354%) route 0.295ns (46.646%)) - Logic Levels: 0 - Clock Path Skew: -0.381ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.131ns - Source Clock Delay (SCD): -1.750ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.337 -1.413 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=5, routed) 0.295 -1.118 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[3] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + net (fo=35652, routed) 2.129 -2.213 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C @@ -27089,11 +35677,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.641ns (logic 0.367ns (57.215%) route 0.274ns (42.785%)) + Data Path Delay: 0.754ns (logic 0.367ns (48.681%) route 0.387ns (51.319%)) Logic Levels: 0 - Clock Path Skew: -0.381ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.131ns - Source Clock Delay (SCD): -1.750ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27111,13 +35699,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 -1.832 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.383 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.274 -1.108 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[1] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + SLICE_X13Y42 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.387 -1.078 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[1] + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27129,21 +35717,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf - Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C + Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.928ns (logic 0.367ns (39.555%) route 0.561ns (60.445%)) + Data Path Delay: 0.782ns (logic 0.385ns (49.223%) route 0.397ns (50.777%)) Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.334ns - Source Clock Delay (SCD): -1.946ns + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27161,13 +35749,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.367 -1.579 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.561 -1.018 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[1] - SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + SLICE_X10Y44 FDCE (Prop_fdce_C_Q) 0.385 -1.446 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.397 -1.049 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27179,21 +35767,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.008 -2.334 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk - SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + net (fo=35652, routed) 2.131 -2.211 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf - Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.770ns (logic 0.367ns (47.632%) route 0.403ns (52.368%)) + Data Path Delay: 0.811ns (logic 0.418ns (51.570%) route 0.393ns (48.430%)) Logic Levels: 0 - Clock Path Skew: -0.381ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.131ns - Source Clock Delay (SCD): -1.750ns + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27211,13 +35799,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.383 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=3, routed) 0.403 -0.979 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[2] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + SLICE_X10Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.393 -1.020 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[0] + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27229,8 +35817,158 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + net (fo=35652, routed) 2.131 -2.211 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.845ns (logic 0.418ns (49.462%) route 0.427ns (50.538%)) + Logic Levels: 0 + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.213ns + Source Clock Delay (SCD): -1.833ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.996 -1.833 u_Axi_CDC/bFifo/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y40 FDCE (Prop_fdce_C_Q) 0.418 -1.415 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.427 -0.988 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[0] + SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.129 -2.213 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.844ns (logic 0.418ns (49.514%) route 0.426ns (50.486%)) + Logic Levels: 0 + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.831ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.426 -0.986 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[1] + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.131 -2.211 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.868ns (logic 0.337ns (38.842%) route 0.531ns (61.158%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.831ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y43 FDCE (Prop_fdce_C_Q) 0.337 -1.494 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.531 -0.963 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[2] + SLICE_X12Y43 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.133 -2.209 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X12Y43 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C @@ -27239,11 +35977,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.000ns (logic 0.367ns (36.693%) route 0.633ns (63.307%)) + Data Path Delay: 0.899ns (logic 0.367ns (40.831%) route 0.532ns (59.169%)) Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.334ns - Source Clock Delay (SCD): -1.946ns + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27261,13 +35999,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.367 -1.579 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.633 -0.946 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[0] - SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + SLICE_X13Y43 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.532 -0.932 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[0] + SLICE_X12Y42 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27279,25 +36017,275 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.008 -2.334 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk - SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X12Y42 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.899ns (logic 0.367ns (40.814%) route 0.532ns (59.186%)) + Logic Levels: 0 + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.831ns +======= + net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.892ns (logic 0.367ns (41.149%) route 0.525ns (58.851%)) + Data Path Delay: 0.781ns (logic 0.367ns (46.998%) route 0.414ns (53.002%)) Logic Levels: 0 - Clock Path Skew: -0.381ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.131ns - Source Clock Delay (SCD): -1.750ns + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.302ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/arFifo/cpu_clk + SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X17Y47 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.532 -0.931 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[1] + SLICE_X16Y47 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y125 FDCE (Prop_fdce_C_Q) 0.367 -1.935 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.414 -1.521 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[0] + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk + SLICE_X16Y47 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.019ns (logic 0.367ns (36.005%) route 0.652ns (63.995%)) + Logic Levels: 0 + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.212ns + Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns +======= + net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.792ns (logic 0.367ns (46.340%) route 0.425ns (53.660%)) + Logic Levels: 0 + Clock Path Skew: -0.396ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.688ns + Source Clock Delay (SCD): -2.292ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 -1.832 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y42 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=3, routed) 0.652 -0.812 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[2] + SLICE_X9Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/bFifo/cpu_clk + SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X95Y122 FDCE (Prop_fdce_C_Q) 0.367 -1.925 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.425 -1.500 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[0] + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 2.130 -2.212 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.035ns (logic 0.337ns (32.545%) route 0.698ns (67.455%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + net (fo=9971, routed) 1.654 -2.688 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.791ns (logic 0.367ns (46.425%) route 0.424ns (53.575%)) + Logic Levels: 0 + Clock Path Skew: -0.393ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.676ns + Source Clock Delay (SCD): -2.283ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 -1.832 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y42 FDCE (Prop_fdce_C_Q) 0.337 -1.495 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=5, routed) 0.698 -0.796 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[3] + SLICE_X12Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.545 -2.283 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X93Y113 FDCE (Prop_fdce_C_Q) 0.367 -1.916 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.424 -1.492 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[1] + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X12Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/D +======= + net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.790ns (logic 0.418ns (52.908%) route 0.372ns (47.092%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.676ns + Source Clock Delay (SCD): -2.281ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -27312,12 +36300,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.383 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.525 -0.858 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[0] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.418 -1.863 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/Q + net (fo=1, routed) 0.372 -1.491 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[1] + SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27329,25 +36317,382 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D + Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.793ns (logic 0.367ns (46.304%) route 0.426ns (53.696%)) + Logic Levels: 0 + Clock Path Skew: -0.392ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.675ns + Source Clock Delay (SCD): -2.283ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.545 -2.283 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X93Y113 FDCE (Prop_fdce_C_Q) 0.367 -1.916 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.426 -1.490 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[0] + SLICE_X92Y112 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y112 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.829ns (logic 0.418ns (50.441%) route 0.411ns (49.559%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.676ns + Source Clock Delay (SCD): -2.281ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.418 -1.863 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.411 -1.452 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[0] + SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.847ns (logic 0.367ns (43.340%) route 0.480ns (56.660%)) + Logic Levels: 0 + Clock Path Skew: -0.398ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.299ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.529 -2.299 u_Axi_CDC/wFifo/cpu_clk + SLICE_X89Y127 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y127 FDCE (Prop_fdce_C_Q) 0.367 -1.932 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.480 -1.452 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[1] + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.870ns (logic 0.367ns (42.168%) route 0.503ns (57.832%)) + Logic Levels: 0 + Clock Path Skew: -0.402ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.700ns + Source Clock Delay (SCD): -2.298ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 -2.298 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y105 FDCE (Prop_fdce_C_Q) 0.367 -1.931 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.503 -1.428 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[1] + SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.642 -2.700 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk + SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.892ns (logic 0.367ns (41.125%) route 0.525ns (58.875%)) + Logic Levels: 0 + Clock Path Skew: -0.402ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.700ns + Source Clock Delay (SCD): -2.298ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.530 -2.298 u_Axi_CDC/arFifo/cpu_clk + SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y105 FDCE (Prop_fdce_C_Q) 0.367 -1.931 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.525 -1.405 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[0] + SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.642 -2.700 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk + SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.974ns (logic 0.337ns (34.595%) route 0.637ns (65.405%)) + Logic Levels: 0 + Clock Path Skew: -0.393ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.676ns + Source Clock Delay (SCD): -2.283ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.545 -2.283 u_Axi_CDC/awFifo/cpu_clk + SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X93Y113 FDCE (Prop_fdce_C_Q) 0.337 -1.946 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.637 -1.309 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.171ns (logic 0.385ns (32.864%) route 0.786ns (67.136%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.675ns + Source Clock Delay (SCD): -2.281ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk + SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.385 -1.896 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.786 -1.109 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[2] + SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D +>>>>>>> Stashed changes (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.215ns (logic 1.056ns (86.901%) route 0.159ns (13.099%)) + Data Path Delay: 1.240ns (logic 1.078ns (86.936%) route 0.162ns (13.064%)) Logic Levels: 0 +<<<<<<< Updated upstream Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.009ns + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns +======= + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.684ns + Source Clock Delay (SCD): -2.290ns +>>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -27361,14 +36706,25 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.953 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/O - net (fo=1, routed) 0.159 -0.794 u_Axi_CDC/awFifo/_zz_ram_port10[1] - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D + SLICE_X18Y56 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -0.929 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/O + net (fo=1, routed) 0.162 -0.767 u_Axi_CDC/awFifo/_zz_ram_port10[34] + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/D +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.234 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.159 -1.075 u_Axi_CDC/awFifo/_zz_ram_port10[7] + SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27380,365 +36736,9 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.218ns (logic 1.059ns (86.968%) route 0.159ns (13.032%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.009ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.950 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/O - net (fo=1, routed) 0.159 -0.792 u_Axi_CDC/awFifo/_zz_ram_port10[5] - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.399ns - Source Clock Delay (SCD): -2.011ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.817 -2.011 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.949 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/O - net (fo=1, routed) 0.159 -0.791 u_Axi_CDC/awFifo/_zz_ram_port10[45] - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.943 -2.399 u_Axi_CDC/awFifo/sys_clk - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.009ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.947 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/O - net (fo=1, routed) 0.159 -0.789 u_Axi_CDC/awFifo/_zz_ram_port10[3] - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) - Logic Levels: 0 - Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.940 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/O - net (fo=1, routed) 0.162 -0.778 u_Axi_CDC/arFifo/_zz_ram_port10__1[6] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.934 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/O - net (fo=1, routed) 0.162 -0.772 u_Axi_CDC/arFifo/_zz_ram_port10__1[48] - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.245ns (logic 1.083ns (86.954%) route 0.162ns (13.046%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.404ns - Source Clock Delay (SCD): -2.015ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.813 -2.015 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.932 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/O - net (fo=1, routed) 0.162 -0.770 u_Axi_CDC/arFifo/_zz_ram_port10__1[44] - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.938 -2.404 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.404ns - Source Clock Delay (SCD): -2.015ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.813 -2.015 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.931 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/O - net (fo=1, routed) 0.162 -0.769 u_Axi_CDC/arFifo/_zz_ram_port10__1[42] - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.938 -2.404 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK @@ -27747,11 +36747,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.329ns (logic 1.078ns (81.137%) route 0.251ns (18.863%)) + Data Path Delay: 1.359ns (logic 1.078ns (79.297%) route 0.281ns (20.703%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27769,14 +36769,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.946 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/O - net (fo=1, routed) 0.251 -0.696 u_Axi_CDC/arFifo/_zz_ram_port10__1[10] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D + SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.030 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/O + net (fo=1, routed) 0.281 -0.749 u_Axi_CDC/arFifo/_zz_ram_port10__1[10] + SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27788,21 +36788,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/C + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/C Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.340ns (logic 1.062ns (79.263%) route 0.278ns (20.737%)) + Data Path Delay: 1.363ns (logic 1.084ns (79.504%) route 0.279ns (20.496%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27820,14 +36820,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.962 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/O - net (fo=1, routed) 0.278 -0.684 u_Axi_CDC/arFifo/_zz_ram_port10__1[3] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D + SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.024 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/O + net (fo=1, routed) 0.279 -0.745 u_Axi_CDC/arFifo/_zz_ram_port10__1[6] + SLICE_X44Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27839,21 +36839,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/C + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X44Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.338ns (logic 1.059ns (79.147%) route 0.279ns (20.853%)) + Data Path Delay: 1.106ns (logic 0.367ns (33.193%) route 0.739ns (66.807%)) Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27871,14 +36871,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/arFifo/cpu_clk + SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.962 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/O - net (fo=1, routed) 0.279 -0.683 u_Axi_CDC/awFifo/_zz_ram_port10[53] - SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D + SLICE_X17Y47 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.739 -0.725 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[0] + SLICE_X16Y47 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27890,8 +36889,8 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/C + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk + SLICE_X16Y47 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK @@ -27900,313 +36899,7 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.334ns (logic 1.056ns (79.142%) route 0.278ns (20.858%)) - Logic Levels: 0 - Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.404ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X18Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.961 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/O - net (fo=1, routed) 0.278 -0.683 u_Axi_CDC/arFifo/_zz_ram_port10__1[37] - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.938 -2.404 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.340ns (logic 1.062ns (79.249%) route 0.278ns (20.751%)) - Logic Levels: 0 - Clock Path Skew: -0.393ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.412ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.956 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/O - net (fo=1, routed) 0.278 -0.678 u_Axi_CDC/arFifo/_zz_ram_port10__1[51] - SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.930 -2.412 u_Axi_CDC/arFifo/sys_clk - SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.337ns (logic 1.056ns (79.009%) route 0.281ns (20.991%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.403ns - Source Clock Delay (SCD): -2.013ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK - SLICE_X16Y65 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.957 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/O - net (fo=1, routed) 0.281 -0.677 u_Axi_CDC/awFifo/_zz_ram_port10[37] - SLICE_X19Y66 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/awFifo/sys_clk - SLICE_X19Y66 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.360ns (logic 1.078ns (79.282%) route 0.282ns (20.718%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.410ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.943 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/O - net (fo=1, routed) 0.282 -0.662 u_Axi_CDC/awFifo/_zz_ram_port10[52] - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.932 -2.410 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.364ns (logic 1.083ns (79.398%) route 0.281ns (20.602%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.398ns - Source Clock Delay (SCD): -2.009ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.926 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/O - net (fo=1, routed) 0.281 -0.645 u_Axi_CDC/awFifo/_zz_ram_port10[2] - SLICE_X21Y59 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.944 -2.398 u_Axi_CDC/awFifo/sys_clk - SLICE_X21Y59 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.411ns (logic 1.062ns (75.266%) route 0.349ns (24.734%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.402ns - Source Clock Delay (SCD): -2.013ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK - SLICE_X16Y65 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.951 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/O - net (fo=1, routed) 0.349 -0.602 u_Axi_CDC/awFifo/_zz_ram_port10[39] - SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.940 -2.402 u_Axi_CDC/awFifo/sys_clk - SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.432ns (logic 1.083ns (75.645%) route 0.349ns (24.355%)) + Data Path Delay: 1.301ns (logic 1.056ns (81.139%) route 0.245ns (18.861%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.396ns @@ -28228,14 +36921,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X20Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y57 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.925 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/O - net (fo=1, routed) 0.349 -0.577 u_Axi_CDC/awFifo/_zz_ram_port10[8] - SLICE_X15Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D + SLICE_X20Y54 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.952 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/O + net (fo=1, routed) 0.245 -0.707 u_Axi_CDC/arFifo/_zz_ram_port10__1[37] + SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28247,21 +36940,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/C + net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/arFifo/sys_clk + SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.451ns (logic 1.056ns (72.768%) route 0.395ns (27.232%)) + Data Path Delay: 1.301ns (logic 1.056ns (81.139%) route 0.245ns (18.861%)) Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.410ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28279,14 +36972,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.965 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/O - net (fo=1, routed) 0.395 -0.570 u_Axi_CDC/awFifo/_zz_ram_port10[49] - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D + SLICE_X18Y56 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.951 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/O + net (fo=1, routed) 0.245 -0.706 u_Axi_CDC/awFifo/_zz_ram_port10[31] + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28298,21 +36991,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.932 -2.410 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/C + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK + Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.454ns (logic 1.062ns (73.041%) route 0.392ns (26.959%)) + Data Path Delay: 1.328ns (logic 1.056ns (79.500%) route 0.272ns (20.500%)) Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.410ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.412ns + Source Clock Delay (SCD): -2.025ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28330,14 +37023,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.803 -2.025 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK + SLICE_X40Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.959 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/O - net (fo=1, routed) 0.392 -0.567 u_Axi_CDC/awFifo/_zz_ram_port10[51] - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D + SLICE_X40Y57 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.969 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.272 -0.697 u_Axi_CDC/awFifo/_zz_ram_port10[13] + SLICE_X38Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28349,21 +37042,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.932 -2.410 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/C + net (fo=35652, routed) 1.930 -2.412 u_Axi_CDC/awFifo/sys_clk + SLICE_X38Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.454ns (logic 1.059ns (72.851%) route 0.395ns (27.149%)) + Data Path Delay: 1.331ns (logic 1.083ns (81.357%) route 0.248ns (18.643%)) Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.409ns - Source Clock Delay (SCD): -2.018ns + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28381,14 +37074,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y67 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.959 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/O - net (fo=1, routed) 0.395 -0.565 u_Axi_CDC/awFifo/_zz_ram_port10[35] - SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D + SLICE_X18Y56 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -0.924 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/O + net (fo=1, routed) 0.248 -0.676 u_Axi_CDC/awFifo/_zz_ram_port10[32] + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28400,8 +37093,160 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.933 -2.409 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/C + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.157ns (logic 0.367ns (31.718%) route 0.790ns (68.282%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 -1.832 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y42 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.790 -0.675 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[0] + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.333ns (logic 1.062ns (79.680%) route 0.271ns (20.320%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -0.945 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/O + net (fo=1, routed) 0.271 -0.674 u_Axi_CDC/arFifo/_zz_ram_port10__1[33] + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.338ns (logic 1.062ns (79.382%) route 0.276ns (20.618%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.396ns + Source Clock Delay (SCD): -2.008ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X20Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X20Y54 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -0.946 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/O + net (fo=1, routed) 0.276 -0.670 u_Axi_CDC/arFifo/_zz_ram_port10__1[39] + SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/arFifo/sys_clk + SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK @@ -28410,11 +37255,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.453ns (logic 1.056ns (72.668%) route 0.397ns (27.332%)) + Data Path Delay: 1.344ns (logic 1.056ns (78.598%) route 0.288ns (21.402%)) Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.017ns + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28432,14 +37277,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X16Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.961 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/O - net (fo=1, routed) 0.397 -0.564 u_Axi_CDC/arFifo/_zz_ram_port10__1[31] - SLICE_X16Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D + SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.951 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/O + net (fo=1, routed) 0.288 -0.664 u_Axi_CDC/arFifo/_zz_ram_port10__1[31] + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28451,25 +37296,42 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk - SLICE_X16Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/C + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.348ns (logic 1.062ns (78.762%) route 0.286ns (21.238%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.394ns + Source Clock Delay (SCD): -2.006ns +======= + net (fo=9971, routed) 1.658 -2.684 u_Axi_CDC/awFifo/sys_clk + SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.457ns (logic 1.062ns (72.904%) route 0.395ns (27.096%)) + Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%)) Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.409ns - Source Clock Delay (SCD): -2.018ns + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.669ns + Source Clock Delay (SCD): -2.275ns +>>>>>>> Stashed changes Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -28483,14 +37345,25 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y67 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X16Y50 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.956 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/O - net (fo=1, routed) 0.395 -0.562 u_Axi_CDC/awFifo/_zz_ram_port10[33] - SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D + SLICE_X16Y50 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -0.944 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/O + net (fo=1, routed) 0.286 -0.658 u_Axi_CDC/arFifo/_zz_ram_port10__1[45] + SLICE_X15Y50 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.553 -2.275 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X60Y100 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X60Y100 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.213 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/O + net (fo=1, routed) 0.159 -1.054 u_Axi_CDC/awFifo/_zz_ram_port10[33] + SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28502,161 +37375,9 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.933 -2.409 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.482ns (logic 1.083ns (73.069%) route 0.399ns (26.931%)) - Logic Levels: 0 - Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.941 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/O - net (fo=1, routed) 0.399 -0.542 u_Axi_CDC/arFifo/_zz_ram_port10__1[8] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.482ns (logic 1.083ns (73.083%) route 0.399ns (26.917%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.938 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/O - net (fo=1, routed) 0.399 -0.539 u_Axi_CDC/awFifo/_zz_ram_port10[50] - SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.479ns (logic 1.078ns (72.907%) route 0.401ns (27.093%)) - Logic Levels: 0 - Clock Path Skew: -0.391ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.409ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X16Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.939 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.401 -0.539 u_Axi_CDC/arFifo/_zz_ram_port10__1[34] - SLICE_X17Y71 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.933 -2.409 u_Axi_CDC/arFifo/sys_clk - SLICE_X17Y71 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 1.948 -2.394 u_Axi_CDC/arFifo/sys_clk + SLICE_X15Y50 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK @@ -28665,117 +37386,36 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.493ns (logic 1.056ns (70.750%) route 0.437ns (29.250%)) + Data Path Delay: 1.451ns (logic 1.056ns (72.768%) route 0.395ns (27.232%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.968 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/O - net (fo=1, routed) 0.437 -0.532 u_Axi_CDC/arFifo/_zz_ram_port10__1[7] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/C +======= + net (fo=9971, routed) 1.673 -2.669 u_Axi_CDC/awFifo/sys_clk + SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/C Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D + Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.493ns (logic 1.056ns (70.750%) route 0.437ns (29.250%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.962 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/O - net (fo=1, routed) 0.437 -0.526 u_Axi_CDC/arFifo/_zz_ram_port10__1[49] - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.496ns (logic 1.059ns (70.775%) route 0.437ns (29.225%)) + Data Path Delay: 1.312ns (logic 1.062ns (80.930%) route 0.250ns (19.070%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.412ns - Source Clock Delay (SCD): -2.018ns + Destination Clock Delay (DCD): -2.699ns + Source Clock Delay (SCD): -2.306ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns +>>>>>>> Stashed changes Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -28789,14 +37429,25 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK +<<<<<<< Updated upstream + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.959 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/O - net (fo=1, routed) 0.437 -0.522 u_Axi_CDC/arFifo/_zz_ram_port10__1[53] - SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/D + SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.052 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.395 -0.657 u_Axi_CDC/arFifo/_zz_ram_port10__1[7] + SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D +======= + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.522 -2.306 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X84Y117 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y117 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.244 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/O + net (fo=1, routed) 0.250 -0.994 u_Axi_CDC/arFifo/_zz_ram_port10__1[15] + SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28808,25 +37459,33 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.930 -2.412 u_Axi_CDC/arFifo/sys_clk - SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/C Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D +======= + net (fo=9971, routed) 1.643 -2.699 u_Axi_CDC/arFifo/sys_clk + SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.497ns (logic 1.059ns (70.746%) route 0.438ns (29.254%)) + Data Path Delay: 1.335ns (logic 1.084ns (81.206%) route 0.251ns (18.794%)) Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.017ns + Clock Path Skew: -0.393ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.699ns + Source Clock Delay (SCD): -2.306ns Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns + Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups @@ -28841,13 +37500,13 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X18Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK + net (fo=6484, routed) 1.522 -2.306 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X84Y117 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.958 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/O - net (fo=1, routed) 0.438 -0.520 u_Axi_CDC/arFifo/_zz_ram_port10__1[41] - SLICE_X20Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D + SLICE_X84Y117 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.222 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/O + net (fo=1, routed) 0.251 -0.971 u_Axi_CDC/arFifo/_zz_ram_port10__1[12] + SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28859,72 +37518,1693 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.935 -2.407 u_Axi_CDC/arFifo/sys_clk - SLICE_X20Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/C + net (fo=9971, routed) 1.643 -2.699 u_Axi_CDC/arFifo/sys_clk + SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.335ns (logic 1.059ns (79.339%) route 0.276ns (20.661%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.681ns + Source Clock Delay (SCD): -2.287ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X72Y104 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X72Y104 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.228 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/O + net (fo=1, routed) 0.276 -0.952 u_Axi_CDC/arFifo/_zz_ram_port10__1[47] + SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.661 -2.681 u_Axi_CDC/arFifo/sys_clk + SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.345ns (logic 1.059ns (78.719%) route 0.286ns (21.281%)) + Logic Levels: 0 + Clock Path Skew: -0.391ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.678ns + Source Clock Delay (SCD): -2.287ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X70Y103 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y103 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.228 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/O + net (fo=1, routed) 0.286 -0.942 u_Axi_CDC/arFifo/_zz_ram_port10__1[35] + SLICE_X68Y103 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.664 -2.678 u_Axi_CDC/arFifo/sys_clk + SLICE_X68Y103 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.354ns (logic 1.056ns (77.964%) route 0.298ns (22.036%)) + Logic Levels: 0 + Clock Path Skew: -0.400ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.692ns + Source Clock Delay (SCD): -2.292ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK + SLICE_X90Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y130 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.236 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 0.298 -0.937 u_Axi_CDC/wFifo/_zz_ram_port10__0[25] + SLICE_X88Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.650 -2.692 u_Axi_CDC/wFifo/sys_clk + SLICE_X88Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.493ns (logic 1.059ns (70.929%) route 0.434ns (29.071%)) + Data Path Delay: 1.345ns (logic 1.059ns (78.719%) route 0.286ns (21.281%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.675ns + Source Clock Delay (SCD): -2.281ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.222 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/O + net (fo=1, routed) 0.286 -0.936 u_Axi_CDC/awFifo/_zz_ram_port10[47] + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/sys_clk + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.375ns (logic 1.083ns (78.791%) route 0.292ns (21.209%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.675ns + Source Clock Delay (SCD): -2.281ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.198 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/O + net (fo=1, routed) 0.292 -0.906 u_Axi_CDC/awFifo/_zz_ram_port10[44] + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/sys_clk + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.428ns (logic 1.056ns (73.931%) route 0.372ns (26.069%)) + Logic Levels: 0 + Clock Path Skew: -0.393ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.699ns + Source Clock Delay (SCD): -2.306ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.522 -2.306 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X84Y117 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y117 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.250 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.372 -0.878 u_Axi_CDC/arFifo/_zz_ram_port10__1[13] + SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.643 -2.699 u_Axi_CDC/arFifo/sys_clk + SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.462ns (logic 1.059ns (72.441%) route 0.403ns (27.559%)) + Logic Levels: 0 + Clock Path Skew: -0.391ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.699ns + Source Clock Delay (SCD): -2.308ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.520 -2.308 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X84Y118 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y118 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.249 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/O + net (fo=1, routed) 0.403 -0.846 u_Axi_CDC/arFifo/_zz_ram_port10__1[5] + SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.643 -2.699 u_Axi_CDC/arFifo/sys_clk + SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.457ns (logic 1.078ns (73.968%) route 0.379ns (26.032%)) + Logic Levels: 0 + Clock Path Skew: -0.410ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.712ns + Source Clock Delay (SCD): -2.302ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK + SLICE_X88Y125 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y125 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.224 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/O + net (fo=1, routed) 0.379 -0.844 u_Axi_CDC/wFifo/_zz_ram_port10__0[34] + SLICE_X86Y125 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.630 -2.712 u_Axi_CDC/wFifo/sys_clk + SLICE_X86Y125 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.457ns (logic 1.083ns (74.327%) route 0.374ns (25.673%)) + Logic Levels: 0 + Clock Path Skew: -0.408ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.703ns + Source Clock Delay (SCD): -2.295ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.533 -2.295 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK + SLICE_X88Y131 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y131 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.212 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/O + net (fo=1, routed) 0.374 -0.838 u_Axi_CDC/wFifo/_zz_ram_port10__0[8] + SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.639 -2.703 u_Axi_CDC/wFifo/sys_clk + SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.454ns (logic 1.056ns (72.605%) route 0.398ns (27.395%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.681ns + Source Clock Delay (SCD): -2.287ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK + SLICE_X70Y105 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y105 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.231 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/O + net (fo=1, routed) 0.398 -0.832 u_Axi_CDC/arFifo/_zz_ram_port10__1[19] + SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.661 -2.681 u_Axi_CDC/arFifo/sys_clk + SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.456ns (logic 1.062ns (72.954%) route 0.394ns (27.046%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.681ns + Source Clock Delay (SCD): -2.287ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X72Y104 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X72Y104 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.225 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/O + net (fo=1, routed) 0.394 -0.831 u_Axi_CDC/arFifo/_zz_ram_port10__1[45] + SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.661 -2.681 u_Axi_CDC/arFifo/sys_clk + SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.481ns (logic 1.078ns (72.808%) route 0.403ns (27.192%)) + Logic Levels: 0 + Clock Path Skew: -0.391ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.699ns + Source Clock Delay (SCD): -2.308ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.520 -2.308 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X84Y118 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y118 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.230 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/O + net (fo=1, routed) 0.403 -0.827 u_Axi_CDC/arFifo/_zz_ram_port10__1[4] + SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.643 -2.699 u_Axi_CDC/arFifo/sys_clk + SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.465ns (logic 1.062ns (72.476%) route 0.403ns (27.524%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.675ns + Source Clock Delay (SCD): -2.281ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.219 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/O + net (fo=1, routed) 0.403 -0.816 u_Axi_CDC/awFifo/_zz_ram_port10[45] + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/sys_clk + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.476ns (logic 1.078ns (73.019%) route 0.398ns (26.981%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.681ns + Source Clock Delay (SCD): -2.287ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X72Y104 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X72Y104 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.209 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/O + net (fo=1, routed) 0.398 -0.811 u_Axi_CDC/arFifo/_zz_ram_port10__1[46] + SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.661 -2.681 u_Axi_CDC/arFifo/sys_clk + SLICE_X72Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.483ns (logic 1.059ns (71.419%) route 0.424ns (28.581%)) + Logic Levels: 0 + Clock Path Skew: -0.397ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.684ns + Source Clock Delay (SCD): -2.287ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X90Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y115 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.228 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/O + net (fo=1, routed) 0.424 -0.804 u_Axi_CDC/awFifo/_zz_ram_port10[5] + SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.658 -2.684 u_Axi_CDC/awFifo/sys_clk + SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.490ns (logic 1.059ns (71.080%) route 0.431ns (28.920%)) + Logic Levels: 0 + Clock Path Skew: -0.389ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.676ns + Source Clock Delay (SCD): -2.287ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK + SLICE_X70Y105 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y105 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.228 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/O + net (fo=1, routed) 0.431 -0.797 u_Axi_CDC/arFifo/_zz_ram_port10__1[23] + SLICE_X64Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/arFifo/sys_clk + SLICE_X64Y105 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.511ns (logic 1.056ns (69.870%) route 0.455ns (30.130%)) + Logic Levels: 0 + Clock Path Skew: -0.410ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.712ns + Source Clock Delay (SCD): -2.302ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK + SLICE_X88Y125 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y125 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.246 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 0.455 -0.791 u_Axi_CDC/wFifo/_zz_ram_port10__0[31] + SLICE_X86Y125 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.630 -2.712 u_Axi_CDC/wFifo/sys_clk + SLICE_X86Y125 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.486ns (logic 1.083ns (72.891%) route 0.403ns (27.109%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.669ns + Source Clock Delay (SCD): -2.275ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.553 -2.275 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X60Y100 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X60Y100 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.192 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/O + net (fo=1, routed) 0.403 -0.789 u_Axi_CDC/awFifo/_zz_ram_port10[32] + SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.673 -2.669 u_Axi_CDC/awFifo/sys_clk + SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.498ns (logic 1.083ns (72.295%) route 0.415ns (27.705%)) + Logic Levels: 0 + Clock Path Skew: -0.391ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.678ns + Source Clock Delay (SCD): -2.287ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X72Y104 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X72Y104 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.204 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/O + net (fo=1, routed) 0.415 -0.789 u_Axi_CDC/arFifo/_zz_ram_port10__1[44] + SLICE_X68Y103 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.664 -2.678 u_Axi_CDC/arFifo/sys_clk + SLICE_X68Y103 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.492ns (logic 1.056ns (70.798%) route 0.436ns (29.202%)) + Logic Levels: 0 + Clock Path Skew: -0.395ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.675ns + Source Clock Delay (SCD): -2.280ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.548 -2.280 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK + SLICE_X62Y103 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X62Y103 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.224 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/O + net (fo=1, routed) 0.436 -0.788 u_Axi_CDC/awFifo/_zz_ram_port10[37] + SLICE_X63Y103 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/sys_clk + SLICE_X63Y103 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.499ns (logic 1.078ns (71.932%) route 0.421ns (28.068%)) + Logic Levels: 0 + Clock Path Skew: -0.397ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.684ns + Source Clock Delay (SCD): -2.287ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.541 -2.287 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X90Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y115 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.209 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/O + net (fo=1, routed) 0.421 -0.788 u_Axi_CDC/awFifo/_zz_ram_port10[4] + SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.658 -2.684 u_Axi_CDC/awFifo/sys_clk + SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) +>>>>>>> Stashed changes + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) +<<<<<<< Updated upstream + Data Path Delay: 1.359ns (logic 1.078ns (79.297%) route 0.281ns (20.703%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.399ns - Source Clock Delay (SCD): -2.011ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.817 -2.011 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.952 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/O - net (fo=1, routed) 0.434 -0.518 u_Axi_CDC/awFifo/_zz_ram_port10[47] - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.943 -2.399 u_Axi_CDC/awFifo/sys_clk - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.511ns (logic 1.083ns (71.691%) route 0.428ns (28.309%)) + Destination Clock Delay (DCD): -2.396ns + Source Clock Delay (SCD): -2.008ns +======= + Data Path Delay: 1.497ns (logic 1.078ns (72.028%) route 0.419ns (27.972%)) Logic Levels: 0 - Clock Path Skew: -0.382ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.024ns + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.675ns + Source Clock Delay (SCD): -2.281ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.203 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/O + net (fo=1, routed) 0.419 -0.784 u_Axi_CDC/awFifo/_zz_ram_port10[46] + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/sys_clk + SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.503ns (logic 1.056ns (70.245%) route 0.447ns (29.755%)) + Logic Levels: 0 + Clock Path Skew: -0.391ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.677ns + Source Clock Delay (SCD): -2.286ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.542 -2.286 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y100 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y100 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.230 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/O + net (fo=1, routed) 0.447 -0.783 u_Axi_CDC/arFifo/_zz_ram_port10__1[37] + SLICE_X67Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.665 -2.677 u_Axi_CDC/arFifo/sys_clk + SLICE_X67Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.504ns (logic 1.059ns (70.399%) route 0.445ns (29.601%)) + Logic Levels: 0 + Clock Path Skew: -0.391ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.677ns + Source Clock Delay (SCD): -2.286ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.542 -2.286 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X70Y100 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X70Y100 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.227 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/O + net (fo=1, routed) 0.445 -0.782 u_Axi_CDC/arFifo/_zz_ram_port10__1[41] + SLICE_X67Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.665 -2.677 u_Axi_CDC/arFifo/sys_clk + SLICE_X67Y100 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.516ns (logic 1.056ns (69.676%) route 0.460ns (30.324%)) + Logic Levels: 0 + Clock Path Skew: -0.394ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.679ns + Source Clock Delay (SCD): -2.285ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.543 -2.285 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK + SLICE_X90Y112 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X90Y112 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.229 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/O + net (fo=1, routed) 0.460 -0.769 u_Axi_CDC/awFifo/_zz_ram_port10[25] + SLICE_X89Y105 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.663 -2.679 u_Axi_CDC/awFifo/sys_clk + SLICE_X89Y105 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.534ns (logic 1.056ns (68.850%) route 0.478ns (31.150%)) + Logic Levels: 0 + Clock Path Skew: -0.397ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.300ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.528 -2.300 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK + SLICE_X84Y109 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y109 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.244 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/O + net (fo=1, routed) 0.478 -0.766 u_Axi_CDC/arFifo/_zz_ram_port10__1[25] + SLICE_X81Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/arFifo/sys_clk + SLICE_X81Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.531ns (logic 1.078ns (70.406%) route 0.453ns (29.594%)) + Logic Levels: 0 + Clock Path Skew: -0.408ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.703ns + Source Clock Delay (SCD): -2.295ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.533 -2.295 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK + SLICE_X88Y131 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X88Y131 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.217 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/O + net (fo=1, routed) 0.453 -0.764 u_Axi_CDC/wFifo/_zz_ram_port10__0[10] + SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.639 -2.703 u_Axi_CDC/wFifo/sys_clk + SLICE_X87Y131 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.542ns (logic 1.056ns (68.461%) route 0.486ns (31.539%)) + Logic Levels: 0 + Clock Path Skew: -0.393ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.304ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.524 -2.304 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK + SLICE_X84Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y115 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.248 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.486 -0.761 u_Axi_CDC/awFifo/_zz_ram_port10[13] + SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/awFifo/sys_clk + SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.544ns (logic 1.059ns (68.591%) route 0.485ns (31.409%)) + Logic Levels: 0 + Clock Path Skew: -0.393ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.697ns + Source Clock Delay (SCD): -2.304ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.216ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.524 -2.304 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK + SLICE_X84Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X84Y115 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.245 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/O + net (fo=1, routed) 0.485 -0.760 u_Axi_CDC/awFifo/_zz_ram_port10[17] + SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/awFifo/sys_clk + SLICE_X84Y114 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: mlkem_clk + To Clock: sys_clk + +Max Delay 0 Endpoints +Min Delay 61 Endpoints +-------------------------------------------------------------------------------------- + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.636ns (logic 0.367ns (57.746%) route 0.269ns (42.254%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.367 -1.755 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.269 -1.487 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.633ns (logic 0.367ns (57.963%) route 0.266ns (42.037%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.499ns + Source Clock Delay (SCD): -2.113ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 -2.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk + SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.266 -1.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[1] + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.637ns (logic 0.367ns (57.593%) route 0.270ns (42.407%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X20Y55 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X20Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -0.930 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/O + net (fo=1, routed) 0.281 -0.649 u_Axi_CDC/awFifo/_zz_ram_port10[46] + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/D +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.367 -1.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.270 -1.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.359ns (logic 1.083ns (79.691%) route 0.276ns (20.309%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28942,14 +39222,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.941 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/O - net (fo=1, routed) 0.428 -0.514 u_Axi_CDC/arFifo/_zz_ram_port10__1[2] - SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D + SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -0.924 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/O + net (fo=1, routed) 0.276 -0.648 u_Axi_CDC/arFifo/_zz_ram_port10__1[32] + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28961,21 +39241,1313 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.935 -2.407 u_Axi_CDC/arFifo/sys_clk - SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/C + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.504ns (logic 1.059ns (70.415%) route 0.445ns (29.585%)) + Data Path Delay: 1.364ns (logic 1.083ns (79.398%) route 0.281ns (20.602%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.396ns + Source Clock Delay (SCD): -2.008ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X20Y55 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X20Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -0.925 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/O + net (fo=1, routed) 0.281 -0.644 u_Axi_CDC/awFifo/_zz_ram_port10[44] + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.364ns (logic 1.084ns (79.446%) route 0.280ns (20.554%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.008ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK + SLICE_X18Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y57 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -0.924 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/O + net (fo=1, routed) 0.280 -0.644 u_Axi_CDC/awFifo/_zz_ram_port10[48] + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.475ns (logic 1.059ns (71.806%) route 0.416ns (28.194%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.049 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/O + net (fo=1, routed) 0.416 -0.633 u_Axi_CDC/arFifo/_zz_ram_port10__1[11] + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.375ns (logic 1.084ns (78.853%) route 0.291ns (21.147%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -0.923 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/O + net (fo=1, routed) 0.291 -0.633 u_Axi_CDC/arFifo/_zz_ram_port10__1[30] + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/C +======= + net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C +>>>>>>> Stashed changes + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) +<<<<<<< Updated upstream + Data Path Delay: 1.484ns (logic 1.083ns (72.970%) route 0.401ns (27.030%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns +======= + Data Path Delay: 0.682ns (logic 0.418ns (61.266%) route 0.264ns (38.734%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.514ns + Source Clock Delay (SCD): -2.127ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y51 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.025 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/O + net (fo=1, routed) 0.401 -0.624 u_Axi_CDC/arFifo/_zz_ram_port10__1[2] + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.701 -2.127 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y97 FDCE (Prop_fdce_C_Q) 0.418 -1.709 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.264 -1.445 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.484ns (logic 1.083ns (72.970%) route 0.401ns (27.030%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns +======= + net (fo=9971, routed) 1.828 -2.514 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.684ns (logic 0.418ns (61.086%) route 0.266ns (38.914%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.514ns + Source Clock Delay (SCD): -2.127ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.701 -2.127 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y97 FDCE (Prop_fdce_C_Q) 0.418 -1.709 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.266 -1.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[1] + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.828 -2.514 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.730ns (logic 0.337ns (46.159%) route 0.393ns (53.841%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.499ns + Source Clock Delay (SCD): -2.113ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 -2.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk + SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.337 -1.776 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.393 -1.383 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.750ns (logic 0.367ns (48.935%) route 0.383ns (51.065%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.367 -1.755 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=3, routed) 0.383 -1.372 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2] + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.770ns (logic 0.367ns (47.632%) route 0.403ns (52.368%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.402ns - Source Clock Delay (SCD): -2.013ns + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns +>>>>>>> Stashed changes + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.025 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/O + net (fo=1, routed) 0.401 -0.624 u_Axi_CDC/arFifo/_zz_ram_port10__1[8] + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.367 -1.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/Q + net (fo=1, routed) 0.403 -1.350 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[1] + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.389ns (logic 1.084ns (78.063%) route 0.305ns (21.937%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.394ns + Source Clock Delay (SCD): -2.006ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.776ns (logic 0.337ns (43.419%) route 0.439ns (56.581%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.337 -1.785 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=5, routed) 0.439 -1.346 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.792ns (logic 0.367ns (46.358%) route 0.425ns (53.642%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock cpu_clk rise edge) 0.000 0.000 r +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X16Y50 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y50 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -0.922 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/O + net (fo=1, routed) 0.305 -0.618 u_Axi_CDC/arFifo/_zz_ram_port10__1[42] + SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.367 -1.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.425 -1.324 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.948 -2.394 u_Axi_CDC/arFifo/sys_clk + SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.463ns (logic 1.084ns (74.106%) route 0.379ns (25.894%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.396ns + Source Clock Delay (SCD): -2.008ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.837ns (logic 0.418ns (49.937%) route 0.419ns (50.063%)) + Logic Levels: 0 + Clock Path Skew: -0.391ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.514ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk + SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X72Y96 FDCE (Prop_fdce_C_Q) 0.418 -1.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.419 -1.285 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.828 -2.514 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk + SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.844ns (logic 0.367ns (43.474%) route 0.477ns (56.526%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.367 -1.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.477 -1.276 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[0] + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.848ns (logic 0.337ns (39.750%) route 0.511ns (60.250%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.337 -1.783 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.511 -1.272 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.044ns (logic 0.367ns (35.163%) route 0.677ns (64.837%)) + Logic Levels: 0 + Clock Path Skew: -0.393ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.670ns + Source Clock Delay (SCD): -2.277ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.551 -2.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk + SLICE_X93Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X93Y102 FDCE (Prop_fdce_C_Q) 0.367 -1.910 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q + net (fo=2, routed) 0.677 -1.233 u_fft_mlkem_axi_slave/mlkem_intr_m + SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.672 -2.670 u_fft_mlkem_axi_slave/sys_clk + SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.902ns (logic 0.367ns (40.694%) route 0.535ns (59.306%)) + Logic Levels: 0 + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.509ns + Source Clock Delay (SCD): -2.120ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk + SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.367 -1.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.535 -1.218 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[3] + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk + SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.908ns (logic 0.367ns (40.413%) route 0.541ns (59.587%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.115ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock cpu_clk rise edge) 0.000 0.000 r +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X20Y55 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X20Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -0.924 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/O + net (fo=1, routed) 0.379 -0.546 u_Axi_CDC/awFifo/_zz_ram_port10[42] + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk + SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.367 -1.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.541 -1.207 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[1] + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.480ns (logic 1.078ns (72.829%) route 0.402ns (27.171%)) + Logic Levels: 0 + Clock Path Skew: -0.382ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.405ns + Source Clock Delay (SCD): -2.022ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk + SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.925ns (logic 0.367ns (39.693%) route 0.558ns (60.307%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.499ns + Source Clock Delay (SCD): -2.113ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.715 -2.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk + SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.558 -1.189 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk + SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.985ns (logic 0.367ns (37.277%) route 0.618ns (62.723%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.507ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk + SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.367 -1.755 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.618 -1.138 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk + SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.240ns (logic 1.078ns (86.936%) route 0.162ns (13.064%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.112ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock cpu_clk rise edge) 0.000 0.000 r +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.806 -2.022 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK + SLICE_X36Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y56 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -0.944 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/O + net (fo=1, routed) 0.402 -0.542 u_Axi_CDC/awFifo/_zz_ram_port10[40] + SLICE_X35Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/D +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK + SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X52Y90 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.034 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O + net (fo=1, routed) 0.162 -0.872 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] + SLICE_X53Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.937 -2.405 u_Axi_CDC/awFifo/sys_clk + SLICE_X35Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.571ns (logic 1.059ns (67.419%) route 0.512ns (32.581%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk + SLICE_X53Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.467ns (logic 1.062ns (72.369%) route 0.405ns (27.631%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.502ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock cpu_clk rise edge) 0.000 0.000 r +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y51 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.049 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/O + net (fo=1, routed) 0.512 -0.537 u_Axi_CDC/arFifo/_zz_ram_port10__1[5] + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.055 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O + net (fo=1, routed) 0.405 -0.650 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.576ns (logic 1.062ns (67.383%) route 0.514ns (32.617%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28993,14 +40565,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK - SLICE_X16Y65 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.954 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/O - net (fo=1, routed) 0.445 -0.509 u_Axi_CDC/awFifo/_zz_ram_port10[41] - SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D + SLICE_X44Y51 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.046 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/O + net (fo=1, routed) 0.514 -0.532 u_Axi_CDC/arFifo/_zz_ram_port10__1[3] + SLICE_X45Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -29012,8 +40584,1923 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.940 -2.402 u_Axi_CDC/awFifo/sys_clk - SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/C + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.482ns (logic 1.078ns (72.759%) route 0.404ns (27.241%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.394ns + Source Clock Delay (SCD): -2.006ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X16Y50 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y50 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -0.928 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/O + net (fo=1, routed) 0.404 -0.525 u_Axi_CDC/arFifo/_zz_ram_port10__1[46] + SLICE_X15Y50 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.948 -2.394 u_Axi_CDC/arFifo/sys_clk + SLICE_X15Y50 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.488ns (logic 1.059ns (71.167%) route 0.429ns (28.833%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -0.948 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/O + net (fo=1, routed) 0.429 -0.519 u_Axi_CDC/arFifo/_zz_ram_port10__1[35] + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.493ns (logic 1.062ns (71.119%) route 0.431ns (28.881%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.396ns + Source Clock Delay (SCD): -2.008ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X20Y55 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X20Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -0.946 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/O + net (fo=1, routed) 0.431 -0.515 u_Axi_CDC/awFifo/_zz_ram_port10[45] + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D +======= + net (fo=9971, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D +>>>>>>> Stashed changes + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.492ns (logic 1.083ns (72.568%) route 0.409ns (27.432%)) + Logic Levels: 0 +<<<<<<< Updated upstream + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.394ns + Source Clock Delay (SCD): -2.006ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.502ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock cpu_clk rise edge) 0.000 0.000 r +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X16Y50 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y50 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -0.923 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/O + net (fo=1, routed) 0.409 -0.514 u_Axi_CDC/arFifo/_zz_ram_port10__1[44] + SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.034 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O + net (fo=1, routed) 0.409 -0.625 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.948 -2.394 u_Axi_CDC/arFifo/sys_clk + SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.597ns (logic 1.062ns (66.517%) route 0.535ns (33.483%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + net (fo=9971, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.506ns (logic 1.083ns (71.903%) route 0.423ns (28.097%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.118ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock cpu_clk rise edge) 0.000 0.000 r +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.046 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/O + net (fo=1, routed) 0.535 -0.512 u_Axi_CDC/arFifo/_zz_ram_port10__1[9] + SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.710 -2.118 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.035 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O + net (fo=1, routed) 0.423 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] + SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.601ns (logic 1.056ns (65.965%) route 0.545ns (34.035%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.496ns + Source Clock Delay (SCD): -2.109ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.593ns (logic 1.056ns (66.281%) route 0.537ns (33.719%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.118ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock cpu_clk rise edge) 0.000 0.000 r +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.719 -2.109 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X44Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y54 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.053 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.545 -0.508 u_Axi_CDC/arFifo/_zz_ram_port10__1[13] + SLICE_X43Y55 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.710 -2.118 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O + net (fo=1, routed) 0.537 -0.525 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] + SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.846 -2.496 u_Axi_CDC/arFifo/sys_clk + SLICE_X43Y55 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.601ns (logic 1.084ns (67.687%) route 0.517ns (32.313%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.109ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.612ns (logic 1.084ns (67.246%) route 0.528ns (32.754%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.118ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock cpu_clk rise edge) 0.000 0.000 r +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.719 -2.109 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X44Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y54 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.025 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/O + net (fo=1, routed) 0.517 -0.508 u_Axi_CDC/arFifo/_zz_ram_port10__1[12] + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.710 -2.118 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.034 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O + net (fo=1, routed) 0.528 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] + SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.601ns (logic 1.084ns (67.690%) route 0.517ns (32.310%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns +======= + net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.616ns (logic 1.078ns (66.728%) route 0.538ns (33.272%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.502ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns +>>>>>>> Stashed changes + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + (clock cpu_clk rise edge) 0.000 0.000 r +======= + (clock mlkem_clk rise edge) + 0.000 0.000 r +>>>>>>> Stashed changes + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll +<<<<<<< Updated upstream + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y51 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.024 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/O + net (fo=1, routed) 0.517 -0.507 u_Axi_CDC/arFifo/_zz_ram_port10__1[0] + SLICE_X44Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D +======= + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.039 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O + net (fo=1, routed) 0.538 -0.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X44Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/C +======= + net (fo=9971, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.651ns (logic 1.062ns (64.315%) route 0.589ns (35.685%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.503ns + Source Clock Delay (SCD): -2.118ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.710 -2.118 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y90 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.056 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O + net (fo=1, routed) 0.589 -0.467 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] + SLICE_X65Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X65Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.709ns (logic 1.059ns (61.956%) route 0.650ns (38.044%)) + Logic Levels: 0 + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.502ns + Source Clock Delay (SCD): -2.117ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.058 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O + net (fo=1, routed) 0.650 -0.408 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.843ns (logic 1.059ns (57.448%) route 0.784ns (42.552%)) + Logic Levels: 0 + Clock Path Skew: -0.375ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.063 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O + net (fo=1, routed) 0.784 -0.279 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.871ns (logic 1.056ns (56.445%) route 0.815ns (43.555%)) + Logic Levels: 0 + Clock Path Skew: -0.375ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.497ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.065 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.815 -0.250 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.874ns (logic 1.062ns (56.680%) route 0.812ns (43.320%)) + Logic Levels: 0 + Clock Path Skew: -0.375ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.060 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O + net (fo=1, routed) 0.812 -0.249 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.875ns (logic 1.056ns (56.314%) route 0.819ns (43.686%)) + Logic Levels: 0 + Clock Path Skew: -0.376ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.065 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 0.819 -0.246 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.901ns (logic 1.059ns (55.705%) route 0.842ns (44.295%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.501ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.063 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O + net (fo=1, routed) 0.842 -0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.841 -2.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.902ns (logic 1.083ns (56.944%) route 0.819ns (43.056%)) + Logic Levels: 0 + Clock Path Skew: -0.375ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.497ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.038 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O + net (fo=1, routed) 0.819 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.920ns (logic 1.083ns (56.420%) route 0.837ns (43.580%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.501ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.039 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/O + net (fo=1, routed) 0.837 -0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[14] + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.841 -2.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.937ns (logic 1.083ns (55.902%) route 0.854ns (44.098%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.501ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.039 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O + net (fo=1, routed) 0.854 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.841 -2.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.959ns (logic 1.059ns (54.058%) route 0.900ns (45.942%)) + Logic Levels: 0 + Clock Path Skew: -0.376ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O + net (fo=1, routed) 0.900 -0.162 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.974ns (logic 1.059ns (53.657%) route 0.915ns (46.343%)) + Logic Levels: 0 + Clock Path Skew: -0.376ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O + net (fo=1, routed) 0.915 -0.148 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.976ns (logic 1.078ns (54.551%) route 0.898ns (45.449%)) + Logic Levels: 0 + Clock Path Skew: -0.375ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.044 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O + net (fo=1, routed) 0.898 -0.146 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.981ns (logic 1.083ns (54.682%) route 0.898ns (45.318%)) + Logic Levels: 0 + Clock Path Skew: -0.375ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.497ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.038 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O + net (fo=1, routed) 0.898 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.984ns (logic 1.056ns (53.233%) route 0.928ns (46.767%)) + Logic Levels: 0 + Clock Path Skew: -0.375ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.066 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O + net (fo=1, routed) 0.928 -0.139 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.988ns (logic 1.062ns (53.409%) route 0.926ns (46.591%)) + Logic Levels: 0 + Clock Path Skew: -0.376ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.059 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O + net (fo=1, routed) 0.926 -0.133 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.996ns (logic 1.056ns (52.902%) route 0.940ns (47.098%)) + Logic Levels: 0 + Clock Path Skew: -0.375ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.066 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 0.940 -0.126 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.999ns (logic 1.062ns (53.120%) route 0.937ns (46.880%)) + Logic Levels: 0 + Clock Path Skew: -0.375ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.497ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.059 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O + net (fo=1, routed) 0.937 -0.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27] + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.845 -2.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.000ns (logic 1.062ns (53.096%) route 0.938ns (46.904%)) + Logic Levels: 0 + Clock Path Skew: -0.376ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.059 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O + net (fo=1, routed) 0.938 -0.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.001ns (logic 1.078ns (53.864%) route 0.923ns (46.136%)) + Logic Levels: 0 + Clock Path Skew: -0.375ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.044 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O + net (fo=1, routed) 0.923 -0.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.011ns (logic 1.084ns (53.891%) route 0.927ns (46.109%)) + Logic Levels: 0 + Clock Path Skew: -0.376ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.037 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.927 -0.110 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.019ns (logic 1.084ns (53.691%) route 0.935ns (46.309%)) + Logic Levels: 0 + Clock Path Skew: -0.375ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.122ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.038 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 0.935 -0.103 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.020ns (logic 1.083ns (53.627%) route 0.937ns (46.373%)) + Logic Levels: 0 + Clock Path Skew: -0.376ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.038 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O + net (fo=1, routed) 0.937 -0.102 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2] + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.031ns (logic 1.084ns (53.380%) route 0.947ns (46.620%)) + Logic Levels: 0 + Clock Path Skew: -0.376ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.037 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 0.947 -0.091 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C + +Slack: inf + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.081ns (logic 1.056ns (50.757%) route 1.025ns (49.243%)) + Logic Levels: 0 + Clock Path Skew: -0.376ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.498ns + Source Clock Delay (SCD): -2.121ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mlkem_clk rise edge) + 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O + net (fo=17272, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.065 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 1.025 -0.041 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk + SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/C +>>>>>>> Stashed changes @@ -29039,10 +42526,10 @@ Slack: inf Path Type: Min at Slow Process Corner Data Path Delay: 3.498ns (logic 0.091ns (2.602%) route 3.407ns (97.398%)) Logic Levels: 1 (BUFG=1) - Clock Uncertainty: 0.169ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.225ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.075ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.110ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -29056,7 +42543,7 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/clkfbout_clk_pll - BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkf_buf/O + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkf_buf/O net (fo=1, routed) 1.652 -2.177 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN ------------------------------------------------------------------- ------------------- @@ -29086,10 +42573,10 @@ Slack: inf Path Type: Min at Fast Process Corner Data Path Delay: 2.614ns (logic 1.260ns (48.196%) route 1.354ns (51.804%)) Logic Levels: 2 (BUFG=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -29103,20 +42590,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.794 -0.468 video_clk_OBUF +<<<<<<< Updated upstream + net (fo=35652, routed) 0.794 -0.468 video_clk_OBUF +======= + net (fo=9971, routed) 0.794 -0.468 video_clk_OBUF +>>>>>>> Stashed changes H22 OBUF (Prop_obuf_I_O) 1.234 0.766 r video_clk_OBUF_inst/O net (fo=0) 0.000 0.766 video_clk H22 r video_clk (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[0]_lopt_replica/C +<<<<<<< Updated upstream + Source: u_confreg/led_data_reg[15]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[0] + Destination: leds[15] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.665ns (logic 1.416ns (53.147%) route 1.249ns (46.853%)) + Data Path Delay: 2.765ns (logic 1.404ns (50.799%) route 1.360ns (49.201%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29134,24 +42626,24 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y96 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C + net (fo=35652, routed) 0.721 -0.541 u_confreg/sys_clk + SLICE_X0Y84 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[0]_lopt_replica/Q - net (fo=1, routed) 1.249 0.852 lopt - B24 OBUF (Prop_obuf_I_O) 1.275 2.128 r leds_OBUF[0]_inst/O - net (fo=0) 0.000 2.128 leds[0] - B24 r leds[0] (OUT) + SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[15]_lopt_replica/Q + net (fo=1, routed) 1.360 0.960 lopt_6 + B20 OBUF (Prop_obuf_I_O) 1.263 2.223 r leds_OBUF[15]_inst/O + net (fo=0) 0.000 2.223 leds[15] + B20 r leds[15] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[1]_lopt_replica/C + Source: u_confreg/led_data_reg[12]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[1] + Destination: leds[12] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.771ns (logic 1.383ns (49.914%) route 1.388ns (50.086%)) + Data Path Delay: 2.814ns (logic 1.384ns (49.180%) route 1.430ns (50.820%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29169,14 +42661,14 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C + net (fo=35652, routed) 0.721 -0.541 u_confreg/sys_clk + SLICE_X0Y85 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[1]_lopt_replica/Q - net (fo=1, routed) 1.388 0.992 lopt_7 - E21 OBUF (Prop_obuf_I_O) 1.242 2.234 r leds_OBUF[1]_inst/O - net (fo=0) 0.000 2.234 leds[1] - E21 r leds[1] (OUT) + SLICE_X0Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[12]_lopt_replica/Q + net (fo=1, routed) 1.430 1.030 lopt_3 + D20 OBUF (Prop_obuf_I_O) 1.243 2.273 r leds_OBUF[12]_inst/O + net (fo=0) 0.000 2.273 leds[12] + D20 r leds[12] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -29186,7 +42678,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.806ns (logic 1.454ns (51.806%) route 1.352ns (48.194%)) + Data Path Delay: 2.837ns (logic 1.414ns (49.822%) route 1.424ns (50.178%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29204,86 +42696,16 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C + net (fo=35652, routed) 0.718 -0.544 u_confreg/sys_clk + SLICE_X0Y81 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.128 -0.409 r u_confreg/led_data_reg[7]_lopt_replica/Q - net (fo=1, routed) 1.352 0.943 lopt_13 - B22 OBUF (Prop_obuf_I_O) 1.326 2.268 r leds_OBUF[7]_inst/O - net (fo=0) 0.000 2.268 leds[7] + SLICE_X0Y81 FDRE (Prop_fdre_C_Q) 0.141 -0.403 r u_confreg/led_data_reg[7]_lopt_replica/Q + net (fo=1, routed) 1.424 1.020 lopt_13 + B22 OBUF (Prop_obuf_I_O) 1.273 2.293 r leds_OBUF[7]_inst/O + net (fo=0) 0.000 2.293 leds[7] B22 r leds[7] (OUT) ------------------------------------------------------------------- ------------------- -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[7] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.807ns (logic 1.362ns (48.520%) route 1.445ns (51.480%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q - net (fo=1, routed) 1.445 1.050 dpy1_OBUF[7] - G17 OBUF (Prop_obuf_I_O) 1.221 2.271 r dpy1_OBUF[7]_inst/O - net (fo=0) 0.000 2.271 dpy1[7] - G17 r dpy1[7] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[13]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[13] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.809ns (logic 1.412ns (50.266%) route 1.397ns (49.734%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk - SLICE_X1Y98 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[13]_lopt_replica/Q - net (fo=1, routed) 1.397 1.002 lopt_4 - A22 OBUF (Prop_obuf_I_O) 1.271 2.273 r leds_OBUF[13]_inst/O - net (fo=0) 0.000 2.273 leds[13] - A22 r leds[13] (OUT) - ------------------------------------------------------------------- ------------------- - Slack: inf Source: u_confreg/led_data_reg[10]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -29291,7 +42713,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.819ns (logic 1.389ns (49.262%) route 1.430ns (50.738%)) + Data Path Delay: 2.845ns (logic 1.389ns (48.821%) route 1.456ns (51.179%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29309,24 +42731,24 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_confreg/sys_clk - SLICE_X0Y86 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C + net (fo=35652, routed) 0.718 -0.544 u_confreg/sys_clk + SLICE_X1Y81 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[10]_lopt_replica/Q - net (fo=1, routed) 1.430 1.030 lopt_1 - D21 OBUF (Prop_obuf_I_O) 1.248 2.278 r leds_OBUF[10]_inst/O - net (fo=0) 0.000 2.278 leds[10] + SLICE_X1Y81 FDRE (Prop_fdre_C_Q) 0.141 -0.403 r u_confreg/led_data_reg[10]_lopt_replica/Q + net (fo=1, routed) 1.456 1.052 lopt_1 + D21 OBUF (Prop_obuf_I_O) 1.248 2.300 r leds_OBUF[10]_inst/O + net (fo=0) 0.000 2.300 leds[10] D21 r leds[10] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[14]_lopt_replica/C + Source: u_confreg/led_data_reg[0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[14] + Destination: leds[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.815ns (logic 1.404ns (49.886%) route 1.411ns (50.114%)) + Data Path Delay: 2.867ns (logic 1.416ns (49.395%) route 1.451ns (50.605%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29344,25 +42766,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[14]_lopt_replica/Q - net (fo=1, routed) 1.411 1.014 lopt_5 - A20 OBUF (Prop_obuf_I_O) 1.263 2.278 r leds_OBUF[14]_inst/O - net (fo=0) 0.000 2.278 leds[14] - A20 r leds[14] (OUT) + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[0]_lopt_replica/Q + net (fo=1, routed) 1.451 1.053 lopt + B24 OBUF (Prop_obuf_I_O) 1.275 2.328 r leds_OBUF[0]_inst/O + net (fo=0) 0.000 2.328 leds[0] + B24 r leds[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C + Source: u_confreg/led_data_reg[4]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: UART_TX + Destination: leds[4] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.818ns (logic 1.033ns (36.656%) route 1.785ns (63.344%)) - Logic Levels: 2 (LUT3=1 OBUFT=1) + Data Path Delay: 2.934ns (logic 1.404ns (47.847%) route 1.530ns (52.153%)) + Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns @@ -29379,17 +42801,119 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C + net (fo=35652, routed) 0.715 -0.547 u_confreg/sys_clk + SLICE_X0Y78 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y60 FDRE (Prop_fdre_C_Q) 0.164 -0.375 r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/Q - net (fo=2, routed) 0.232 -0.143 u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en - SLICE_X3Y60 LUT3 (Prop_lut3_I0_O) 0.045 -0.098 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O - net (fo=1, routed) 1.553 1.455 UART_TX_IOBUF_inst/T - H18 OBUFT (TriStatD_obuft_T_O) - 0.824 2.279 r UART_TX_IOBUF_inst/OBUFT/O - net (fo=1, unset) 0.000 2.279 UART_TX - H18 r UART_TX (INOUT) + SLICE_X0Y78 FDRE (Prop_fdre_C_Q) 0.141 -0.406 r u_confreg/led_data_reg[4]_lopt_replica/Q + net (fo=1, routed) 1.530 1.124 lopt_10 + C22 OBUF (Prop_obuf_I_O) 1.263 2.386 r leds_OBUF[4]_inst/O + net (fo=0) 0.000 2.386 leds[4] + C22 r leds[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[6]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[6] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.974ns (logic 1.383ns (46.512%) route 1.591ns (53.488%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.715 -0.547 u_confreg/sys_clk + SLICE_X0Y78 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y78 FDRE (Prop_fdre_C_Q) 0.141 -0.406 r u_confreg/led_data_reg[6]_lopt_replica/Q + net (fo=1, routed) 1.591 1.185 lopt_12 + E20 OBUF (Prop_obuf_I_O) 1.242 2.427 r leds_OBUF[6]_inst/O + net (fo=0) 0.000 2.427 leds[6] + E20 r leds[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[11]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[11] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.976ns (logic 1.408ns (47.324%) route 1.568ns (52.676%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[11]_lopt_replica/Q + net (fo=1, routed) 1.568 1.169 lopt_2 + A18 OBUF (Prop_obuf_I_O) 1.267 2.436 r leds_OBUF[11]_inst/O + net (fo=0) 0.000 2.436 leds[11] + A18 r leds[11] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[5] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.051ns (logic 1.388ns (45.475%) route 1.664ns (54.525%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q + net (fo=1, routed) 1.664 1.267 dpy0_OBUF[5] + C19 OBUF (Prop_obuf_I_O) 1.247 2.514 r dpy0_OBUF[5]_inst/O + net (fo=0) 0.000 2.514 dpy0[5] + C19 r dpy0[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -29399,7 +42923,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.902ns (logic 0.965ns (33.253%) route 1.937ns (66.747%)) + Data Path Delay: 2.985ns (logic 0.965ns (32.328%) route 2.020ns (67.672%)) Logic Levels: 1 (OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29417,25 +42941,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_axi_uart_controller/uart0/regs/sys_clk - SLICE_X9Y67 FDSE r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C + net (fo=35652, routed) 0.795 -0.468 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X3Y39 FDSE r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X9Y67 FDSE (Prop_fdse_C_Q) 0.141 -0.432 r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/Q - net (fo=28, routed) 1.937 1.505 UART_RX_IOBUF_inst/T + SLICE_X3Y39 FDSE (Prop_fdse_C_Q) 0.141 -0.327 r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/Q + net (fo=28, routed) 2.020 1.693 UART_RX_IOBUF_inst/T J20 OBUFT (TriStatD_obuft_T_O) - 0.824 2.329 r UART_RX_IOBUF_inst/OBUFT/O - net (fo=1, unset) 0.000 2.329 UART_RX + 0.824 2.517 r UART_RX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 2.517 UART_RX J20 r UART_RX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[0] + Source: u_confreg/led_data_reg[5]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[5] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.872ns (logic 1.407ns (48.983%) route 1.465ns (51.017%)) + Data Path Delay: 3.109ns (logic 1.435ns (46.158%) route 1.674ns (53.842%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29453,25 +42977,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q - net (fo=1, routed) 1.465 1.070 dpy1_OBUF[0] - A17 OBUF (Prop_obuf_I_O) 1.266 2.336 r dpy1_OBUF[0]_inst/O - net (fo=0) 0.000 2.336 dpy1[0] - A17 r dpy1[0] (OUT) + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r u_confreg/led_data_reg[5]_lopt_replica/Q + net (fo=1, routed) 1.674 1.263 lopt_11 + C21 OBUF (Prop_obuf_I_O) 1.307 2.570 r leds_OBUF[5]_inst/O + net (fo=0) 0.000 2.570 leds[5] + C21 r leds[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[5] + Source: u_axi_uart_controller/uart0/regs/transmitter/stx_o_tmp_reg/C + (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: UART_TX (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.877ns (logic 1.376ns (47.814%) route 1.502ns (52.186%)) - Logic Levels: 1 (OBUF=1) + Data Path Delay: 3.056ns (logic 1.416ns (46.332%) route 1.640ns (53.668%)) + Logic Levels: 2 (LUT4=1 OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns @@ -29488,24 +43012,26 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + net (fo=35652, routed) 0.796 -0.467 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X0Y41 FDSE r u_axi_uart_controller/uart0/regs/transmitter/stx_o_tmp_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q - net (fo=1, routed) 1.502 1.106 dpy1_OBUF[5] - G16 OBUF (Prop_obuf_I_O) 1.235 2.341 r dpy1_OBUF[5]_inst/O - net (fo=0) 0.000 2.341 dpy1[5] - G16 r dpy1[5] (OUT) + SLICE_X0Y41 FDSE (Prop_fdse_C_Q) 0.141 -0.326 r u_axi_uart_controller/uart0/regs/transmitter/stx_o_tmp_reg/Q + net (fo=5, routed) 0.136 -0.189 u_axi_uart_controller/uart0/regs/transmitter/stx_o_tmp_reg_0 + SLICE_X0Y40 LUT4 (Prop_lut4_I1_O) 0.045 -0.144 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_1/O + net (fo=1, routed) 1.504 1.360 UART_TX_IOBUF_inst/I + H18 OBUFT (Prop_obuft_I_O) 1.230 2.590 r UART_TX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 2.590 UART_TX + H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[7] + Destination: dpy0[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.946ns (logic 1.386ns (47.054%) route 1.560ns (52.946%)) + Data Path Delay: 3.150ns (logic 1.400ns (44.449%) route 1.750ns (55.551%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29523,24 +43049,24 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q - net (fo=1, routed) 1.560 1.096 dpy0_OBUF[7] - C17 OBUF (Prop_obuf_I_O) 1.245 2.341 r dpy0_OBUF[7]_inst/O - net (fo=0) 0.000 2.341 dpy0[7] - C17 r dpy0[7] (OUT) + SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q + net (fo=1, routed) 1.750 1.353 dpy0_OBUF[2] + B21 OBUF (Prop_obuf_I_O) 1.259 2.612 r dpy0_OBUF[2]_inst/O + net (fo=0) 0.000 2.612 dpy0[2] + B21 r dpy0[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[6] + Destination: dpy0[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.958ns (logic 1.398ns (47.262%) route 1.560ns (52.738%)) + Data Path Delay: 3.168ns (logic 1.402ns (44.239%) route 1.767ns (55.761%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29558,14 +43084,119 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q - net (fo=1, routed) 1.560 1.096 dpy0_OBUF[6] - B17 OBUF (Prop_obuf_I_O) 1.257 2.353 r dpy0_OBUF[6]_inst/O - net (fo=0) 0.000 2.353 dpy0[6] - B17 r dpy0[6] (OUT) + SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q + net (fo=1, routed) 1.767 1.370 dpy0_OBUF[0] + B19 OBUF (Prop_obuf_I_O) 1.261 2.631 r dpy0_OBUF[0]_inst/O + net (fo=0) 0.000 2.631 dpy0[0] + B19 r dpy0[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[3] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.170ns (logic 1.415ns (44.629%) route 1.755ns (55.371%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q + net (fo=1, routed) 1.755 1.359 dpy0_OBUF[3] + A19 OBUF (Prop_obuf_I_O) 1.274 2.632 r dpy0_OBUF[3]_inst/O + net (fo=0) 0.000 2.632 dpy0[3] + A19 r dpy0[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[6] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.175ns (logic 1.379ns (43.433%) route 1.796ns (56.567%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q + net (fo=1, routed) 1.796 1.398 dpy1_OBUF[6] + F15 OBUF (Prop_obuf_I_O) 1.238 2.636 r dpy1_OBUF[6]_inst/O + net (fo=0) 0.000 2.636 dpy1[6] + F15 r dpy1[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[3]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[3] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.180ns (logic 1.444ns (45.406%) route 1.736ns (54.594%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r u_confreg/led_data_reg[3]_lopt_replica/Q + net (fo=1, routed) 1.736 1.324 lopt_9 + D23 OBUF (Prop_obuf_I_O) 1.316 2.640 r leds_OBUF[3]_inst/O + net (fo=0) 0.000 2.640 leds[3] + D23 r leds[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -29575,7 +43206,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.927ns (logic 1.391ns (47.509%) route 1.537ns (52.491%)) + Data Path Delay: 3.210ns (logic 1.391ns (43.329%) route 1.819ns (56.671%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29593,13 +43224,13 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q - net (fo=1, routed) 1.537 1.141 dpy1_OBUF[1] - D16 OBUF (Prop_obuf_I_O) 1.250 2.391 r dpy1_OBUF[1]_inst/O - net (fo=0) 0.000 2.391 dpy1[1] + SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q + net (fo=1, routed) 1.819 1.422 dpy1_OBUF[1] + D16 OBUF (Prop_obuf_I_O) 1.250 2.671 r dpy1_OBUF[1]_inst/O + net (fo=0) 0.000 2.671 dpy1[1] D16 r dpy1[1] (OUT) ------------------------------------------------------------------- ------------------- @@ -29610,7 +43241,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.966ns (logic 1.383ns (46.637%) route 1.583ns (53.363%)) + Data Path Delay: 3.257ns (logic 1.383ns (42.471%) route 1.874ns (57.529%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29628,24 +43259,24 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q - net (fo=1, routed) 1.583 1.188 dpy1_OBUF[4] - E16 OBUF (Prop_obuf_I_O) 1.242 2.430 r dpy1_OBUF[4]_inst/O - net (fo=0) 0.000 2.430 dpy1[4] + SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q + net (fo=1, routed) 1.874 1.476 dpy1_OBUF[4] + E16 OBUF (Prop_obuf_I_O) 1.242 2.719 r dpy1_OBUF[4]_inst/O + net (fo=0) 0.000 2.719 dpy1[4] E16 r dpy1[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[3] + Destination: dpy1[3] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.046ns (logic 1.415ns (46.436%) route 1.632ns (53.564%)) + Data Path Delay: 3.258ns (logic 1.356ns (41.632%) route 1.902ns (58.368%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29663,119 +43294,14 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q - net (fo=1, routed) 1.632 1.168 dpy0_OBUF[3] - A19 OBUF (Prop_obuf_I_O) 1.274 2.441 r dpy0_OBUF[3]_inst/O - net (fo=0) 0.000 2.441 dpy0[3] - A19 r dpy0[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[12]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[12] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.006ns (logic 1.384ns (46.047%) route 1.622ns (53.953%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_confreg/sys_clk - SLICE_X3Y89 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[12]_lopt_replica/Q - net (fo=1, routed) 1.622 1.223 lopt_3 - D20 OBUF (Prop_obuf_I_O) 1.243 2.467 r leds_OBUF[12]_inst/O - net (fo=0) 0.000 2.467 leds[12] - D20 r leds[12] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[0] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.083ns (logic 1.402ns (45.458%) route 1.682ns (54.542%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q - net (fo=1, routed) 1.682 1.218 dpy0_OBUF[0] - B19 OBUF (Prop_obuf_I_O) 1.261 2.478 r dpy0_OBUF[0]_inst/O - net (fo=0) 0.000 2.478 dpy0[0] - B19 r dpy0[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[6] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.165ns (logic 1.379ns (43.565%) route 1.786ns (56.435%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q - net (fo=1, routed) 1.786 1.391 dpy1_OBUF[6] - F15 OBUF (Prop_obuf_I_O) 1.238 2.629 r dpy1_OBUF[6]_inst/O - net (fo=0) 0.000 2.629 dpy1[6] - F15 r dpy1[6] (OUT) + SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q + net (fo=1, routed) 1.902 1.504 dpy1_OBUF[3] + F17 OBUF (Prop_obuf_I_O) 1.215 2.719 r dpy1_OBUF[3]_inst/O + net (fo=0) 0.000 2.719 dpy1[3] + F17 r dpy1[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -29785,7 +43311,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.248ns (logic 1.387ns (42.702%) route 1.861ns (57.298%)) + Data Path Delay: 3.344ns (logic 1.387ns (41.472%) route 1.957ns (58.528%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29803,94 +43329,24 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q - net (fo=1, routed) 1.861 1.397 dpy0_OBUF[1] - D19 OBUF (Prop_obuf_I_O) 1.246 2.643 r dpy0_OBUF[1]_inst/O - net (fo=0) 0.000 2.643 dpy0[1] + SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q + net (fo=1, routed) 1.957 1.561 dpy0_OBUF[1] + D19 OBUF (Prop_obuf_I_O) 1.246 2.807 r dpy0_OBUF[1]_inst/O + net (fo=0) 0.000 2.807 dpy0[1] D19 r dpy0[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[5] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.258ns (logic 1.388ns (42.591%) route 1.870ns (57.409%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q - net (fo=1, routed) 1.870 1.406 dpy0_OBUF[5] - C19 OBUF (Prop_obuf_I_O) 1.247 2.653 r dpy0_OBUF[5]_inst/O - net (fo=0) 0.000 2.653 dpy0[5] - C19 r dpy0[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[2] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.236ns (logic 1.383ns (42.747%) route 1.853ns (57.253%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q - net (fo=1, routed) 1.853 1.457 dpy1_OBUF[2] - E17 OBUF (Prop_obuf_I_O) 1.242 2.700 r dpy1_OBUF[2]_inst/O - net (fo=0) 0.000 2.700 dpy1[2] - E17 r dpy1[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[6]_lopt_replica/C + Source: u_confreg/led_data_reg[14]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[6] + Destination: leds[14] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.273ns (logic 1.423ns (43.486%) route 1.850ns (56.514%)) + Data Path Delay: 3.393ns (logic 1.404ns (41.392%) route 1.989ns (58.608%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29908,24 +43364,133 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.128 -0.409 r u_confreg/led_data_reg[6]_lopt_replica/Q - net (fo=1, routed) 1.850 1.440 lopt_12 - E20 OBUF (Prop_obuf_I_O) 1.295 2.736 r leds_OBUF[6]_inst/O - net (fo=0) 0.000 2.736 leds[6] - E20 r leds[6] (OUT) + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[14]_lopt_replica/Q + net (fo=1, routed) 1.989 1.590 lopt_5 + A20 OBUF (Prop_obuf_I_O) 1.263 2.854 r leds_OBUF[14]_inst/O + net (fo=0) 0.000 2.854 leds[14] + A20 r leds[14] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[11]_lopt_replica/C + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[6] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.619ns (logic 1.398ns (38.631%) route 2.221ns (61.369%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q + net (fo=1, routed) 2.221 1.825 dpy0_OBUF[6] + B17 OBUF (Prop_obuf_I_O) 1.257 3.082 r dpy0_OBUF[6]_inst/O + net (fo=0) 0.000 3.082 dpy0[6] + B17 r dpy0[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.636ns (logic 1.407ns (38.697%) route 2.229ns (61.303%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q + net (fo=1, routed) 2.229 1.831 dpy1_OBUF[0] + A17 OBUF (Prop_obuf_I_O) 1.266 3.097 r dpy1_OBUF[0]_inst/O + net (fo=0) 0.000 3.097 dpy1[0] + A17 r dpy1[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[11] + Destination: video_vsync (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.362ns (logic 1.408ns (41.889%) route 1.954ns (58.111%)) + Data Path Delay: 3.669ns (logic 1.482ns (40.396%) route 2.187ns (59.604%)) + Logic Levels: 3 (LUT4=1 LUT6=1 OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.716 -0.546 u_axi_dvi/sys_clk + SLICE_X1Y79 FDRE r u_axi_dvi/vdata_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y79 FDRE (Prop_fdre_C_Q) 0.141 -0.405 r u_axi_dvi/vdata_reg[0]/Q + net (fo=13, routed) 0.170 -0.236 u_axi_dvi/vdata_reg_n_0_[0] + SLICE_X1Y79 LUT6 (Prop_lut6_I3_O) 0.045 -0.191 r u_axi_dvi/video_vsync_OBUF_inst_i_2/O + net (fo=1, routed) 0.189 -0.001 u_axi_dvi/video_vsync_OBUF_inst_i_2_n_0 + SLICE_X1Y80 LUT4 (Prop_lut4_I0_O) 0.045 0.044 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O + net (fo=1, routed) 1.828 1.872 video_vsync_OBUF + H24 OBUF (Prop_obuf_I_O) 1.251 3.123 r video_vsync_OBUF_inst/O + net (fo=0) 0.000 3.123 video_vsync + H24 r video_vsync (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[7] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.661ns (logic 1.386ns (37.869%) route 2.275ns (62.131%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29943,24 +43508,59 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y96 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[11]_lopt_replica/Q - net (fo=1, routed) 1.954 1.557 lopt_2 - A18 OBUF (Prop_obuf_I_O) 1.267 2.825 r leds_OBUF[11]_inst/O - net (fo=0) 0.000 2.825 leds[11] - A18 r leds[11] (OUT) + SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q + net (fo=1, routed) 2.275 1.878 dpy0_OBUF[7] + C17 OBUF (Prop_obuf_I_O) 1.245 3.124 r dpy0_OBUF[7]_inst/O + net (fo=0) 0.000 3.124 dpy0[7] + C17 r dpy0[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[4] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.691ns (logic 1.381ns (37.421%) route 2.309ns (62.579%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q + net (fo=1, routed) 2.309 1.913 dpy0_OBUF[4] + E18 OBUF (Prop_obuf_I_O) 1.240 3.153 r dpy0_OBUF[4]_inst/O + net (fo=0) 0.000 3.153 dpy0[4] + E18 r dpy0[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_de (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.419ns (logic 1.470ns (42.999%) route 1.949ns (57.001%)) + Data Path Delay: 3.778ns (logic 1.447ns (38.313%) route 2.330ns (61.687%)) Logic Levels: 2 (LUT6=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29978,18 +43578,188 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C + net (fo=35652, routed) 0.713 -0.549 u_axi_dvi/sys_clk + SLICE_X0Y76 FDRE r u_axi_dvi/vdata_reg[11]/C ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 f u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.247 -0.161 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X14Y86 LUT6 (Prop_lut6_I3_O) 0.045 -0.116 r u_axi_dvi/video_de_OBUF_inst_i_1/O - net (fo=1, routed) 1.702 1.586 video_de_OBUF - G24 OBUF (Prop_obuf_I_O) 1.261 2.847 r video_de_OBUF_inst/O - net (fo=0) 0.000 2.847 video_de + SLICE_X0Y76 FDRE (Prop_fdre_C_Q) 0.141 -0.408 f u_axi_dvi/vdata_reg[11]/Q + net (fo=11, routed) 0.358 -0.050 u_axi_dvi/vdata_reg_n_0_[11] + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.045 -0.005 r u_axi_dvi/video_de_OBUF_inst_i_1/O + net (fo=1, routed) 1.972 1.967 video_de_OBUF + G24 OBUF (Prop_obuf_I_O) 1.261 3.228 r video_de_OBUF_inst/O + net (fo=0) 0.000 3.228 video_de G24 r video_de (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[2] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.808ns (logic 1.383ns (36.327%) route 2.425ns (63.673%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q + net (fo=1, routed) 2.425 2.027 dpy1_OBUF[2] + E17 OBUF (Prop_obuf_I_O) 1.242 3.270 r dpy1_OBUF[2]_inst/O + net (fo=0) 0.000 3.270 dpy1[2] + E17 r dpy1[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[2] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.856ns (logic 1.671ns (43.330%) route 2.185ns (56.670%)) + Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.712 -0.550 u_axi_dvi/sys_clk + SLICE_X0Y74 FDRE r u_axi_dvi/vdata_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.409 r u_axi_dvi/vdata_reg[2]/Q + net (fo=12, routed) 0.241 -0.169 u_axi_dvi/vdata_reg_n_0_[2] + SLICE_X2Y73 LUT4 (Prop_lut4_I2_O) 0.047 -0.122 r u_axi_dvi/video_red_OBUF[2]_inst_i_53/O + net (fo=1, routed) 0.000 -0.122 u_axi_dvi/video_red_OBUF[2]_inst_i_53_n_0 + SLICE_X2Y73 CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.111 -0.011 r u_axi_dvi/video_red_OBUF[2]_inst_i_19/CO[3] + net (fo=1, routed) 0.000 -0.011 u_axi_dvi/video_red_OBUF[2]_inst_i_19_n_0 + SLICE_X2Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.040 0.029 r u_axi_dvi/video_red_OBUF[2]_inst_i_4/CO[3] + net (fo=1, routed) 0.222 0.252 u_axi_dvi/vdata1_in_range07_in + SLICE_X6Y74 LUT5 (Prop_lut5_I2_O) 0.045 0.297 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 1.722 2.019 video_red_OBUF[0] + E26 OBUF (Prop_obuf_I_O) 1.287 3.306 r video_red_OBUF[2]_inst/O + net (fo=0) 0.000 3.306 video_red[2] + E26 r video_red[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.955ns (logic 1.645ns (41.586%) route 2.310ns (58.414%)) + Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.712 -0.550 u_axi_dvi/sys_clk + SLICE_X0Y74 FDRE r u_axi_dvi/vdata_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.409 r u_axi_dvi/vdata_reg[2]/Q + net (fo=12, routed) 0.241 -0.169 u_axi_dvi/vdata_reg_n_0_[2] + SLICE_X2Y73 LUT4 (Prop_lut4_I2_O) 0.047 -0.122 r u_axi_dvi/video_red_OBUF[2]_inst_i_53/O + net (fo=1, routed) 0.000 -0.122 u_axi_dvi/video_red_OBUF[2]_inst_i_53_n_0 + SLICE_X2Y73 CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.111 -0.011 r u_axi_dvi/video_red_OBUF[2]_inst_i_19/CO[3] + net (fo=1, routed) 0.000 -0.011 u_axi_dvi/video_red_OBUF[2]_inst_i_19_n_0 + SLICE_X2Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.040 0.029 r u_axi_dvi/video_red_OBUF[2]_inst_i_4/CO[3] + net (fo=1, routed) 0.222 0.252 u_axi_dvi/vdata1_in_range07_in + SLICE_X6Y74 LUT5 (Prop_lut5_I2_O) 0.045 0.297 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 1.847 2.144 video_red_OBUF[0] + F24 OBUF (Prop_obuf_I_O) 1.261 3.405 r video_red_OBUF[1]_inst/O + net (fo=0) 0.000 3.405 video_red[1] + F24 r video_red[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.987ns (logic 1.617ns (40.568%) route 2.370ns (59.432%)) + Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.712 -0.550 u_axi_dvi/sys_clk + SLICE_X0Y74 FDRE r u_axi_dvi/vdata_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.409 r u_axi_dvi/vdata_reg[2]/Q + net (fo=12, routed) 0.241 -0.169 u_axi_dvi/vdata_reg_n_0_[2] + SLICE_X2Y73 LUT4 (Prop_lut4_I2_O) 0.047 -0.122 r u_axi_dvi/video_red_OBUF[2]_inst_i_53/O + net (fo=1, routed) 0.000 -0.122 u_axi_dvi/video_red_OBUF[2]_inst_i_53_n_0 + SLICE_X2Y73 CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.111 -0.011 r u_axi_dvi/video_red_OBUF[2]_inst_i_19/CO[3] + net (fo=1, routed) 0.000 -0.011 u_axi_dvi/video_red_OBUF[2]_inst_i_19_n_0 + SLICE_X2Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.040 0.029 r u_axi_dvi/video_red_OBUF[2]_inst_i_4/CO[3] + net (fo=1, routed) 0.222 0.252 u_axi_dvi/vdata1_in_range07_in + SLICE_X6Y74 LUT5 (Prop_lut5_I2_O) 0.045 0.297 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 1.907 2.203 video_red_OBUF[0] + K23 OBUF (Prop_obuf_I_O) 1.233 3.437 r video_red_OBUF[0]_inst/O + net (fo=0) 0.000 3.437 video_red[0] + K23 r video_red[0] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: u_axi_dvi/hdata_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -29997,7 +43767,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.614ns (logic 1.455ns (40.253%) route 2.159ns (59.747%)) + Data Path Delay: 4.159ns (logic 1.455ns (34.973%) route 2.705ns (65.027%)) Logic Levels: 2 (LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -30015,108 +43785,26 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C + net (fo=35652, routed) 0.712 -0.550 u_axi_dvi/sys_clk + SLICE_X6Y72 FDRE r u_axi_dvi/hdata_reg[11]/C ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 f u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.447 0.038 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X9Y86 LUT5 (Prop_lut5_I1_O) 0.045 0.083 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O - net (fo=1, routed) 1.713 1.796 video_hsync_OBUF - J24 OBUF (Prop_obuf_I_O) 1.246 3.041 r video_hsync_OBUF_inst/O - net (fo=0) 0.000 3.041 video_hsync + SLICE_X6Y72 FDRE (Prop_fdre_C_Q) 0.164 -0.386 f u_axi_dvi/hdata_reg[11]/Q + net (fo=12, routed) 0.410 0.023 u_axi_dvi/hdata_reg_n_0_[11] + SLICE_X0Y72 LUT5 (Prop_lut5_I1_O) 0.045 0.068 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O + net (fo=1, routed) 2.295 2.363 video_hsync_OBUF + J24 OBUF (Prop_obuf_I_O) 1.246 3.609 r video_hsync_OBUF_inst/O + net (fo=0) 0.000 3.609 video_hsync J24 r video_hsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_axi_dvi/vdata_reg[8]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_vsync - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.713ns (logic 1.505ns (40.539%) route 2.208ns (59.461%)) - Logic Levels: 3 (LUT4=2 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.687 -0.575 u_axi_dvi/sys_clk - SLICE_X18Y80 FDRE r u_axi_dvi/vdata_reg[8]/C - ------------------------------------------------------------------- ------------------- - SLICE_X18Y80 FDRE (Prop_fdre_C_Q) 0.164 -0.411 f u_axi_dvi/vdata_reg[8]/Q - net (fo=11, routed) 0.333 -0.079 u_axi_dvi/vdata_reg_n_0_[8] - SLICE_X17Y86 LUT4 (Prop_lut4_I3_O) 0.045 -0.034 f u_axi_dvi/video_vsync_OBUF_inst_i_4/O - net (fo=2, routed) 0.093 0.059 u_axi_dvi/video_vsync_OBUF_inst_i_4_n_0 - SLICE_X17Y86 LUT4 (Prop_lut4_I3_O) 0.045 0.104 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O - net (fo=1, routed) 1.782 1.886 video_vsync_OBUF - H24 OBUF (Prop_obuf_I_O) 1.251 3.138 r video_vsync_OBUF_inst/O - net (fo=0) 0.000 3.138 video_vsync - H24 r video_vsync (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[2] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.728ns (logic 1.648ns (44.198%) route 2.081ns (55.802%)) - Logic Levels: 4 (CARRY4=2 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 r u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.257 -0.152 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X15Y84 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.113 -0.039 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3] - net (fo=1, routed) 0.000 -0.039 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0 - SLICE_X15Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.039 0.000 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3] - net (fo=1, routed) 0.257 0.257 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I3_O) 0.045 0.302 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 1.568 1.869 video_red_OBUF[0] - E26 OBUF (Prop_obuf_I_O) 1.287 3.156 r video_red_OBUF[2]_inst/O - net (fo=0) 0.000 3.156 video_red[2] - E26 r video_red[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[3] + Destination: dpy1[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.728ns (logic 1.356ns (36.384%) route 2.371ns (63.616%)) + Data Path Delay: 4.208ns (logic 1.362ns (32.369%) route 2.846ns (67.631%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -30134,345 +43822,14 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q - net (fo=1, routed) 2.371 1.976 dpy1_OBUF[3] - F17 OBUF (Prop_obuf_I_O) 1.215 3.191 r dpy1_OBUF[3]_inst/O - net (fo=0) 0.000 3.191 dpy1[3] - F17 r dpy1[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[1] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.827ns (logic 1.622ns (42.374%) route 2.206ns (57.626%)) - Logic Levels: 4 (CARRY4=2 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 r u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.257 -0.152 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X15Y84 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.113 -0.039 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3] - net (fo=1, routed) 0.000 -0.039 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0 - SLICE_X15Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.039 0.000 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3] - net (fo=1, routed) 0.257 0.257 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I3_O) 0.045 0.302 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 1.693 1.994 video_red_OBUF[0] - F24 OBUF (Prop_obuf_I_O) 1.261 3.255 r video_red_OBUF[1]_inst/O - net (fo=0) 0.000 3.255 video_red[1] - F24 r video_red[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[0] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.859ns (logic 1.594ns (41.315%) route 2.265ns (58.685%)) - Logic Levels: 4 (CARRY4=2 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 r u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.257 -0.152 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X15Y84 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.113 -0.039 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3] - net (fo=1, routed) 0.000 -0.039 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0 - SLICE_X15Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.039 0.000 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3] - net (fo=1, routed) 0.257 0.257 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I3_O) 0.045 0.302 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 1.752 2.053 video_red_OBUF[0] - K23 OBUF (Prop_obuf_I_O) 1.233 3.287 r video_red_OBUF[0]_inst/O - net (fo=0) 0.000 3.287 video_red[0] - K23 r video_red[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[2] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.903ns (logic 1.400ns (35.872%) route 2.503ns (64.128%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q - net (fo=1, routed) 2.503 2.039 dpy0_OBUF[2] - B21 OBUF (Prop_obuf_I_O) 1.259 3.298 r dpy0_OBUF[2]_inst/O - net (fo=0) 0.000 3.298 dpy0[2] - B21 r dpy0[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[2]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[2] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.877ns (logic 1.428ns (36.839%) route 2.448ns (63.161%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[2]_lopt_replica/Q - net (fo=1, routed) 2.448 2.053 lopt_8 - A24 OBUF (Prop_obuf_I_O) 1.287 3.340 r leds_OBUF[2]_inst/O - net (fo=0) 0.000 3.340 leds[2] - A24 r leds[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[3]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[3] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.896ns (logic 1.404ns (36.025%) route 2.493ns (63.975%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[3]_lopt_replica/Q - net (fo=1, routed) 2.493 2.097 lopt_9 - D23 OBUF (Prop_obuf_I_O) 1.263 3.360 r leds_OBUF[3]_inst/O - net (fo=0) 0.000 3.360 leds[3] - D23 r leds[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[9]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[9] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.250ns (logic 1.424ns (33.494%) route 2.827ns (66.506%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_confreg/sys_clk - SLICE_X0Y86 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[9]_lopt_replica/Q - net (fo=1, routed) 2.827 2.426 lopt_15 - A23 OBUF (Prop_obuf_I_O) 1.283 3.709 r leds_OBUF[9]_inst/O - net (fo=0) 0.000 3.709 leds[9] - A23 r leds[9] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[5]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[5] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.428ns (logic 1.436ns (32.434%) route 2.992ns (67.566%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.128 -0.409 r u_confreg/led_data_reg[5]_lopt_replica/Q - net (fo=1, routed) 2.992 2.582 lopt_11 - C21 OBUF (Prop_obuf_I_O) 1.308 3.890 r leds_OBUF[5]_inst/O - net (fo=0) 0.000 3.890 leds[5] - C21 r leds[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[4] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.536ns (logic 1.381ns (30.449%) route 3.155ns (69.551%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q - net (fo=1, routed) 3.155 2.691 dpy0_OBUF[4] - E18 OBUF (Prop_obuf_I_O) 1.240 3.931 r dpy0_OBUF[4]_inst/O - net (fo=0) 0.000 3.931 dpy0[4] - E18 r dpy0[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[4]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[4] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.540ns (logic 1.404ns (30.920%) route 3.136ns (69.080%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_confreg/sys_clk - SLICE_X3Y89 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[4]_lopt_replica/Q - net (fo=1, routed) 3.136 2.738 lopt_10 - C22 OBUF (Prop_obuf_I_O) 1.263 4.001 r leds_OBUF[4]_inst/O - net (fo=0) 0.000 4.001 leds[4] - C22 r leds[4] (OUT) + SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q + net (fo=1, routed) 2.846 2.449 dpy1_OBUF[7] + G17 OBUF (Prop_obuf_I_O) 1.221 3.670 r dpy1_OBUF[7]_inst/O + net (fo=0) 0.000 3.670 dpy1[7] + G17 r dpy1[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -30482,7 +43839,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 4.629ns (logic 1.426ns (30.799%) route 3.203ns (69.201%)) + Data Path Delay: 4.363ns (logic 1.443ns (33.063%) route 2.921ns (66.937%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -30500,24 +43857,102 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_confreg/sys_clk - SLICE_X2Y81 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y81 FDRE (Prop_fdre_C_Q) 0.164 -0.380 r u_confreg/led_data_reg[8]_lopt_replica/Q - net (fo=1, routed) 3.203 2.823 lopt_14 - C23 OBUF (Prop_obuf_I_O) 1.262 4.084 r leds_OBUF[8]_inst/O - net (fo=0) 0.000 4.084 leds[8] + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r u_confreg/led_data_reg[8]_lopt_replica/Q + net (fo=1, routed) 2.921 2.509 lopt_14 + C23 OBUF (Prop_obuf_I_O) 1.315 3.824 r leds_OBUF[8]_inst/O + net (fo=0) 0.000 3.824 leds[8] C23 r leds[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[15]_lopt_replica/C + Source: u_confreg/led_data_reg[2]_lopt_replica/C +======= + Source: u_confreg/led_data_reg[9]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[15] + Destination: leds[9] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 4.721ns (logic 1.404ns (29.752%) route 3.316ns (70.248%)) + Data Path Delay: 2.581ns (logic 1.447ns (56.055%) route 1.134ns (43.945%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X14Y141 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X14Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[9]_lopt_replica/Q + net (fo=1, routed) 1.134 0.663 lopt_15 + A23 OBUF (Prop_obuf_I_O) 1.283 1.946 r leds_OBUF[9]_inst/O + net (fo=0) 0.000 1.946 leds[9] + A23 r leds[9] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[15]_lopt_replica/C +>>>>>>> Stashed changes + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[2] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner +<<<<<<< Updated upstream + Data Path Delay: 4.375ns (logic 1.428ns (32.639%) route 2.947ns (67.361%)) +======= + Data Path Delay: 2.597ns (logic 1.427ns (54.964%) route 1.170ns (45.036%)) +>>>>>>> Stashed changes + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.721 -0.541 u_confreg/sys_clk + SLICE_X0Y84 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[2]_lopt_replica/Q + net (fo=1, routed) 2.947 2.547 lopt_8 + A24 OBUF (Prop_obuf_I_O) 1.287 3.834 r leds_OBUF[2]_inst/O + net (fo=0) 0.000 3.834 leds[2] + A24 r leds[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[9]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[9] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.395ns (logic 1.424ns (32.390%) route 2.972ns (67.610%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -30535,14 +43970,1507 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C + net (fo=35652, routed) 0.721 -0.541 u_confreg/sys_clk + SLICE_X0Y84 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[15]_lopt_replica/Q - net (fo=1, routed) 3.316 2.920 lopt_6 - B20 OBUF (Prop_obuf_I_O) 1.263 4.183 r leds_OBUF[15]_inst/O - net (fo=0) 0.000 4.183 leds[15] + SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[9]_lopt_replica/Q + net (fo=1, routed) 2.972 2.571 lopt_15 + A23 OBUF (Prop_obuf_I_O) 1.283 3.854 r leds_OBUF[9]_inst/O + net (fo=0) 0.000 3.854 leds[9] + A23 r leds[9] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[1]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.695ns (logic 1.424ns (30.329%) route 3.271ns (69.671%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r u_confreg/led_data_reg[1]_lopt_replica/Q + net (fo=1, routed) 3.271 2.860 lopt_7 + E21 OBUF (Prop_obuf_I_O) 1.296 4.155 r leds_OBUF[1]_inst/O + net (fo=0) 0.000 4.155 leds[1] + E21 r leds[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[13]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[13] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.756ns (logic 1.412ns (29.687%) route 3.344ns (70.313%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[13]_lopt_replica/Q + net (fo=1, routed) 3.344 2.946 lopt_4 + A22 OBUF (Prop_obuf_I_O) 1.271 4.217 r leds_OBUF[13]_inst/O + net (fo=0) 0.000 4.217 leds[13] + A22 r leds[13] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[5] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 5.792ns (logic 1.376ns (23.753%) route 4.416ns (76.247%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q + net (fo=1, routed) 4.416 4.019 dpy1_OBUF[5] + G16 OBUF (Prop_obuf_I_O) 1.235 5.254 r dpy1_OBUF[5]_inst/O + net (fo=0) 0.000 5.254 dpy1[5] + G16 r dpy1[5] (OUT) +======= + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X12Y142 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[15]_lopt_replica/Q + net (fo=1, routed) 1.170 0.699 lopt_6 + B20 OBUF (Prop_obuf_I_O) 1.263 1.962 r leds_OBUF[15]_inst/O + net (fo=0) 0.000 1.962 leds[15] B20 r leds[15] (OUT) +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[10]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[10] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.666ns (logic 1.412ns (52.947%) route 1.255ns (47.053%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk + SLICE_X20Y141 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X20Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[10]_lopt_replica/Q + net (fo=1, routed) 1.255 0.781 lopt_1 + D21 OBUF (Prop_obuf_I_O) 1.248 2.028 r leds_OBUF[10]_inst/O + net (fo=0) 0.000 2.028 leds[10] + D21 r leds[10] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[12]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[12] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.709ns (logic 1.384ns (51.091%) route 1.325ns (48.909%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X13Y142 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y142 FDRE (Prop_fdre_C_Q) 0.141 -0.494 r u_confreg/led_data_reg[12]_lopt_replica/Q + net (fo=1, routed) 1.325 0.831 lopt_3 + D20 OBUF (Prop_obuf_I_O) 1.243 2.074 r leds_OBUF[12]_inst/O + net (fo=0) 0.000 2.074 leds[12] + D20 r leds[12] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[0]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.736ns (logic 1.439ns (52.603%) route 1.297ns (47.397%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk + SLICE_X22Y141 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[0]_lopt_replica/Q + net (fo=1, routed) 1.297 0.823 lopt + B24 OBUF (Prop_obuf_I_O) 1.275 2.098 r leds_OBUF[0]_inst/O + net (fo=0) 0.000 2.098 leds[0] + B24 r leds[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[11]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[11] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.765ns (logic 1.431ns (51.772%) route 1.333ns (48.228%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X12Y141 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[11]_lopt_replica/Q + net (fo=1, routed) 1.333 0.862 lopt_2 + A18 OBUF (Prop_obuf_I_O) 1.267 2.130 r leds_OBUF[11]_inst/O + net (fo=0) 0.000 2.130 leds[11] + A18 r leds[11] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[1]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.956ns (logic 1.406ns (47.555%) route 1.550ns (52.445%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X12Y142 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[1]_lopt_replica/Q + net (fo=1, routed) 1.550 1.079 lopt_7 + E21 OBUF (Prop_obuf_I_O) 1.242 2.321 r leds_OBUF[1]_inst/O + net (fo=0) 0.000 2.321 leds[1] + E21 r leds[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[13]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[13] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.031ns (logic 1.412ns (46.583%) route 1.619ns (53.417%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X13Y142 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y142 FDRE (Prop_fdre_C_Q) 0.141 -0.494 r u_confreg/led_data_reg[13]_lopt_replica/Q + net (fo=1, routed) 1.619 1.125 lopt_4 + A22 OBUF (Prop_obuf_I_O) 1.271 2.396 r leds_OBUF[13]_inst/O + net (fo=0) 0.000 2.396 leds[13] + A22 r leds[13] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[5]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[5] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.069ns (logic 1.418ns (46.208%) route 1.651ns (53.792%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk + SLICE_X20Y141 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X20Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[5]_lopt_replica/Q + net (fo=1, routed) 1.651 1.177 lopt_11 + C21 OBUF (Prop_obuf_I_O) 1.254 2.431 r leds_OBUF[5]_inst/O + net (fo=0) 0.000 2.431 leds[5] + C21 r leds[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[3]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[3] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.092ns (logic 1.427ns (46.147%) route 1.665ns (53.853%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.617 -0.646 u_confreg/sys_clk + SLICE_X36Y141 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X36Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.482 r u_confreg/led_data_reg[3]_lopt_replica/Q + net (fo=1, routed) 1.665 1.183 lopt_9 + D23 OBUF (Prop_obuf_I_O) 1.263 2.446 r leds_OBUF[3]_inst/O + net (fo=0) 0.000 2.446 leds[3] + D23 r leds[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[8]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[8] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.086ns (logic 1.426ns (46.198%) route 1.660ns (53.802%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk + SLICE_X22Y141 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[8]_lopt_replica/Q + net (fo=1, routed) 1.660 1.186 lopt_14 + C23 OBUF (Prop_obuf_I_O) 1.262 2.448 r leds_OBUF[8]_inst/O + net (fo=0) 0.000 2.448 leds[8] + C23 r leds[8] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[4]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[4] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.088ns (logic 1.427ns (46.209%) route 1.661ns (53.791%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk + SLICE_X22Y141 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[4]_lopt_replica/Q + net (fo=1, routed) 1.661 1.187 lopt_10 + C22 OBUF (Prop_obuf_I_O) 1.263 2.450 r leds_OBUF[4]_inst/O + net (fo=0) 0.000 2.450 leds[4] + C22 r leds[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[7]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[7] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.095ns (logic 1.437ns (46.407%) route 1.659ns (53.593%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X12Y142 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[7]_lopt_replica/Q + net (fo=1, routed) 1.659 1.188 lopt_13 + B22 OBUF (Prop_obuf_I_O) 1.273 2.461 r leds_OBUF[7]_inst/O + net (fo=0) 0.000 2.461 leds[7] + B22 r leds[7] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[6]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[6] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.132ns (logic 1.406ns (44.897%) route 1.726ns (55.103%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk + SLICE_X12Y142 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[6]_lopt_replica/Q + net (fo=1, routed) 1.726 1.255 lopt_12 + E20 OBUF (Prop_obuf_I_O) 1.242 2.497 r leds_OBUF[6]_inst/O + net (fo=0) 0.000 2.497 leds[6] + E20 r leds[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[14]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[14] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.179ns (logic 1.427ns (44.902%) route 1.752ns (55.098%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk + SLICE_X22Y141 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[14]_lopt_replica/Q + net (fo=1, routed) 1.752 1.278 lopt_5 + A20 OBUF (Prop_obuf_I_O) 1.263 2.541 r leds_OBUF[14]_inst/O + net (fo=0) 0.000 2.541 leds[14] + A20 r leds[14] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[2]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[2] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.213ns (logic 1.451ns (45.157%) route 1.762ns (54.843%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.617 -0.646 u_confreg/sys_clk + SLICE_X36Y140 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X36Y140 FDRE (Prop_fdre_C_Q) 0.164 -0.482 r u_confreg/led_data_reg[2]_lopt_replica/Q + net (fo=1, routed) 1.762 1.280 lopt_8 + A24 OBUF (Prop_obuf_I_O) 1.287 2.567 r leds_OBUF[2]_inst/O + net (fo=0) 0.000 2.567 leds[2] + A24 r leds[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: UART_TX + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.463ns (logic 1.033ns (29.825%) route 2.430ns (70.175%)) + Logic Levels: 2 (LUT3=1 OBUFT=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.572 -0.691 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X76Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y137 FDRE (Prop_fdre_C_Q) 0.164 -0.527 r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/Q + net (fo=2, routed) 0.147 -0.380 u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en + SLICE_X77Y137 LUT3 (Prop_lut3_I0_O) 0.045 -0.335 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O + net (fo=1, routed) 2.283 1.949 UART_TX_IOBUF_inst/T + H18 OBUFT (TriStatD_obuft_T_O) + 0.824 2.773 r UART_TX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 2.773 UART_TX + H18 r UART_TX (INOUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[2] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.498ns (logic 1.406ns (40.207%) route 2.091ns (59.793%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q + net (fo=1, routed) 2.091 1.566 dpy1_OBUF[2] + E17 OBUF (Prop_obuf_I_O) 1.242 2.808 r dpy1_OBUF[2]_inst/O + net (fo=0) 0.000 2.808 dpy1[2] + E17 r dpy1[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.553ns (logic 1.387ns (39.035%) route 2.166ns (60.965%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q + net (fo=1, routed) 2.166 1.625 dpy0_OBUF[1] + D19 OBUF (Prop_obuf_I_O) 1.246 2.871 r dpy0_OBUF[1]_inst/O + net (fo=0) 0.000 2.871 dpy0[1] + D19 r dpy0[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[2] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.658ns (logic 1.400ns (38.270%) route 2.258ns (61.730%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q + net (fo=1, routed) 2.258 1.717 dpy0_OBUF[2] + B21 OBUF (Prop_obuf_I_O) 1.259 2.976 r dpy0_OBUF[2]_inst/O + net (fo=0) 0.000 2.976 dpy0[2] + B21 r dpy0[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.681ns (logic 1.430ns (38.848%) route 2.251ns (61.152%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q + net (fo=1, routed) 2.251 1.725 dpy1_OBUF[0] + A17 OBUF (Prop_obuf_I_O) 1.266 2.991 r dpy1_OBUF[0]_inst/O + net (fo=0) 0.000 2.991 dpy1[0] + A17 r dpy1[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.690ns (logic 1.414ns (38.316%) route 2.276ns (61.684%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q + net (fo=1, routed) 2.276 1.750 dpy1_OBUF[1] + D16 OBUF (Prop_obuf_I_O) 1.250 3.000 r dpy1_OBUF[1]_inst/O + net (fo=0) 0.000 3.000 dpy1[1] + D16 r dpy1[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[3] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.708ns (logic 1.438ns (38.776%) route 2.270ns (61.224%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.164 -0.518 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q + net (fo=1, routed) 2.270 1.752 dpy0_OBUF[3] + A19 OBUF (Prop_obuf_I_O) 1.274 3.026 r dpy0_OBUF[3]_inst/O + net (fo=0) 0.000 3.026 dpy0[3] + A19 r dpy0[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[5] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.719ns (logic 1.399ns (37.614%) route 2.320ns (62.386%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q + net (fo=1, routed) 2.320 1.794 dpy1_OBUF[5] + G16 OBUF (Prop_obuf_I_O) 1.235 3.029 r dpy1_OBUF[5]_inst/O + net (fo=0) 0.000 3.029 dpy1[5] + G16 r dpy1[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[4] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.719ns (logic 1.406ns (37.816%) route 2.313ns (62.184%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q + net (fo=1, routed) 2.313 1.787 dpy1_OBUF[4] + E16 OBUF (Prop_obuf_I_O) 1.242 3.029 r dpy1_OBUF[4]_inst/O + net (fo=0) 0.000 3.029 dpy1[4] + E16 r dpy1[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C + (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: UART_RX + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.734ns (logic 0.988ns (26.459%) route 2.746ns (73.541%)) + Logic Levels: 1 (OBUFT=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.563 -0.700 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X80Y133 FDSE r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y133 FDSE (Prop_fdse_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/Q + net (fo=28, routed) 2.746 2.210 UART_RX_IOBUF_inst/T + J20 OBUFT (TriStatD_obuft_T_O) + 0.824 3.034 r UART_RX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 3.034 UART_RX + J20 r UART_RX (INOUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[6] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.726ns (logic 1.402ns (37.617%) route 2.325ns (62.383%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q + net (fo=1, routed) 2.325 1.799 dpy1_OBUF[6] + F15 OBUF (Prop_obuf_I_O) 1.238 3.037 r dpy1_OBUF[6]_inst/O + net (fo=0) 0.000 3.037 dpy1[6] + F15 r dpy1[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[3] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.738ns (logic 1.379ns (36.896%) route 2.359ns (63.104%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q + net (fo=1, routed) 2.359 1.833 dpy1_OBUF[3] + F17 OBUF (Prop_obuf_I_O) 1.215 3.049 r dpy1_OBUF[3]_inst/O + net (fo=0) 0.000 3.049 dpy1[3] + F17 r dpy1[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[5] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.812ns (logic 1.388ns (36.398%) route 2.425ns (63.602%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q + net (fo=1, routed) 2.425 1.884 dpy0_OBUF[5] + C19 OBUF (Prop_obuf_I_O) 1.247 3.130 r dpy0_OBUF[5]_inst/O + net (fo=0) 0.000 3.130 dpy0[5] + C19 r dpy0[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[7] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.845ns (logic 1.385ns (36.025%) route 2.460ns (63.975%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q + net (fo=1, routed) 2.460 1.934 dpy1_OBUF[7] + G17 OBUF (Prop_obuf_I_O) 1.221 3.155 r dpy1_OBUF[7]_inst/O + net (fo=0) 0.000 3.155 dpy1[7] + G17 r dpy1[7] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.860ns (logic 1.402ns (36.317%) route 2.458ns (63.683%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.582 -0.681 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X63Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X63Y141 FDCE (Prop_fdce_C_Q) 0.141 -0.540 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q + net (fo=1, routed) 2.458 1.918 dpy0_OBUF[0] + B19 OBUF (Prop_obuf_I_O) 1.261 3.179 r dpy0_OBUF[0]_inst/O + net (fo=0) 0.000 3.179 dpy0[0] + B19 r dpy0[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[4] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.015ns (logic 1.404ns (34.969%) route 2.611ns (65.031%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.164 -0.518 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q + net (fo=1, routed) 2.611 2.093 dpy0_OBUF[4] + E18 OBUF (Prop_obuf_I_O) 1.240 3.333 r dpy0_OBUF[4]_inst/O + net (fo=0) 0.000 3.333 dpy0[4] + E18 r dpy0[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[7] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.060ns (logic 1.409ns (34.714%) route 2.651ns (65.286%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.164 -0.518 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q + net (fo=1, routed) 2.651 2.133 dpy0_OBUF[7] + C17 OBUF (Prop_obuf_I_O) 1.245 3.378 r dpy0_OBUF[7]_inst/O + net (fo=0) 0.000 3.378 dpy0[7] + C17 r dpy0[7] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/hdata_reg[10]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_hsync + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.023ns (logic 1.455ns (36.157%) route 2.569ns (63.843%)) + Logic Levels: 2 (LUT5=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.650 -0.612 u_axi_dvi/sys_clk + SLICE_X46Y86 FDRE r u_axi_dvi/hdata_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X46Y86 FDRE (Prop_fdre_C_Q) 0.164 -0.448 f u_axi_dvi/hdata_reg[10]/Q + net (fo=12, routed) 0.384 -0.065 u_axi_dvi/hdata_reg_n_0_[10] + SLICE_X41Y86 LUT5 (Prop_lut5_I0_O) 0.045 -0.020 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O + net (fo=1, routed) 2.185 2.165 video_hsync_OBUF + J24 OBUF (Prop_obuf_I_O) 1.246 3.411 r video_hsync_OBUF_inst/O + net (fo=0) 0.000 3.411 video_hsync + J24 r video_hsync (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[6] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.163ns (logic 1.421ns (34.137%) route 2.742ns (65.863%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.164 -0.518 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q + net (fo=1, routed) 2.742 2.224 dpy0_OBUF[6] + B17 OBUF (Prop_obuf_I_O) 1.257 3.481 r dpy0_OBUF[6]_inst/O + net (fo=0) 0.000 3.481 dpy0[6] + B17 r dpy0[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[10]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_vsync + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.146ns (logic 1.482ns (35.753%) route 2.664ns (64.247%)) + Logic Levels: 3 (LUT4=2 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.649 -0.613 u_axi_dvi/sys_clk + SLICE_X47Y83 FDRE r u_axi_dvi/vdata_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y83 FDRE (Prop_fdre_C_Q) 0.141 -0.472 f u_axi_dvi/vdata_reg[10]/Q + net (fo=11, routed) 0.120 -0.353 u_axi_dvi/vdata_reg_n_0_[10] + SLICE_X49Y82 LUT4 (Prop_lut4_I1_O) 0.045 -0.308 f u_axi_dvi/video_vsync_OBUF_inst_i_4/O + net (fo=2, routed) 0.145 -0.163 u_axi_dvi/video_vsync_OBUF_inst_i_4_n_0 + SLICE_X49Y81 LUT4 (Prop_lut4_I3_O) 0.045 -0.118 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O + net (fo=1, routed) 2.399 2.281 video_vsync_OBUF + H24 OBUF (Prop_obuf_I_O) 1.251 3.532 r video_vsync_OBUF_inst/O + net (fo=0) 0.000 3.532 video_vsync + H24 r video_vsync (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/hdata_reg[11]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_de + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.171ns (logic 1.470ns (35.251%) route 2.701ns (64.749%)) + Logic Levels: 2 (LUT6=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.650 -0.612 u_axi_dvi/sys_clk + SLICE_X46Y86 FDRE r u_axi_dvi/hdata_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X46Y86 FDRE (Prop_fdre_C_Q) 0.164 -0.448 f u_axi_dvi/hdata_reg[11]/Q + net (fo=12, routed) 0.239 -0.210 u_axi_dvi/hdata_reg_n_0_[11] + SLICE_X46Y83 LUT6 (Prop_lut6_I3_O) 0.045 -0.165 r u_axi_dvi/video_de_OBUF_inst_i_1/O + net (fo=1, routed) 2.462 2.297 video_de_OBUF + G24 OBUF (Prop_obuf_I_O) 1.261 3.559 r video_de_OBUF_inst/O + net (fo=0) 0.000 3.559 video_de + G24 r video_de (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/DVI_SQU_DIR_reg[31]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[2] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.241ns (logic 1.808ns (42.631%) route 2.433ns (57.369%)) + Logic Levels: 6 (CARRY4=2 LUT2=2 LUT5=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.680 -0.582 u_axi_dvi/sys_clk + SLICE_X39Y85 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[31]/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.441 r u_axi_dvi/DVI_SQU_DIR_reg[31]/Q + net (fo=3, routed) 0.121 -0.320 u_axi_dvi/p_1_in[15] + SLICE_X40Y85 LUT2 (Prop_lut2_I0_O) 0.045 -0.275 r u_axi_dvi/video_red_OBUF[2]_inst_i_107/O + net (fo=1, routed) 0.000 -0.275 u_axi_dvi/video_red_OBUF[2]_inst_i_107_n_0 + SLICE_X40Y85 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.064 -0.211 f u_axi_dvi/video_red_OBUF[2]_inst_i_50/O[3] + net (fo=1, routed) 0.110 -0.101 hdata1_in_range11_out[15] + SLICE_X41Y84 LUT2 (Prop_lut2_I0_O) 0.111 0.010 r video_red_OBUF[2]_inst_i_15/O + net (fo=1, routed) 0.000 0.010 u_axi_dvi/video_red_OBUF[2]_inst_i_1_2[1] + SLICE_X41Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.115 0.125 r u_axi_dvi/video_red_OBUF[2]_inst_i_3/CO[3] + net (fo=1, routed) 0.214 0.338 u_axi_dvi/hdata1_in_range08_in + SLICE_X41Y85 LUT5 (Prop_lut5_I1_O) 0.045 0.383 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 1.988 2.372 video_red_OBUF[0] + E26 OBUF (Prop_obuf_I_O) 1.287 3.658 r video_red_OBUF[2]_inst/O + net (fo=0) 0.000 3.658 video_red[2] + E26 r video_red[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/DVI_SQU_DIR_reg[31]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.340ns (logic 1.782ns (41.058%) route 2.558ns (58.942%)) + Logic Levels: 6 (CARRY4=2 LUT2=2 LUT5=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.680 -0.582 u_axi_dvi/sys_clk + SLICE_X39Y85 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[31]/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.441 r u_axi_dvi/DVI_SQU_DIR_reg[31]/Q + net (fo=3, routed) 0.121 -0.320 u_axi_dvi/p_1_in[15] + SLICE_X40Y85 LUT2 (Prop_lut2_I0_O) 0.045 -0.275 r u_axi_dvi/video_red_OBUF[2]_inst_i_107/O + net (fo=1, routed) 0.000 -0.275 u_axi_dvi/video_red_OBUF[2]_inst_i_107_n_0 + SLICE_X40Y85 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.064 -0.211 f u_axi_dvi/video_red_OBUF[2]_inst_i_50/O[3] + net (fo=1, routed) 0.110 -0.101 hdata1_in_range11_out[15] + SLICE_X41Y84 LUT2 (Prop_lut2_I0_O) 0.111 0.010 r video_red_OBUF[2]_inst_i_15/O + net (fo=1, routed) 0.000 0.010 u_axi_dvi/video_red_OBUF[2]_inst_i_1_2[1] + SLICE_X41Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.115 0.125 r u_axi_dvi/video_red_OBUF[2]_inst_i_3/CO[3] + net (fo=1, routed) 0.214 0.338 u_axi_dvi/hdata1_in_range08_in + SLICE_X41Y85 LUT5 (Prop_lut5_I1_O) 0.045 0.383 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 2.113 2.497 video_red_OBUF[0] + F24 OBUF (Prop_obuf_I_O) 1.261 3.757 r video_red_OBUF[1]_inst/O + net (fo=0) 0.000 3.757 video_red[1] + F24 r video_red[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/DVI_SQU_DIR_reg[31]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.372ns (logic 1.754ns (40.132%) route 2.617ns (59.868%)) + Logic Levels: 6 (CARRY4=2 LUT2=2 LUT5=1 OBUF=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.680 -0.582 u_axi_dvi/sys_clk + SLICE_X39Y85 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[31]/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.441 r u_axi_dvi/DVI_SQU_DIR_reg[31]/Q + net (fo=3, routed) 0.121 -0.320 u_axi_dvi/p_1_in[15] + SLICE_X40Y85 LUT2 (Prop_lut2_I0_O) 0.045 -0.275 r u_axi_dvi/video_red_OBUF[2]_inst_i_107/O + net (fo=1, routed) 0.000 -0.275 u_axi_dvi/video_red_OBUF[2]_inst_i_107_n_0 + SLICE_X40Y85 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.064 -0.211 f u_axi_dvi/video_red_OBUF[2]_inst_i_50/O[3] + net (fo=1, routed) 0.110 -0.101 hdata1_in_range11_out[15] + SLICE_X41Y84 LUT2 (Prop_lut2_I0_O) 0.111 0.010 r video_red_OBUF[2]_inst_i_15/O + net (fo=1, routed) 0.000 0.010 u_axi_dvi/video_red_OBUF[2]_inst_i_1_2[1] + SLICE_X41Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.115 0.125 r u_axi_dvi/video_red_OBUF[2]_inst_i_3/CO[3] + net (fo=1, routed) 0.214 0.338 u_axi_dvi/hdata1_in_range08_in + SLICE_X41Y85 LUT5 (Prop_lut5_I1_O) 0.045 0.383 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 2.172 2.556 video_red_OBUF[0] + K23 OBUF (Prop_obuf_I_O) 1.233 3.789 r video_red_OBUF[0]_inst/O + net (fo=0) 0.000 3.789 video_red[0] + K23 r video_red[0] (OUT) ------------------------------------------------------------------- ------------------- @@ -30562,53 +45490,17 @@ Min Delay 43 Endpoints Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.811ns (logic 0.287ns (15.865%) route 1.523ns (84.135%)) - Logic Levels: 2 (IBUF=1 LUT5=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 f UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.523 1.766 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF - SLICE_X4Y61 LUT5 (Prop_lut5_I2_O) 0.045 1.811 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O - net (fo=1, routed) 0.000 1.811 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 - SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C - -Slack: inf +<<<<<<< Updated upstream Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.893ns (logic 0.287ns (15.179%) route 1.605ns (84.821%)) + Data Path Delay: 1.872ns (logic 0.287ns (15.346%) route 1.585ns (84.654%)) Logic Levels: 2 (IBUF=1 LUT4=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns + Clock Path Skew: -0.231ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.231ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -30617,10 +45509,10 @@ Slack: inf H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.605 1.848 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_TX_IBUF - SLICE_X1Y61 LUT4 (Prop_lut4_I2_O) 0.045 1.893 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O - net (fo=1, routed) 0.000 1.893 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D + net (fo=4, routed) 1.585 1.827 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_TX_IBUF + SLICE_X0Y42 LUT4 (Prop_lut4_I2_O) 0.045 1.872 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O + net (fo=1, routed) 0.000 1.872 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i + SLICE_X0Y42 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -30632,78 +45524,8 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - -Slack: inf - Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Removal (Min at Fast Process Corner) - Data Path Delay: 1.899ns (logic 0.045ns (2.370%) route 1.854ns (97.630%)) - Logic Levels: 1 (LUT1=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - net (fo=1, routed) 1.417 1.417 pll_clk.u_rst_sys/locked - SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.045 1.462 f pll_clk.u_rst_sys/delay[1]_i_1/O - net (fo=2, routed) 0.437 1.899 pll_clk.u_rst_sys/delay[1]_i_1_n_0 - SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.932 -0.376 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C - -Slack: inf - Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Removal (Min at Fast Process Corner) - Data Path Delay: 1.899ns (logic 0.045ns (2.370%) route 1.854ns (97.630%)) - Logic Levels: 1 (LUT1=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - net (fo=1, routed) 1.417 1.417 pll_clk.u_rst_sys/locked - SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.045 1.462 f pll_clk.u_rst_sys/delay[1]_i_1/O - net (fo=2, routed) 0.437 1.899 pll_clk.u_rst_sys/delay[1]_i_1_n_0 - SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.932 -0.376 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.077 -0.231 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk + SLICE_X0Y42 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C Slack: inf Source: UART_TX @@ -30712,10 +45534,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.058ns (logic 0.287ns (13.959%) route 1.771ns (86.041%)) + Data Path Delay: 1.957ns (logic 0.287ns (14.676%) route 1.670ns (85.324%)) Logic Levels: 2 (IBUF=1 LUT5=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns + Clock Path Skew: -0.232ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.232ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -30724,10 +45546,10 @@ Slack: inf H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.550 1.793 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT5 (Prop_lut5_I0_O) 0.045 1.838 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O - net (fo=1, routed) 0.220 2.058 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D + net (fo=4, routed) 1.670 1.912 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X1Y38 LUT5 (Prop_lut5_I0_O) 0.045 1.957 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O + net (fo=1, routed) 0.000 1.957 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 + SLICE_X1Y38 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -30739,8 +45561,45 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C + net (fo=35652, routed) 1.076 -0.232 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X1Y38 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.987ns (logic 0.287ns (14.457%) route 1.700ns (85.543%)) + Logic Levels: 2 (IBUF=1 LUT5=1) + Clock Path Skew: -0.232ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.232ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 f UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 1.700 1.942 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF + SLICE_X1Y39 LUT5 (Prop_lut5_I2_O) 0.045 1.987 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O + net (fo=1, routed) 0.000 1.987 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.076 -0.232 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C Slack: inf Source: UART_TX @@ -30749,10 +45608,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.089ns (logic 0.408ns (19.545%) route 1.681ns (80.455%)) + Data Path Delay: 2.184ns (logic 0.395ns (18.098%) route 1.789ns (81.902%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns + Clock Path Skew: -0.232ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.232ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -30761,12 +45620,12 @@ Slack: inf H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.550 1.793 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.048 1.841 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O - net (fo=2, routed) 0.130 1.971 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 - SLICE_X2Y61 LUT6 (Prop_lut6_I2_O) 0.118 2.089 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O - net (fo=1, routed) 0.000 2.089 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 - SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D + net (fo=4, routed) 1.670 1.912 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X1Y38 LUT2 (Prop_lut2_I1_O) 0.046 1.958 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O + net (fo=2, routed) 0.119 2.077 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 + SLICE_X1Y39 LUT6 (Prop_lut6_I2_O) 0.107 2.184 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O + net (fo=1, routed) 0.000 2.184 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -30778,43 +45637,8 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C - -Slack: inf - Source: touch_btn[0] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.121ns (logic 0.267ns (12.568%) route 1.855ns (87.432%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -0.339ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T2 0.000 0.000 r touch_btn[0] (IN) - net (fo=0) 0.000 0.000 touch_btn[0] - T2 IBUF (Prop_ibuf_I_O) 0.267 0.267 r touch_btn_IBUF[0]_inst/O - net (fo=1, routed) 1.855 2.121 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_confreg/u_int_ctrl/sys_clk - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C + net (fo=35652, routed) 1.076 -0.232 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C Slack: inf Source: UART_TX @@ -30823,10 +45647,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.315ns (logic 0.406ns (17.548%) route 1.909ns (82.452%)) + Data Path Delay: 2.412ns (logic 0.394ns (16.343%) route 2.018ns (83.657%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns + Clock Path Skew: -0.232ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.232ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -30835,12 +45659,12 @@ Slack: inf H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.550 1.793 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.048 1.841 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O - net (fo=2, routed) 0.239 2.080 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 - SLICE_X2Y60 LUT5 (Prop_lut5_I1_O) 0.116 2.196 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O - net (fo=1, routed) 0.119 2.315 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D + net (fo=4, routed) 1.670 1.912 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X1Y38 LUT2 (Prop_lut2_I1_O) 0.046 1.958 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O + net (fo=2, routed) 0.348 2.306 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 + SLICE_X1Y39 LUT5 (Prop_lut5_I1_O) 0.106 2.412 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O + net (fo=1, routed) 0.000 2.412 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -30852,242 +45676,8 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C - -Slack: inf - Source: dip_sw[31] - (input port) - Destination: u_confreg/s_rdata_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.513ns (logic 0.351ns (13.984%) route 2.162ns (86.016%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R2 0.000 0.000 r dip_sw[31] (IN) - net (fo=0) 0.000 0.000 dip_sw[31] - R2 IBUF (Prop_ibuf_I_O) 0.261 0.261 r dip_sw_IBUF[31]_inst/O - net (fo=1, routed) 1.988 2.249 u_confreg/dip_sw_IBUF[31] - SLICE_X2Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.294 r u_confreg/s_rdata[31]_i_6/O - net (fo=1, routed) 0.174 2.468 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 - SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.513 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O - net (fo=1, routed) 0.000 2.513 u_confreg/u_int_ctrl_n_0 - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/C - -Slack: inf - Source: dip_sw[27] - (input port) - Destination: u_confreg/s_rdata_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.522ns (logic 0.362ns (14.372%) route 2.159ns (85.628%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.338ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R1 0.000 0.000 r dip_sw[27] (IN) - net (fo=0) 0.000 0.000 dip_sw[27] - R1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[27]_inst/O - net (fo=1, routed) 1.804 2.076 u_confreg/dip_sw_IBUF[27] - SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.121 r u_confreg/s_rdata[27]_i_4/O - net (fo=1, routed) 0.356 2.477 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.522 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O - net (fo=1, routed) 0.000 2.522 u_confreg/u_int_ctrl_n_4 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/C - -Slack: inf - Source: dip_sw[22] - (input port) - Destination: u_confreg/s_rdata_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.618ns (logic 0.320ns (12.234%) route 2.298ns (87.766%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P6 0.000 0.000 r dip_sw[22] (IN) - net (fo=0) 0.000 0.000 dip_sw[22] - P6 IBUF (Prop_ibuf_I_O) 0.230 0.230 r dip_sw_IBUF[22]_inst/O - net (fo=1, routed) 1.991 2.221 u_confreg/dip_sw_IBUF[22] - SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.045 2.266 r u_confreg/s_rdata[22]_i_4/O - net (fo=1, routed) 0.307 2.573 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 - SLICE_X4Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.618 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O - net (fo=1, routed) 0.000 2.618 u_confreg/u_int_ctrl_n_9 - SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/C - -Slack: inf - Source: dip_sw[28] - (input port) - Destination: u_confreg/s_rdata_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.622ns (logic 0.326ns (12.419%) route 2.296ns (87.581%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R5 0.000 0.000 r dip_sw[28] (IN) - net (fo=0) 0.000 0.000 dip_sw[28] - R5 IBUF (Prop_ibuf_I_O) 0.236 0.236 r dip_sw_IBUF[28]_inst/O - net (fo=1, routed) 2.141 2.376 u_confreg/dip_sw_IBUF[28] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.421 r u_confreg/s_rdata[28]_i_4/O - net (fo=1, routed) 0.155 2.577 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.622 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O - net (fo=1, routed) 0.000 2.622 u_confreg/u_int_ctrl_n_3 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/C - -Slack: inf - Source: dip_sw[30] - (input port) - Destination: u_confreg/s_rdata_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.648ns (logic 0.317ns (11.976%) route 2.331ns (88.024%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R6 0.000 0.000 r dip_sw[30] (IN) - net (fo=0) 0.000 0.000 dip_sw[30] - R6 IBUF (Prop_ibuf_I_O) 0.227 0.227 r dip_sw_IBUF[30]_inst/O - net (fo=1, routed) 1.934 2.162 u_confreg/dip_sw_IBUF[30] - SLICE_X2Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.207 r u_confreg/s_rdata[30]_i_4/O - net (fo=1, routed) 0.396 2.603 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 - SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.648 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O - net (fo=1, routed) 0.000 2.648 u_confreg/u_int_ctrl_n_1 - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_confreg/sys_clk - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/C - -Slack: inf - Source: dip_sw[18] - (input port) - Destination: u_confreg/s_rdata_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.666ns (logic 0.347ns (13.011%) route 2.319ns (86.989%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.340ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.340ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N3 0.000 0.000 r dip_sw[18] (IN) - net (fo=0) 0.000 0.000 dip_sw[18] - N3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[18]_inst/O - net (fo=1, routed) 2.090 2.347 u_confreg/dip_sw_IBUF[18] - SLICE_X8Y87 LUT5 (Prop_lut5_I4_O) 0.045 2.392 r u_confreg/s_rdata[18]_i_4/O - net (fo=1, routed) 0.229 2.621 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 - SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.045 2.666 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O - net (fo=1, routed) 0.000 2.666 u_confreg/u_int_ctrl_n_13 - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.968 -0.340 u_confreg/sys_clk - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/C + net (fo=35652, routed) 1.076 -0.232 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C Slack: inf Source: dip_sw[29] @@ -31096,10 +45686,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.680ns (logic 0.336ns (12.535%) route 2.344ns (87.465%)) + Data Path Delay: 2.665ns (logic 0.336ns (12.609%) route 2.329ns (87.391%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns + Clock Path Skew: -0.309ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -31108,12 +45698,12 @@ Slack: inf T5 0.000 0.000 r dip_sw[29] (IN) net (fo=0) 0.000 0.000 dip_sw[29] T5 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[29]_inst/O - net (fo=1, routed) 1.991 2.237 u_confreg/dip_sw_IBUF[29] - SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.045 2.282 r u_confreg/s_rdata[29]_i_4/O - net (fo=1, routed) 0.353 2.635 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 - SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.680 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O - net (fo=1, routed) 0.000 2.680 u_confreg/u_int_ctrl_n_2 - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/D + net (fo=1, routed) 2.278 2.524 u_confreg/dip_sw_IBUF[29] + SLICE_X5Y59 LUT5 (Prop_lut5_I4_O) 0.045 2.569 r u_confreg/s_rdata[29]_i_4/O + net (fo=1, routed) 0.050 2.620 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 + SLICE_X5Y59 LUT6 (Prop_lut6_I4_O) 0.045 2.665 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O + net (fo=1, routed) 0.000 2.665 u_confreg/u_int_ctrl_n_2 + SLICE_X5Y59 FDRE r u_confreg/s_rdata_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31125,34 +45715,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_confreg/sys_clk - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/C + net (fo=35652, routed) 0.999 -0.309 u_confreg/sys_clk + SLICE_X5Y59 FDRE r u_confreg/s_rdata_reg[29]/C Slack: inf - Source: dip_sw[12] + Source: dip_sw[16] (input port) - Destination: u_confreg/s_rdata_reg[12]/D + Destination: u_confreg/s_rdata_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.685ns (logic 0.327ns (12.182%) route 2.358ns (87.818%)) + Data Path Delay: 3.200ns (logic 0.358ns (11.179%) route 2.842ns (88.821%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.315ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.315ns + Clock Path Skew: -0.306ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - M5 0.000 0.000 r dip_sw[12] (IN) - net (fo=0) 0.000 0.000 dip_sw[12] - M5 IBUF (Prop_ibuf_I_O) 0.237 0.237 r dip_sw_IBUF[12]_inst/O - net (fo=1, routed) 2.193 2.430 u_confreg/dip_sw_IBUF[12] - SLICE_X5Y86 LUT5 (Prop_lut5_I4_O) 0.045 2.475 r u_confreg/s_rdata[12]_i_4/O - net (fo=1, routed) 0.165 2.640 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 - SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.045 2.685 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O - net (fo=1, routed) 0.000 2.685 u_confreg/u_int_ctrl_n_19 - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/D + K2 0.000 0.000 r dip_sw[16] (IN) + net (fo=0) 0.000 0.000 dip_sw[16] + K2 IBUF (Prop_ibuf_I_O) 0.268 0.268 r dip_sw_IBUF[16]_inst/O + net (fo=1, routed) 2.701 2.969 u_confreg/dip_sw_IBUF[16] + SLICE_X1Y56 LUT5 (Prop_lut5_I4_O) 0.045 3.014 r u_confreg/s_rdata[16]_i_4/O + net (fo=1, routed) 0.142 3.155 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 + SLICE_X1Y54 LUT6 (Prop_lut6_I4_O) 0.045 3.200 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O + net (fo=1, routed) 0.000 3.200 u_confreg/u_int_ctrl_n_15 + SLICE_X1Y54 FDRE r u_confreg/s_rdata_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31164,34 +45754,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.993 -0.315 u_confreg/sys_clk - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/C + net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk + SLICE_X1Y54 FDRE r u_confreg/s_rdata_reg[16]/C Slack: inf - Source: dip_sw[7] + Source: dip_sw[11] (input port) - Destination: u_confreg/s_rdata_reg[7]/D + Destination: u_confreg/s_rdata_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.753ns (logic 0.329ns (11.958%) route 2.424ns (88.042%)) + Data Path Delay: 3.265ns (logic 0.329ns (10.081%) route 2.936ns (89.919%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.312ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns + Clock Path Skew: -0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.335ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - N6 0.000 0.000 r dip_sw[7] (IN) - net (fo=0) 0.000 0.000 dip_sw[7] - N6 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[7]_inst/O - net (fo=1, routed) 2.373 2.612 u_confreg/dip_sw_IBUF[7] - SLICE_X1Y84 LUT5 (Prop_lut5_I4_O) 0.045 2.657 r u_confreg/s_rdata[7]_i_4/O - net (fo=1, routed) 0.051 2.708 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 - SLICE_X1Y84 LUT6 (Prop_lut6_I4_O) 0.045 2.753 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O - net (fo=1, routed) 0.000 2.753 u_confreg/u_int_ctrl_n_24 - SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/D + L7 0.000 0.000 r dip_sw[11] (IN) + net (fo=0) 0.000 0.000 dip_sw[11] + L7 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[11]_inst/O + net (fo=1, routed) 2.885 3.124 u_confreg/dip_sw_IBUF[11] + SLICE_X9Y51 LUT5 (Prop_lut5_I4_O) 0.045 3.169 r u_confreg/s_rdata[11]_i_4/O + net (fo=1, routed) 0.051 3.220 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 + SLICE_X9Y51 LUT6 (Prop_lut6_I4_O) 0.045 3.265 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O + net (fo=1, routed) 0.000 3.265 u_confreg/u_int_ctrl_n_20 + SLICE_X9Y51 FDRE r u_confreg/s_rdata_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31203,8 +45793,550 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.996 -0.312 u_confreg/sys_clk - SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/C + net (fo=35652, routed) 0.973 -0.335 u_confreg/sys_clk + SLICE_X9Y51 FDRE r u_confreg/s_rdata_reg[11]/C + +Slack: inf + Source: dip_sw[13] + (input port) + Destination: u_confreg/s_rdata_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.266ns (logic 0.344ns (10.521%) route 2.922ns (89.479%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.335ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K3 0.000 0.000 r dip_sw[13] (IN) + net (fo=0) 0.000 0.000 dip_sw[13] + K3 IBUF (Prop_ibuf_I_O) 0.254 0.254 r dip_sw_IBUF[13]_inst/O + net (fo=1, routed) 2.784 3.038 u_confreg/dip_sw_IBUF[13] + SLICE_X10Y52 LUT5 (Prop_lut5_I4_O) 0.045 3.083 r u_confreg/s_rdata[13]_i_4/O + net (fo=1, routed) 0.138 3.221 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 + SLICE_X11Y52 LUT6 (Prop_lut6_I4_O) 0.045 3.266 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O + net (fo=1, routed) 0.000 3.266 u_confreg/u_int_ctrl_n_18 + SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.973 -0.335 u_confreg/sys_clk + SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[13]/C + +Slack: inf + Source: dip_sw[0] + (input port) + Destination: u_confreg/s_rdata_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.268ns (logic 0.353ns (10.796%) route 2.915ns (89.204%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T3 0.000 0.000 r dip_sw[0] (IN) + net (fo=0) 0.000 0.000 dip_sw[0] + T3 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[0]_inst/O + net (fo=1, routed) 2.694 2.957 u_confreg/dip_sw_IBUF[0] + SLICE_X8Y54 LUT5 (Prop_lut5_I4_O) 0.045 3.002 r u_confreg/s_rdata[0]_i_4/O + net (fo=1, routed) 0.220 3.223 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 + SLICE_X8Y54 LUT6 (Prop_lut6_I4_O) 0.045 3.268 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O + net (fo=1, routed) 0.000 3.268 u_confreg/u_int_ctrl_n_31 + SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.972 -0.336 u_confreg/sys_clk + SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[0]/C + +Slack: inf + Source: dip_sw[6] + (input port) + Destination: u_confreg/s_rdata_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.390ns (logic 0.346ns (10.197%) route 3.045ns (89.803%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L3 0.000 0.000 r dip_sw[6] (IN) + net (fo=0) 0.000 0.000 dip_sw[6] + L3 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[6]_inst/O + net (fo=1, routed) 2.741 2.996 u_confreg/dip_sw_IBUF[6] + SLICE_X8Y59 LUT5 (Prop_lut5_I4_O) 0.045 3.041 r u_confreg/s_rdata[6]_i_4/O + net (fo=1, routed) 0.304 3.345 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 + SLICE_X8Y54 LUT6 (Prop_lut6_I4_O) 0.045 3.390 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O + net (fo=1, routed) 0.000 3.390 u_confreg/u_int_ctrl_n_25 + SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.972 -0.336 u_confreg/sys_clk + SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[6]/C + +Slack: inf + Source: dip_sw[19] + (input port) + Destination: u_confreg/s_rdata_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.414ns (logic 0.336ns (9.845%) route 3.078ns (90.155%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.338ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.338ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L4 0.000 0.000 r dip_sw[19] (IN) + net (fo=0) 0.000 0.000 dip_sw[19] + L4 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[19]_inst/O + net (fo=1, routed) 3.026 3.272 u_confreg/dip_sw_IBUF[19] + SLICE_X15Y58 LUT5 (Prop_lut5_I4_O) 0.045 3.317 r u_confreg/s_rdata[19]_i_4/O + net (fo=1, routed) 0.051 3.369 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 + SLICE_X15Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.414 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O + net (fo=1, routed) 0.000 3.414 u_confreg/u_int_ctrl_n_12 + SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.970 -0.338 u_confreg/sys_clk + SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[19]/C + +Slack: inf + Source: dip_sw[14] + (input port) + Destination: u_confreg/s_rdata_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.434ns (logic 0.373ns (10.848%) route 3.061ns (89.152%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.306ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + J1 0.000 0.000 r dip_sw[14] (IN) + net (fo=0) 0.000 0.000 dip_sw[14] + J1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r dip_sw_IBUF[14]_inst/O + net (fo=1, routed) 3.010 3.293 u_confreg/dip_sw_IBUF[14] + SLICE_X1Y53 LUT5 (Prop_lut5_I4_O) 0.045 3.338 r u_confreg/s_rdata[14]_i_4/O + net (fo=1, routed) 0.051 3.389 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 + SLICE_X1Y53 LUT6 (Prop_lut6_I4_O) 0.045 3.434 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O + net (fo=1, routed) 0.000 3.434 u_confreg/u_int_ctrl_n_17 + SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk + SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[14]/C + +Slack: inf + Source: dip_sw[10] + (input port) + Destination: u_confreg/s_rdata_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.439ns (logic 0.330ns (9.600%) route 3.109ns (90.400%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.260ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.260ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M7 0.000 0.000 r dip_sw[10] (IN) + net (fo=0) 0.000 0.000 dip_sw[10] + M7 IBUF (Prop_ibuf_I_O) 0.240 0.240 r dip_sw_IBUF[10]_inst/O + net (fo=1, routed) 3.053 3.293 u_confreg/dip_sw_IBUF[10] + SLICE_X10Y49 LUT5 (Prop_lut5_I4_O) 0.045 3.338 r u_confreg/s_rdata[10]_i_4/O + net (fo=1, routed) 0.056 3.394 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 + SLICE_X10Y49 LUT6 (Prop_lut6_I4_O) 0.045 3.439 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O + net (fo=1, routed) 0.000 3.439 u_confreg/u_int_ctrl_n_21 + SLICE_X10Y49 FDRE r u_confreg/s_rdata_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.048 -0.260 u_confreg/sys_clk + SLICE_X10Y49 FDRE r u_confreg/s_rdata_reg[10]/C + +Slack: inf + Source: dip_sw[8] + (input port) + Destination: u_confreg/s_rdata_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.468ns (logic 0.334ns (9.621%) route 3.134ns (90.379%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.335ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M6 0.000 0.000 r dip_sw[8] (IN) + net (fo=0) 0.000 0.000 dip_sw[8] + M6 IBUF (Prop_ibuf_I_O) 0.244 0.244 r dip_sw_IBUF[8]_inst/O + net (fo=1, routed) 2.855 3.099 u_confreg/dip_sw_IBUF[8] + SLICE_X11Y54 LUT5 (Prop_lut5_I4_O) 0.045 3.144 r u_confreg/s_rdata[8]_i_4/O + net (fo=1, routed) 0.279 3.423 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 + SLICE_X11Y52 LUT6 (Prop_lut6_I4_O) 0.045 3.468 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O + net (fo=1, routed) 0.000 3.468 u_confreg/u_int_ctrl_n_23 + SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.973 -0.335 u_confreg/sys_clk + SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[8]/C + +Slack: inf + Source: dip_sw[5] + (input port) + Destination: u_confreg/s_rdata_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.503ns (logic 0.328ns (9.375%) route 3.174ns (90.625%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.305ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L5 0.000 0.000 r dip_sw[5] (IN) + net (fo=0) 0.000 0.000 dip_sw[5] + L5 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[5]_inst/O + net (fo=1, routed) 3.123 3.361 u_confreg/dip_sw_IBUF[5] + SLICE_X3Y52 LUT5 (Prop_lut5_I4_O) 0.045 3.406 r u_confreg/s_rdata[5]_i_4/O + net (fo=1, routed) 0.051 3.458 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 + SLICE_X3Y52 LUT6 (Prop_lut6_I4_O) 0.045 3.503 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O + net (fo=1, routed) 0.000 3.503 u_confreg/u_int_ctrl_n_26 + SLICE_X3Y52 FDRE r u_confreg/s_rdata_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.003 -0.305 u_confreg/sys_clk + SLICE_X3Y52 FDRE r u_confreg/s_rdata_reg[5]/C + +Slack: inf + Source: dip_sw[15] + (input port) + Destination: u_confreg/s_rdata_reg[15]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.507ns (logic 0.352ns (10.034%) route 3.155ns (89.966%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.306ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L2 0.000 0.000 r dip_sw[15] (IN) + net (fo=0) 0.000 0.000 dip_sw[15] + L2 IBUF (Prop_ibuf_I_O) 0.262 0.262 r dip_sw_IBUF[15]_inst/O + net (fo=1, routed) 2.926 3.188 u_confreg/dip_sw_IBUF[15] + SLICE_X2Y53 LUT5 (Prop_lut5_I4_O) 0.045 3.233 r u_confreg/s_rdata[15]_i_4/O + net (fo=1, routed) 0.229 3.462 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 + SLICE_X2Y53 LUT6 (Prop_lut6_I4_O) 0.045 3.507 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O + net (fo=1, routed) 0.000 3.507 u_confreg/u_int_ctrl_n_16 + SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk + SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[15]/C + +Slack: inf + Source: touch_btn[2] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.530ns (logic 0.255ns (7.212%) route 3.276ns (92.788%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.340ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.340ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P3 0.000 0.000 r touch_btn[2] (IN) + net (fo=0) 0.000 0.000 touch_btn[2] + P3 IBUF (Prop_ibuf_I_O) 0.255 0.255 r touch_btn_IBUF[2]_inst/O + net (fo=1, routed) 3.276 3.530 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] + SLICE_X9Y62 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.968 -0.340 u_confreg/u_int_ctrl/sys_clk + SLICE_X9Y62 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C + +Slack: inf + Source: dip_sw[9] + (input port) + Destination: u_confreg/s_rdata_reg[9]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.537ns (logic 0.328ns (9.266%) route 3.209ns (90.734%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N7 0.000 0.000 r dip_sw[9] (IN) + net (fo=0) 0.000 0.000 dip_sw[9] + N7 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[9]_inst/O + net (fo=1, routed) 3.010 3.247 u_confreg/dip_sw_IBUF[9] + SLICE_X13Y57 LUT5 (Prop_lut5_I4_O) 0.045 3.292 r u_confreg/s_rdata[9]_i_4/O + net (fo=1, routed) 0.199 3.492 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 + SLICE_X13Y55 LUT6 (Prop_lut6_I4_O) 0.045 3.537 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O + net (fo=1, routed) 0.000 3.537 u_confreg/u_int_ctrl_n_22 + SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[9]/C + +Slack: inf + Source: dip_sw[23] + (input port) + Destination: u_confreg/s_rdata_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.560ns (logic 0.376ns (10.559%) route 3.184ns (89.441%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N1 0.000 0.000 r dip_sw[23] (IN) + net (fo=0) 0.000 0.000 dip_sw[23] + N1 IBUF (Prop_ibuf_I_O) 0.286 0.286 r dip_sw_IBUF[23]_inst/O + net (fo=1, routed) 2.820 3.106 u_confreg/dip_sw_IBUF[23] + SLICE_X15Y60 LUT5 (Prop_lut5_I4_O) 0.045 3.151 r u_confreg/s_rdata[23]_i_4/O + net (fo=1, routed) 0.365 3.515 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 + SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.045 3.560 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O + net (fo=1, routed) 0.000 3.560 u_confreg/u_int_ctrl_n_8 + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[23]/C + +Slack: inf + Source: dip_sw[2] + (input port) + Destination: u_confreg/s_rdata_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.591ns (logic 0.353ns (9.826%) route 3.238ns (90.174%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.306ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M2 0.000 0.000 r dip_sw[2] (IN) + net (fo=0) 0.000 0.000 dip_sw[2] + M2 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[2]_inst/O + net (fo=1, routed) 2.898 3.161 u_confreg/dip_sw_IBUF[2] + SLICE_X2Y56 LUT5 (Prop_lut5_I4_O) 0.045 3.206 r u_confreg/s_rdata[2]_i_4/O + net (fo=1, routed) 0.340 3.546 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 + SLICE_X2Y53 LUT6 (Prop_lut6_I4_O) 0.045 3.591 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O + net (fo=1, routed) 0.000 3.591 u_confreg/u_int_ctrl_n_29 + SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk + SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[2]/C + +Slack: inf + Source: dip_sw[17] + (input port) + Destination: u_confreg/s_rdata_reg[17]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.592ns (logic 0.362ns (10.072%) route 3.230ns (89.928%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.307ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.307ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K1 0.000 0.000 r dip_sw[17] (IN) + net (fo=0) 0.000 0.000 dip_sw[17] + K1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[17]_inst/O + net (fo=1, routed) 3.009 3.281 u_confreg/dip_sw_IBUF[17] + SLICE_X3Y58 LUT5 (Prop_lut5_I4_O) 0.045 3.326 r u_confreg/s_rdata[17]_i_4/O + net (fo=1, routed) 0.221 3.547 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 + SLICE_X3Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.592 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O + net (fo=1, routed) 0.000 3.592 u_confreg/u_int_ctrl_n_14 + SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk + SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[17]/C Slack: inf Source: dip_sw[24] @@ -31213,10 +46345,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.843ns (logic 0.324ns (11.413%) route 2.518ns (88.587%)) + Data Path Delay: 3.594ns (logic 0.324ns (9.027%) route 3.270ns (90.973%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns + Clock Path Skew: -0.338ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -31225,12 +46357,12 @@ Slack: inf P5 0.000 0.000 r dip_sw[24] (IN) net (fo=0) 0.000 0.000 dip_sw[24] P5 IBUF (Prop_ibuf_I_O) 0.234 0.234 r dip_sw_IBUF[24]_inst/O - net (fo=1, routed) 2.106 2.340 u_confreg/dip_sw_IBUF[24] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.385 r u_confreg/s_rdata[24]_i_4/O - net (fo=1, routed) 0.412 2.798 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.843 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O - net (fo=1, routed) 0.000 2.843 u_confreg/u_int_ctrl_n_7 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/D + net (fo=1, routed) 3.131 3.365 u_confreg/dip_sw_IBUF[24] + SLICE_X15Y58 LUT5 (Prop_lut5_I4_O) 0.045 3.410 r u_confreg/s_rdata[24]_i_4/O + net (fo=1, routed) 0.139 3.549 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 + SLICE_X15Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.594 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O + net (fo=1, routed) 0.000 3.594 u_confreg/u_int_ctrl_n_7 + SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31242,8 +46374,203 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/C + net (fo=35652, routed) 0.970 -0.338 u_confreg/sys_clk + SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[24]/C + +Slack: inf + Source: dip_sw[12] + (input port) + Destination: u_confreg/s_rdata_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.598ns (logic 0.327ns (9.090%) route 3.271ns (90.910%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M5 0.000 0.000 r dip_sw[12] (IN) + net (fo=0) 0.000 0.000 dip_sw[12] + M5 IBUF (Prop_ibuf_I_O) 0.237 0.237 r dip_sw_IBUF[12]_inst/O + net (fo=1, routed) 3.009 3.246 u_confreg/dip_sw_IBUF[12] + SLICE_X14Y57 LUT5 (Prop_lut5_I4_O) 0.045 3.291 r u_confreg/s_rdata[12]_i_4/O + net (fo=1, routed) 0.262 3.553 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 + SLICE_X13Y56 LUT6 (Prop_lut6_I4_O) 0.045 3.598 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O + net (fo=1, routed) 0.000 3.598 u_confreg/u_int_ctrl_n_19 + SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[12]/C + +Slack: inf + Source: dip_sw[1] + (input port) + Destination: u_confreg/s_rdata_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.716ns (logic 0.355ns (9.565%) route 3.361ns (90.435%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.307ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.307ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + J3 0.000 0.000 r dip_sw[1] (IN) + net (fo=0) 0.000 0.000 dip_sw[1] + J3 IBUF (Prop_ibuf_I_O) 0.265 0.265 r dip_sw_IBUF[1]_inst/O + net (fo=1, routed) 3.093 3.358 u_confreg/dip_sw_IBUF[1] + SLICE_X5Y51 LUT5 (Prop_lut5_I4_O) 0.045 3.403 r u_confreg/s_rdata[1]_i_4/O + net (fo=1, routed) 0.268 3.671 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 + SLICE_X5Y50 LUT6 (Prop_lut6_I4_O) 0.045 3.716 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O + net (fo=1, routed) 0.000 3.716 u_confreg/u_int_ctrl_n_30 + SLICE_X5Y50 FDRE r u_confreg/s_rdata_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk + SLICE_X5Y50 FDRE r u_confreg/s_rdata_reg[1]/C + +Slack: inf + Source: dip_sw[20] + (input port) + Destination: u_confreg/s_rdata_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.770ns (logic 0.333ns (8.832%) route 3.437ns (91.168%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.307ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.307ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M4 0.000 0.000 r dip_sw[20] (IN) + net (fo=0) 0.000 0.000 dip_sw[20] + M4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r dip_sw_IBUF[20]_inst/O + net (fo=1, routed) 3.269 3.512 u_confreg/dip_sw_IBUF[20] + SLICE_X1Y61 LUT5 (Prop_lut5_I4_O) 0.045 3.557 r u_confreg/s_rdata[20]_i_4/O + net (fo=1, routed) 0.168 3.725 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 + SLICE_X1Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.770 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O + net (fo=1, routed) 0.000 3.770 u_confreg/u_int_ctrl_n_11 + SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk + SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[20]/C + +Slack: inf + Source: dip_sw[26] + (input port) + Destination: u_confreg/s_rdata_reg[26]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.868ns (logic 0.367ns (9.485%) route 3.501ns (90.515%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.307ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.307ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T4 0.000 0.000 r dip_sw[26] (IN) + net (fo=0) 0.000 0.000 dip_sw[26] + T4 IBUF (Prop_ibuf_I_O) 0.277 0.277 r dip_sw_IBUF[26]_inst/O + net (fo=1, routed) 3.288 3.565 u_confreg/dip_sw_IBUF[26] + SLICE_X1Y58 LUT5 (Prop_lut5_I4_O) 0.045 3.610 r u_confreg/s_rdata[26]_i_4/O + net (fo=1, routed) 0.213 3.823 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 + SLICE_X1Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.868 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O + net (fo=1, routed) 0.000 3.868 u_confreg/u_int_ctrl_n_5 + SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk + SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[26]/C + +Slack: inf + Source: dip_sw[3] + (input port) + Destination: u_confreg/s_rdata_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.879ns (logic 0.362ns (9.330%) route 3.517ns (90.670%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.307ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.307ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P1 0.000 0.000 r dip_sw[3] (IN) + net (fo=0) 0.000 0.000 dip_sw[3] + P1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[3]_inst/O + net (fo=1, routed) 3.459 3.731 u_confreg/dip_sw_IBUF[3] + SLICE_X4Y51 LUT5 (Prop_lut5_I4_O) 0.045 3.776 r u_confreg/s_rdata[3]_i_4/O + net (fo=1, routed) 0.059 3.834 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 + SLICE_X4Y51 LUT6 (Prop_lut6_I4_O) 0.045 3.879 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O + net (fo=1, routed) 0.000 3.879 u_confreg/u_int_ctrl_n_28 + SLICE_X4Y51 FDRE r u_confreg/s_rdata_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk + SLICE_X4Y51 FDRE r u_confreg/s_rdata_reg[3]/C Slack: inf Source: touch_btn[1] @@ -31252,7 +46579,7 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.881ns (logic 0.283ns (9.807%) route 2.599ns (90.193%)) + Data Path Delay: 3.995ns (logic 0.283ns (7.072%) route 3.713ns (92.928%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns @@ -31264,8 +46591,8 @@ Slack: inf M1 0.000 0.000 r touch_btn[1] (IN) net (fo=0) 0.000 0.000 touch_btn[1] M1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r touch_btn_IBUF[1]_inst/O - net (fo=1, routed) 2.599 2.881 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D + net (fo=1, routed) 3.713 3.995 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] + SLICE_X15Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31277,125 +46604,8 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_confreg/u_int_ctrl/sys_clk - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C - -Slack: inf - Source: dip_sw[3] - (input port) - Destination: u_confreg/s_rdata_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.900ns (logic 0.362ns (12.483%) route 2.538ns (87.517%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.319ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.319ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P1 0.000 0.000 r dip_sw[3] (IN) - net (fo=0) 0.000 0.000 dip_sw[3] - P1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[3]_inst/O - net (fo=1, routed) 2.197 2.469 u_confreg/dip_sw_IBUF[3] - SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.514 r u_confreg/s_rdata[3]_i_4/O - net (fo=1, routed) 0.340 2.855 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 - SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.045 2.900 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O - net (fo=1, routed) 0.000 2.900 u_confreg/u_int_ctrl_n_28 - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.989 -0.319 u_confreg/sys_clk - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/C - -Slack: inf - Source: dip_sw[16] - (input port) - Destination: u_confreg/s_rdata_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.965ns (logic 0.358ns (12.066%) route 2.607ns (87.934%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K2 0.000 0.000 r dip_sw[16] (IN) - net (fo=0) 0.000 0.000 dip_sw[16] - K2 IBUF (Prop_ibuf_I_O) 0.268 0.268 r dip_sw_IBUF[16]_inst/O - net (fo=1, routed) 2.496 2.764 u_confreg/dip_sw_IBUF[16] - SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.045 2.809 r u_confreg/s_rdata[16]_i_4/O - net (fo=1, routed) 0.111 2.920 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.965 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O - net (fo=1, routed) 0.000 2.965 u_confreg/u_int_ctrl_n_15 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/C - -Slack: inf - Source: dip_sw[0] - (input port) - Destination: u_confreg/s_rdata_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.973ns (logic 0.353ns (11.866%) route 2.620ns (88.134%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.316ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.316ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T3 0.000 0.000 r dip_sw[0] (IN) - net (fo=0) 0.000 0.000 dip_sw[0] - T3 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[0]_inst/O - net (fo=1, routed) 2.278 2.541 u_confreg/dip_sw_IBUF[0] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.586 r u_confreg/s_rdata[0]_i_4/O - net (fo=1, routed) 0.342 2.928 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 - SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.045 2.973 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O - net (fo=1, routed) 0.000 2.973 u_confreg/u_int_ctrl_n_31 - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.992 -0.316 u_confreg/sys_clk - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/C + net (fo=35652, routed) 0.969 -0.339 u_confreg/u_int_ctrl/sys_clk + SLICE_X15Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C Slack: inf Source: touch_btn[3] @@ -31404,10 +46614,10 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.974ns (logic 0.280ns (9.424%) route 2.694ns (90.576%)) + Data Path Delay: 4.065ns (logic 0.280ns (6.894%) route 3.785ns (93.106%)) Logic Levels: 1 (IBUF=1) - Clock Path Skew: -0.317ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.317ns + Clock Path Skew: -0.338ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -31416,8 +46626,8 @@ Slack: inf U2 0.000 0.000 r touch_btn[3] (IN) net (fo=0) 0.000 0.000 touch_btn[3] U2 IBUF (Prop_ibuf_I_O) 0.280 0.280 r touch_btn_IBUF[3]_inst/O - net (fo=1, routed) 2.694 2.974 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] - SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D + net (fo=1, routed) 3.785 4.065 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] + SLICE_X10Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31429,34 +46639,30 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.991 -0.317 u_confreg/u_int_ctrl/sys_clk - SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C + net (fo=35652, routed) 0.970 -0.338 u_confreg/u_int_ctrl/sys_clk + SLICE_X10Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C Slack: inf - Source: dip_sw[14] + Source: touch_btn[0] (input port) - Destination: u_confreg/s_rdata_reg[14]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.984ns (logic 0.373ns (12.482%) route 2.612ns (87.518%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns + Data Path Delay: 4.085ns (logic 0.267ns (6.527%) route 3.818ns (93.473%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - J1 0.000 0.000 r dip_sw[14] (IN) - net (fo=0) 0.000 0.000 dip_sw[14] - J1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r dip_sw_IBUF[14]_inst/O - net (fo=1, routed) 2.273 2.555 u_confreg/dip_sw_IBUF[14] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.600 r u_confreg/s_rdata[14]_i_4/O - net (fo=1, routed) 0.339 2.939 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.984 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O - net (fo=1, routed) 0.000 2.984 u_confreg/u_int_ctrl_n_17 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/D + T2 0.000 0.000 r touch_btn[0] (IN) + net (fo=0) 0.000 0.000 touch_btn[0] + T2 IBUF (Prop_ibuf_I_O) 0.267 0.267 r touch_btn_IBUF[0]_inst/O + net (fo=1, routed) 3.818 4.085 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] + SLICE_X8Y57 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31468,8 +46674,118 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/C + net (fo=35652, routed) 0.971 -0.337 u_confreg/u_int_ctrl/sys_clk + SLICE_X8Y57 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C + +Slack: inf +======= +>>>>>>> Stashed changes + Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) +<<<<<<< Updated upstream + Data Path Delay: 4.205ns (logic 0.045ns (1.070%) route 4.160ns (98.930%)) + Logic Levels: 1 (LUT1=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns +======= + Data Path Delay: 1.811ns (logic 0.045ns (2.485%) route 1.766ns (97.515%)) + Logic Levels: 1 (LUT1=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED +<<<<<<< Updated upstream + net (fo=1, routed) 3.932 3.932 pll_clk.u_rst_sys/locked + SLICE_X106Y69 LUT1 (Prop_lut1_I0_O) 0.045 3.977 f pll_clk.u_rst_sys/delay[1]_i_1/O + net (fo=2, routed) 0.228 4.205 pll_clk.u_rst_sys/delay[1]_i_1_n_0 + SLICE_X106Y69 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR +======= + net (fo=1, routed) 1.592 1.592 pll_clk.u_rst_sys/locked + SLICE_X22Y139 LUT1 (Prop_lut1_I0_O) 0.045 1.637 f pll_clk.u_rst_sys/delay[1]_i_1/O + net (fo=2, routed) 0.174 1.811 pll_clk.u_rst_sys/delay[1]_i_1_n_0 + SLICE_X22Y139 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.922 -0.386 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C +======= + net (fo=9971, routed) 0.896 -0.412 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C +>>>>>>> Stashed changes + +Slack: inf + Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) +<<<<<<< Updated upstream + Data Path Delay: 4.205ns (logic 0.045ns (1.070%) route 4.160ns (98.930%)) + Logic Levels: 1 (LUT1=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns +======= + Data Path Delay: 1.811ns (logic 0.045ns (2.485%) route 1.766ns (97.515%)) + Logic Levels: 1 (LUT1=1) + Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.165ns +>>>>>>> Stashed changes + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED +<<<<<<< Updated upstream + net (fo=1, routed) 3.932 3.932 pll_clk.u_rst_sys/locked + SLICE_X106Y69 LUT1 (Prop_lut1_I0_O) 0.045 3.977 f pll_clk.u_rst_sys/delay[1]_i_1/O + net (fo=2, routed) 0.228 4.205 pll_clk.u_rst_sys/delay[1]_i_1_n_0 + SLICE_X106Y69 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR +======= + net (fo=1, routed) 1.592 1.592 pll_clk.u_rst_sys/locked + SLICE_X22Y139 LUT1 (Prop_lut1_I0_O) 0.045 1.637 f pll_clk.u_rst_sys/delay[1]_i_1/O + net (fo=2, routed) 0.174 1.811 pll_clk.u_rst_sys/delay[1]_i_1_n_0 + SLICE_X22Y139 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.922 -0.386 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C Slack: inf Source: dip_sw[21] @@ -31478,10 +46794,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.997ns (logic 0.346ns (11.544%) route 2.651ns (88.456%)) + Data Path Delay: 4.217ns (logic 0.346ns (8.203%) route 3.871ns (91.797%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.338ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -31490,12 +46806,12 @@ Slack: inf N2 0.000 0.000 r dip_sw[21] (IN) net (fo=0) 0.000 0.000 dip_sw[21] N2 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[21]_inst/O - net (fo=1, routed) 2.278 2.534 u_confreg/dip_sw_IBUF[21] - SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.579 r u_confreg/s_rdata[21]_i_4/O - net (fo=1, routed) 0.373 2.952 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.997 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O - net (fo=1, routed) 0.000 2.997 u_confreg/u_int_ctrl_n_10 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/D + net (fo=1, routed) 3.762 4.018 u_confreg/dip_sw_IBUF[21] + SLICE_X12Y56 LUT5 (Prop_lut5_I4_O) 0.045 4.063 r u_confreg/s_rdata[21]_i_4/O + net (fo=1, routed) 0.110 4.172 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 + SLICE_X13Y56 LUT6 (Prop_lut6_I4_O) 0.045 4.217 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O + net (fo=1, routed) 0.000 4.217 u_confreg/u_int_ctrl_n_10 + SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31507,34 +46823,54 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/C + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[21]/C +======= + net (fo=9971, routed) 0.896 -0.412 pll_clk.u_rst_sys/sys_clk + SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C +>>>>>>> Stashed changes Slack: inf - Source: dip_sw[6] + Source: dip_sw[31] (input port) - Destination: u_confreg/s_rdata_reg[6]/D + Destination: u_confreg/s_rdata_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.000ns (logic 0.346ns (11.523%) route 2.655ns (88.477%)) +<<<<<<< Updated upstream + Data Path Delay: 4.251ns (logic 0.351ns (8.267%) route 3.899ns (91.733%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.315ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.315ns + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns +======= + Data Path Delay: 2.161ns (logic 0.351ns (16.258%) route 1.810ns (83.742%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.454ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.454ns +>>>>>>> Stashed changes Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - L3 0.000 0.000 r dip_sw[6] (IN) - net (fo=0) 0.000 0.000 dip_sw[6] - L3 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[6]_inst/O - net (fo=1, routed) 2.297 2.553 u_confreg/dip_sw_IBUF[6] - SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.598 r u_confreg/s_rdata[6]_i_4/O - net (fo=1, routed) 0.358 2.955 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 - SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.045 3.000 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O - net (fo=1, routed) 0.000 3.000 u_confreg/u_int_ctrl_n_25 - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/D + R2 0.000 0.000 r dip_sw[31] (IN) + net (fo=0) 0.000 0.000 dip_sw[31] + R2 IBUF (Prop_ibuf_I_O) 0.261 0.261 r dip_sw_IBUF[31]_inst/O +<<<<<<< Updated upstream + net (fo=1, routed) 3.787 4.048 u_confreg/dip_sw_IBUF[31] + SLICE_X9Y61 LUT5 (Prop_lut5_I4_O) 0.045 4.093 r u_confreg/s_rdata[31]_i_6/O + net (fo=1, routed) 0.112 4.206 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 + SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.045 4.251 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O + net (fo=1, routed) 0.000 4.251 u_confreg/u_int_ctrl_n_0 + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[31]/D +======= + net (fo=1, routed) 1.699 1.960 u_confreg/dip_sw_IBUF[31] + SLICE_X59Y137 LUT5 (Prop_lut5_I4_O) 0.045 2.005 r u_confreg/s_rdata[31]_i_6/O + net (fo=1, routed) 0.111 2.116 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 + SLICE_X57Y137 LUT6 (Prop_lut6_I4_O) 0.045 2.161 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O + net (fo=1, routed) 0.000 2.161 u_confreg/u_int_ctrl_n_0 + SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[31]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31546,242 +46882,24 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.993 -0.315 u_confreg/sys_clk - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[31]/C Slack: inf - Source: dip_sw[26] + Source: dip_sw[18] (input port) - Destination: u_confreg/s_rdata_reg[26]/D + Destination: u_confreg/s_rdata_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.025ns (logic 0.367ns (12.128%) route 2.658ns (87.872%)) + Data Path Delay: 4.259ns (logic 0.347ns (8.145%) route 3.912ns (91.855%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.340ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.340ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T4 0.000 0.000 r dip_sw[26] (IN) - net (fo=0) 0.000 0.000 dip_sw[26] - T4 IBUF (Prop_ibuf_I_O) 0.277 0.277 r dip_sw_IBUF[26]_inst/O - net (fo=1, routed) 2.208 2.485 u_confreg/dip_sw_IBUF[26] - SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.530 r u_confreg/s_rdata[26]_i_4/O - net (fo=1, routed) 0.450 2.980 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 - SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.045 3.025 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O - net (fo=1, routed) 0.000 3.025 u_confreg/u_int_ctrl_n_5 - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.968 -0.340 u_confreg/sys_clk - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/C - -Slack: inf - Source: dip_sw[10] - (input port) - Destination: u_confreg/s_rdata_reg[10]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.067ns (logic 0.330ns (10.763%) route 2.737ns (89.237%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.345ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M7 0.000 0.000 r dip_sw[10] (IN) - net (fo=0) 0.000 0.000 dip_sw[10] - M7 IBUF (Prop_ibuf_I_O) 0.240 0.240 r dip_sw_IBUF[10]_inst/O - net (fo=1, routed) 2.590 2.830 u_confreg/dip_sw_IBUF[10] - SLICE_X8Y80 LUT5 (Prop_lut5_I4_O) 0.045 2.875 r u_confreg/s_rdata[10]_i_4/O - net (fo=1, routed) 0.147 3.022 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 3.067 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O - net (fo=1, routed) 0.000 3.067 u_confreg/u_int_ctrl_n_21 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/C - -Slack: inf - Source: dip_sw[15] - (input port) - Destination: u_confreg/s_rdata_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.091ns (logic 0.352ns (11.385%) route 2.739ns (88.615%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L2 0.000 0.000 r dip_sw[15] (IN) - net (fo=0) 0.000 0.000 dip_sw[15] - L2 IBUF (Prop_ibuf_I_O) 0.262 0.262 r dip_sw_IBUF[15]_inst/O - net (fo=1, routed) 2.453 2.715 u_confreg/dip_sw_IBUF[15] - SLICE_X1Y95 LUT5 (Prop_lut5_I4_O) 0.045 2.760 r u_confreg/s_rdata[15]_i_4/O - net (fo=1, routed) 0.285 3.046 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 3.091 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O - net (fo=1, routed) 0.000 3.091 u_confreg/u_int_ctrl_n_16 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/C - -Slack: inf - Source: dip_sw[5] - (input port) - Destination: u_confreg/s_rdata_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.122ns (logic 0.328ns (10.518%) route 2.794ns (89.482%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.345ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L5 0.000 0.000 r dip_sw[5] (IN) - net (fo=0) 0.000 0.000 dip_sw[5] - L5 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[5]_inst/O - net (fo=1, routed) 2.365 2.604 u_confreg/dip_sw_IBUF[5] - SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.045 2.649 r u_confreg/s_rdata[5]_i_4/O - net (fo=1, routed) 0.428 3.077 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 3.122 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O - net (fo=1, routed) 0.000 3.122 u_confreg/u_int_ctrl_n_26 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/C - -Slack: inf - Source: dip_sw[2] - (input port) - Destination: u_confreg/s_rdata_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.123ns (logic 0.353ns (11.299%) route 2.770ns (88.701%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.345ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M2 0.000 0.000 r dip_sw[2] (IN) - net (fo=0) 0.000 0.000 dip_sw[2] - M2 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[2]_inst/O - net (fo=1, routed) 2.335 2.598 u_confreg/dip_sw_IBUF[2] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.643 r u_confreg/s_rdata[2]_i_4/O - net (fo=1, routed) 0.435 3.078 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 3.123 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O - net (fo=1, routed) 0.000 3.123 u_confreg/u_int_ctrl_n_29 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/C - -Slack: inf - Source: dip_sw[17] - (input port) - Destination: u_confreg/s_rdata_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.171ns (logic 0.362ns (11.408%) route 2.809ns (88.593%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K1 0.000 0.000 r dip_sw[17] (IN) - net (fo=0) 0.000 0.000 dip_sw[17] - K1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[17]_inst/O - net (fo=1, routed) 2.515 2.787 u_confreg/dip_sw_IBUF[17] - SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.832 r u_confreg/s_rdata[17]_i_4/O - net (fo=1, routed) 0.294 3.126 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.045 3.171 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O - net (fo=1, routed) 0.000 3.171 u_confreg/u_int_ctrl_n_14 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/C + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns +======= + net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk + SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[31]/C Slack: inf Source: dip_sw[23] @@ -31790,24 +46908,37 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.218ns (logic 0.376ns (11.683%) route 2.842ns (88.317%)) + Data Path Delay: 2.220ns (logic 0.376ns (16.930%) route 1.845ns (83.070%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.338ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns + Clock Path Skew: -0.452ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns +>>>>>>> Stashed changes Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + N3 0.000 0.000 r dip_sw[18] (IN) + net (fo=0) 0.000 0.000 dip_sw[18] + N3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[18]_inst/O + net (fo=1, routed) 3.633 3.889 u_confreg/dip_sw_IBUF[18] + SLICE_X13Y57 LUT5 (Prop_lut5_I4_O) 0.045 3.934 r u_confreg/s_rdata[18]_i_4/O + net (fo=1, routed) 0.279 4.214 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 + SLICE_X13Y55 LUT6 (Prop_lut6_I4_O) 0.045 4.259 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O + net (fo=1, routed) 0.000 4.259 u_confreg/u_int_ctrl_n_13 + SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[18]/D +======= N1 0.000 0.000 r dip_sw[23] (IN) net (fo=0) 0.000 0.000 dip_sw[23] N1 IBUF (Prop_ibuf_I_O) 0.286 0.286 r dip_sw_IBUF[23]_inst/O - net (fo=1, routed) 2.402 2.688 u_confreg/dip_sw_IBUF[23] - SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.733 r u_confreg/s_rdata[23]_i_4/O - net (fo=1, routed) 0.440 3.173 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 3.218 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O - net (fo=1, routed) 0.000 3.218 u_confreg/u_int_ctrl_n_8 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/D + net (fo=1, routed) 1.603 1.889 u_confreg/dip_sw_IBUF[23] + SLICE_X51Y139 LUT5 (Prop_lut5_I4_O) 0.045 1.934 r u_confreg/s_rdata[23]_i_4/O + net (fo=1, routed) 0.241 2.175 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 + SLICE_X50Y139 LUT6 (Prop_lut6_I4_O) 0.045 2.220 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O + net (fo=1, routed) 0.000 2.220 u_confreg/u_int_ctrl_n_8 + SLICE_X50Y139 FDRE r u_confreg/s_rdata_reg[23]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31819,34 +46950,171 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[18]/C Slack: inf - Source: dip_sw[4] + Source: dip_sw[30] (input port) - Destination: u_confreg/s_rdata_reg[4]/D + Destination: u_confreg/s_rdata_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.278ns (logic 0.346ns (10.553%) route 2.932ns (89.447%)) + Data Path Delay: 4.355ns (logic 0.317ns (7.282%) route 4.038ns (92.718%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.313ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.313ns + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- + R6 0.000 0.000 r dip_sw[30] (IN) + net (fo=0) 0.000 0.000 dip_sw[30] + R6 IBUF (Prop_ibuf_I_O) 0.227 0.227 r dip_sw_IBUF[30]_inst/O + net (fo=1, routed) 3.935 4.162 u_confreg/dip_sw_IBUF[30] + SLICE_X9Y60 LUT5 (Prop_lut5_I4_O) 0.045 4.207 r u_confreg/s_rdata[30]_i_4/O + net (fo=1, routed) 0.103 4.310 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 + SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.045 4.355 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O + net (fo=1, routed) 0.000 4.355 u_confreg/u_int_ctrl_n_1 + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[30]/C + +Slack: inf + Source: dip_sw[22] + (input port) + Destination: u_confreg/s_rdata_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 4.425ns (logic 0.320ns (7.240%) route 4.104ns (92.760%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P6 0.000 0.000 r dip_sw[22] (IN) + net (fo=0) 0.000 0.000 dip_sw[22] + P6 IBUF (Prop_ibuf_I_O) 0.230 0.230 r dip_sw_IBUF[22]_inst/O + net (fo=1, routed) 3.963 4.193 u_confreg/dip_sw_IBUF[22] + SLICE_X9Y61 LUT5 (Prop_lut5_I4_O) 0.045 4.238 r u_confreg/s_rdata[22]_i_4/O + net (fo=1, routed) 0.142 4.380 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 + SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.045 4.425 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O + net (fo=1, routed) 0.000 4.425 u_confreg/u_int_ctrl_n_9 + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[22]/C + +Slack: inf + Source: dip_sw[7] + (input port) + Destination: u_confreg/s_rdata_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 4.560ns (logic 0.329ns (7.220%) route 4.231ns (92.780%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.306ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N6 0.000 0.000 r dip_sw[7] (IN) + net (fo=0) 0.000 0.000 dip_sw[7] + N6 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[7]_inst/O + net (fo=1, routed) 4.018 4.257 u_confreg/dip_sw_IBUF[7] + SLICE_X3Y56 LUT5 (Prop_lut5_I4_O) 0.045 4.302 r u_confreg/s_rdata[7]_i_4/O + net (fo=1, routed) 0.213 4.515 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 + SLICE_X3Y56 LUT6 (Prop_lut6_I4_O) 0.045 4.560 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O + net (fo=1, routed) 0.000 4.560 u_confreg/u_int_ctrl_n_24 + SLICE_X3Y56 FDRE r u_confreg/s_rdata_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk + SLICE_X3Y56 FDRE r u_confreg/s_rdata_reg[7]/C +======= + net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk + SLICE_X50Y139 FDRE r u_confreg/s_rdata_reg[23]/C +>>>>>>> Stashed changes + +Slack: inf + Source: touch_btn[1] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) +<<<<<<< Updated upstream + Data Path Delay: 4.587ns (logic 0.346ns (7.542%) route 4.241ns (92.458%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.306ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns +======= + Data Path Delay: 2.242ns (logic 0.283ns (12.603%) route 1.959ns (87.397%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.465ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.465ns +>>>>>>> Stashed changes + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream P4 0.000 0.000 r dip_sw[4] (IN) net (fo=0) 0.000 0.000 dip_sw[4] P4 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[4]_inst/O - net (fo=1, routed) 2.708 2.964 u_confreg/dip_sw_IBUF[4] - SLICE_X2Y85 LUT5 (Prop_lut5_I4_O) 0.045 3.009 r u_confreg/s_rdata[4]_i_4/O - net (fo=1, routed) 0.224 3.233 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 - SLICE_X2Y83 LUT6 (Prop_lut6_I4_O) 0.045 3.278 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O - net (fo=1, routed) 0.000 3.278 u_confreg/u_int_ctrl_n_27 - SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/D + net (fo=1, routed) 3.727 3.983 u_confreg/dip_sw_IBUF[4] + SLICE_X0Y59 LUT5 (Prop_lut5_I4_O) 0.045 4.028 r u_confreg/s_rdata[4]_i_4/O + net (fo=1, routed) 0.514 4.542 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 + SLICE_X1Y53 LUT6 (Prop_lut6_I4_O) 0.045 4.587 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O + net (fo=1, routed) 0.000 4.587 u_confreg/u_int_ctrl_n_27 + SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[4]/D +======= + M1 0.000 0.000 r touch_btn[1] (IN) + net (fo=0) 0.000 0.000 touch_btn[1] + M1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r touch_btn_IBUF[1]_inst/O + net (fo=1, routed) 1.959 2.242 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] + SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31858,34 +47126,61 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.995 -0.313 u_confreg/sys_clk - SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk + SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[4]/C Slack: inf - Source: dip_sw[9] + Source: dip_sw[27] (input port) - Destination: u_confreg/s_rdata_reg[9]/D + Destination: u_confreg/s_rdata_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.293ns (logic 0.328ns (9.951%) route 2.965ns (90.049%)) + Data Path Delay: 4.738ns (logic 0.362ns (7.650%) route 4.375ns (92.350%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.316ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.316ns + Clock Path Skew: -0.309ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.309ns +======= + net (fo=9971, routed) 0.843 -0.465 u_confreg/u_int_ctrl/sys_clk + SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.295ns (logic 0.287ns (12.514%) route 2.008ns (87.486%)) + Logic Levels: 2 (IBUF=1 LUT5=1) + Clock Path Skew: -0.466ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.466ns +>>>>>>> Stashed changes Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - N7 0.000 0.000 r dip_sw[9] (IN) - net (fo=0) 0.000 0.000 dip_sw[9] - N7 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[9]_inst/O - net (fo=1, routed) 2.752 2.990 u_confreg/dip_sw_IBUF[9] - SLICE_X1Y80 LUT5 (Prop_lut5_I4_O) 0.045 3.035 r u_confreg/s_rdata[9]_i_4/O - net (fo=1, routed) 0.213 3.248 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 - SLICE_X1Y80 LUT6 (Prop_lut6_I4_O) 0.045 3.293 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O - net (fo=1, routed) 0.000 3.293 u_confreg/u_int_ctrl_n_22 - SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/D +<<<<<<< Updated upstream + R1 0.000 0.000 r dip_sw[27] (IN) + net (fo=0) 0.000 0.000 dip_sw[27] + R1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[27]_inst/O + net (fo=1, routed) 4.155 4.428 u_confreg/dip_sw_IBUF[27] + SLICE_X5Y58 LUT5 (Prop_lut5_I4_O) 0.045 4.473 r u_confreg/s_rdata[27]_i_4/O + net (fo=1, routed) 0.220 4.693 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 + SLICE_X5Y58 LUT6 (Prop_lut6_I4_O) 0.045 4.738 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O + net (fo=1, routed) 0.000 4.738 u_confreg/u_int_ctrl_n_4 + SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[27]/D +======= + H18 0.000 0.000 f UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 2.008 2.250 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF + SLICE_X77Y137 LUT5 (Prop_lut5_I2_O) 0.045 2.295 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O + net (fo=1, routed) 0.000 2.295 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 + SLICE_X77Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31897,30 +47192,173 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.992 -0.316 u_confreg/sys_clk - SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 0.999 -0.309 u_confreg/sys_clk + SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[27]/C +======= + net (fo=9971, routed) 0.842 -0.466 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X77Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C Slack: inf - Source: touch_btn[2] + Source: dip_sw[28] (input port) + Destination: u_confreg/s_rdata_reg[28]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.315ns (logic 0.326ns (14.065%) route 1.989ns (85.935%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.452ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R5 0.000 0.000 r dip_sw[28] (IN) + net (fo=0) 0.000 0.000 dip_sw[28] + R5 IBUF (Prop_ibuf_I_O) 0.236 0.236 r dip_sw_IBUF[28]_inst/O + net (fo=1, routed) 1.643 1.878 u_confreg/dip_sw_IBUF[28] + SLICE_X59Y139 LUT5 (Prop_lut5_I4_O) 0.045 1.923 r u_confreg/s_rdata[28]_i_4/O + net (fo=1, routed) 0.346 2.270 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 + SLICE_X52Y139 LUT6 (Prop_lut6_I4_O) 0.045 2.315 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O + net (fo=1, routed) 0.000 2.315 u_confreg/u_int_ctrl_n_3 + SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk + SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[28]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D + (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.347ns (logic 0.287ns (12.237%) route 2.060ns (87.763%)) + Logic Levels: 2 (IBUF=1 LUT4=1) + Clock Path Skew: -0.466ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.466ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 r UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 2.060 2.302 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_TX_IBUF + SLICE_X77Y137 LUT4 (Prop_lut4_I2_O) 0.045 2.347 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O + net (fo=1, routed) 0.000 2.347 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i + SLICE_X77Y137 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.842 -0.466 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk + SLICE_X77Y137 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C + +Slack: inf + Source: dip_sw[17] + (input port) + Destination: u_confreg/s_rdata_reg[17]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.367ns (logic 0.362ns (15.281%) route 2.005ns (84.719%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.455ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.455ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K1 0.000 0.000 r dip_sw[17] (IN) + net (fo=0) 0.000 0.000 dip_sw[17] + K1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[17]_inst/O + net (fo=1, routed) 1.744 2.015 u_confreg/dip_sw_IBUF[17] + SLICE_X56Y136 LUT5 (Prop_lut5_I4_O) 0.045 2.060 r u_confreg/s_rdata[17]_i_4/O + net (fo=1, routed) 0.262 2.322 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 + SLICE_X49Y136 LUT6 (Prop_lut6_I4_O) 0.045 2.367 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O + net (fo=1, routed) 0.000 2.367 u_confreg/u_int_ctrl_n_14 + SLICE_X49Y136 FDRE r u_confreg/s_rdata_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk + SLICE_X49Y136 FDRE r u_confreg/s_rdata_reg[17]/C +>>>>>>> Stashed changes + +Slack: inf + Source: dip_sw[28] + (input port) +<<<<<<< Updated upstream + Destination: u_confreg/s_rdata_reg[28]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 4.824ns (logic 0.326ns (6.749%) route 4.499ns (93.251%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.307ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.307ns +======= Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.287ns (logic 0.255ns (5.940%) route 4.032ns (94.060%)) + Data Path Delay: 2.371ns (logic 0.255ns (10.737%) route 2.117ns (89.263%)) Logic Levels: 1 (IBUF=1) - Clock Path Skew: -0.315ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.315ns + Clock Path Skew: -0.462ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.462ns +>>>>>>> Stashed changes Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- +<<<<<<< Updated upstream + R5 0.000 0.000 r dip_sw[28] (IN) + net (fo=0) 0.000 0.000 dip_sw[28] + R5 IBUF (Prop_ibuf_I_O) 0.236 0.236 r dip_sw_IBUF[28]_inst/O + net (fo=1, routed) 3.990 4.226 u_confreg/dip_sw_IBUF[28] + SLICE_X12Y58 LUT5 (Prop_lut5_I4_O) 0.045 4.271 r u_confreg/s_rdata[28]_i_4/O + net (fo=1, routed) 0.508 4.779 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 + SLICE_X3Y58 LUT6 (Prop_lut6_I4_O) 0.045 4.824 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O + net (fo=1, routed) 0.000 4.824 u_confreg/u_int_ctrl_n_3 + SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[28]/D +======= P3 0.000 0.000 r touch_btn[2] (IN) net (fo=0) 0.000 0.000 touch_btn[2] P3 IBUF (Prop_ibuf_I_O) 0.255 0.255 r touch_btn_IBUF[2]_inst/O - net (fo=1, routed) 4.032 4.287 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] - SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D + net (fo=1, routed) 2.117 2.371 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] + SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D +>>>>>>> Stashed changes ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31932,86 +47370,12 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.993 -0.315 u_confreg/u_int_ctrl/sys_clk - SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C - -Slack: inf - Source: dip_sw[19] - (input port) - Destination: u_confreg/s_rdata_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.396ns (logic 0.336ns (7.645%) route 4.060ns (92.355%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.313ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.313ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L4 0.000 0.000 r dip_sw[19] (IN) - net (fo=0) 0.000 0.000 dip_sw[19] - L4 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[19]_inst/O - net (fo=1, routed) 4.009 4.255 u_confreg/dip_sw_IBUF[19] - SLICE_X7Y86 LUT5 (Prop_lut5_I4_O) 0.045 4.300 r u_confreg/s_rdata[19]_i_4/O - net (fo=1, routed) 0.051 4.351 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 - SLICE_X7Y86 LUT6 (Prop_lut6_I4_O) 0.045 4.396 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O - net (fo=1, routed) 0.000 4.396 u_confreg/u_int_ctrl_n_12 - SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.995 -0.313 u_confreg/sys_clk - SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/C - -Slack: inf - Source: dip_sw[25] - (input port) - Destination: u_confreg/s_rdata_reg[25]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.440ns (logic 0.347ns (7.817%) route 4.093ns (92.183%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.338ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R3 0.000 0.000 r dip_sw[25] (IN) - net (fo=0) 0.000 0.000 dip_sw[25] - R3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[25]_inst/O - net (fo=1, routed) 3.854 4.111 u_confreg/dip_sw_IBUF[25] - SLICE_X9Y88 LUT5 (Prop_lut5_I4_O) 0.045 4.156 r u_confreg/s_rdata[25]_i_4/O - net (fo=1, routed) 0.239 4.395 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 4.440 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O - net (fo=1, routed) 0.000 4.440 u_confreg/u_int_ctrl_n_6 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/C +<<<<<<< Updated upstream + net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk + SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[28]/C +======= + net (fo=9971, routed) 0.846 -0.462 u_confreg/u_int_ctrl/sys_clk + SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C Slack: inf Source: dip_sw[11] @@ -32020,10 +47384,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.518ns (logic 0.329ns (7.286%) route 4.189ns (92.714%)) + Data Path Delay: 2.379ns (logic 0.329ns (13.836%) route 2.050ns (86.164%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.316ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.316ns + Clock Path Skew: -0.457ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -32032,12 +47396,12 @@ Slack: inf L7 0.000 0.000 r dip_sw[11] (IN) net (fo=0) 0.000 0.000 dip_sw[11] L7 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[11]_inst/O - net (fo=1, routed) 3.969 4.208 u_confreg/dip_sw_IBUF[11] - SLICE_X4Y82 LUT5 (Prop_lut5_I4_O) 0.045 4.253 r u_confreg/s_rdata[11]_i_4/O - net (fo=1, routed) 0.220 4.473 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 - SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.045 4.518 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O - net (fo=1, routed) 0.000 4.518 u_confreg/u_int_ctrl_n_20 - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/D + net (fo=1, routed) 1.819 2.059 u_confreg/dip_sw_IBUF[11] + SLICE_X60Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.104 r u_confreg/s_rdata[11]_i_4/O + net (fo=1, routed) 0.230 2.334 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 + SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.045 2.379 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O + net (fo=1, routed) 0.000 2.379 u_confreg/u_int_ctrl_n_20 + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -32049,34 +47413,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.992 -0.316 u_confreg/sys_clk - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/C + net (fo=9971, routed) 0.851 -0.457 u_confreg/sys_clk + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[11]/C Slack: inf - Source: dip_sw[13] + Source: dip_sw[9] (input port) - Destination: u_confreg/s_rdata_reg[13]/D + Destination: u_confreg/s_rdata_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.727ns (logic 0.344ns (7.270%) route 4.383ns (92.730%)) + Data Path Delay: 2.511ns (logic 0.328ns (13.048%) route 2.184ns (86.952%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns + Clock Path Skew: -0.458ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - K3 0.000 0.000 r dip_sw[13] (IN) - net (fo=0) 0.000 0.000 dip_sw[13] - K3 IBUF (Prop_ibuf_I_O) 0.254 0.254 r dip_sw_IBUF[13]_inst/O - net (fo=1, routed) 4.162 4.416 u_confreg/dip_sw_IBUF[13] - SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.045 4.461 r u_confreg/s_rdata[13]_i_4/O - net (fo=1, routed) 0.221 4.682 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 - SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.045 4.727 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O - net (fo=1, routed) 0.000 4.727 u_confreg/u_int_ctrl_n_18 - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/D + N7 0.000 0.000 r dip_sw[9] (IN) + net (fo=0) 0.000 0.000 dip_sw[9] + N7 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[9]_inst/O + net (fo=1, routed) 1.929 2.167 u_confreg/dip_sw_IBUF[9] + SLICE_X58Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.212 r u_confreg/s_rdata[9]_i_4/O + net (fo=1, routed) 0.254 2.466 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 + SLICE_X57Y132 LUT6 (Prop_lut6_I4_O) 0.045 2.511 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O + net (fo=1, routed) 0.000 2.511 u_confreg/u_int_ctrl_n_22 + SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -32088,8 +47452,232 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/C + net (fo=9971, routed) 0.850 -0.458 u_confreg/sys_clk + SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[9]/C + +Slack: inf + Source: dip_sw[30] + (input port) + Destination: u_confreg/s_rdata_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.573ns (logic 0.317ns (12.327%) route 2.256ns (87.673%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.451ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R6 0.000 0.000 r dip_sw[30] (IN) + net (fo=0) 0.000 0.000 dip_sw[30] + R6 IBUF (Prop_ibuf_I_O) 0.227 0.227 r dip_sw_IBUF[30]_inst/O + net (fo=1, routed) 2.205 2.432 u_confreg/dip_sw_IBUF[30] + SLICE_X57Y140 LUT5 (Prop_lut5_I4_O) 0.045 2.477 r u_confreg/s_rdata[30]_i_4/O + net (fo=1, routed) 0.050 2.528 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 + SLICE_X57Y140 LUT6 (Prop_lut6_I4_O) 0.045 2.573 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O + net (fo=1, routed) 0.000 2.573 u_confreg/u_int_ctrl_n_1 + SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.857 -0.451 u_confreg/sys_clk + SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[30]/C + +Slack: inf + Source: dip_sw[26] + (input port) + Destination: u_confreg/s_rdata_reg[26]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.588ns (logic 0.367ns (14.175%) route 2.221ns (85.825%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.454ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.454ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T4 0.000 0.000 r dip_sw[26] (IN) + net (fo=0) 0.000 0.000 dip_sw[26] + T4 IBUF (Prop_ibuf_I_O) 0.277 0.277 r dip_sw_IBUF[26]_inst/O + net (fo=1, routed) 1.957 2.234 u_confreg/dip_sw_IBUF[26] + SLICE_X52Y137 LUT5 (Prop_lut5_I4_O) 0.045 2.279 r u_confreg/s_rdata[26]_i_4/O + net (fo=1, routed) 0.264 2.543 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 + SLICE_X50Y137 LUT6 (Prop_lut6_I4_O) 0.045 2.588 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O + net (fo=1, routed) 0.000 2.588 u_confreg/u_int_ctrl_n_5 + SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk + SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[26]/C + +Slack: inf + Source: touch_btn[0] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.605ns (logic 0.267ns (10.235%) route 2.338ns (89.765%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.460ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.460ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T2 0.000 0.000 r touch_btn[0] (IN) + net (fo=0) 0.000 0.000 touch_btn[0] + T2 IBUF (Prop_ibuf_I_O) 0.267 0.267 r touch_btn_IBUF[0]_inst/O + net (fo=1, routed) 2.338 2.605 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] + SLICE_X60Y132 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.848 -0.460 u_confreg/u_int_ctrl/sys_clk + SLICE_X60Y132 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C + +Slack: inf + Source: dip_sw[10] + (input port) + Destination: u_confreg/s_rdata_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.611ns (logic 0.330ns (12.645%) route 2.281ns (87.355%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.455ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.455ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M7 0.000 0.000 r dip_sw[10] (IN) + net (fo=0) 0.000 0.000 dip_sw[10] + M7 IBUF (Prop_ibuf_I_O) 0.240 0.240 r dip_sw_IBUF[10]_inst/O + net (fo=1, routed) 1.737 1.977 u_confreg/dip_sw_IBUF[10] + SLICE_X62Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.022 r u_confreg/s_rdata[10]_i_4/O + net (fo=1, routed) 0.543 2.566 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 + SLICE_X55Y135 LUT6 (Prop_lut6_I4_O) 0.045 2.611 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O + net (fo=1, routed) 0.000 2.611 u_confreg/u_int_ctrl_n_21 + SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk + SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[10]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.615ns (logic 0.287ns (10.986%) route 2.328ns (89.014%)) + Logic Levels: 2 (IBUF=1 LUT5=1) + Clock Path Skew: -0.474ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.474ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 r UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 2.328 2.570 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X79Y136 LUT5 (Prop_lut5_I0_O) 0.045 2.615 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O + net (fo=1, routed) 0.000 2.615 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 + SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.834 -0.474 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C + +Slack: inf + Source: touch_btn[3] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.660ns (logic 0.280ns (10.536%) route 2.380ns (89.464%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.461ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + U2 0.000 0.000 r touch_btn[3] (IN) + net (fo=0) 0.000 0.000 touch_btn[3] + U2 IBUF (Prop_ibuf_I_O) 0.280 0.280 r touch_btn_IBUF[3]_inst/O + net (fo=1, routed) 2.380 2.660 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] + SLICE_X60Y131 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.847 -0.461 u_confreg/u_int_ctrl/sys_clk + SLICE_X60Y131 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C Slack: inf Source: dip_sw[1] @@ -32098,10 +47686,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.729ns (logic 0.355ns (7.516%) route 4.374ns (92.484%)) + Data Path Delay: 2.718ns (logic 0.355ns (13.080%) route 2.362ns (86.920%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.345ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns + Clock Path Skew: -0.457ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -32110,12 +47698,12 @@ Slack: inf J3 0.000 0.000 r dip_sw[1] (IN) net (fo=0) 0.000 0.000 dip_sw[1] J3 IBUF (Prop_ibuf_I_O) 0.265 0.265 r dip_sw_IBUF[1]_inst/O - net (fo=1, routed) 3.965 4.231 u_confreg/dip_sw_IBUF[1] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.045 4.276 r u_confreg/s_rdata[1]_i_4/O - net (fo=1, routed) 0.409 4.684 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 4.729 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O - net (fo=1, routed) 0.000 4.729 u_confreg/u_int_ctrl_n_30 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/D + net (fo=1, routed) 1.935 2.201 u_confreg/dip_sw_IBUF[1] + SLICE_X66Y141 LUT5 (Prop_lut5_I4_O) 0.045 2.246 r u_confreg/s_rdata[1]_i_4/O + net (fo=1, routed) 0.427 2.673 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 + SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.045 2.718 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O + net (fo=1, routed) 0.000 2.718 u_confreg/u_int_ctrl_n_30 + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -32127,34 +47715,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/C + net (fo=9971, routed) 0.851 -0.457 u_confreg/sys_clk + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[1]/C Slack: inf - Source: dip_sw[20] + Source: dip_sw[5] (input port) - Destination: u_confreg/s_rdata_reg[20]/D + Destination: u_confreg/s_rdata_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.977ns (logic 0.333ns (6.690%) route 4.644ns (93.310%)) + Data Path Delay: 2.769ns (logic 0.328ns (11.858%) route 2.441ns (88.142%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns + Clock Path Skew: -0.454ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.454ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - M4 0.000 0.000 r dip_sw[20] (IN) - net (fo=0) 0.000 0.000 dip_sw[20] - M4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r dip_sw_IBUF[20]_inst/O - net (fo=1, routed) 4.258 4.501 u_confreg/dip_sw_IBUF[20] - SLICE_X7Y92 LUT5 (Prop_lut5_I4_O) 0.045 4.546 r u_confreg/s_rdata[20]_i_4/O - net (fo=1, routed) 0.386 4.932 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.045 4.977 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O - net (fo=1, routed) 0.000 4.977 u_confreg/u_int_ctrl_n_11 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/D + L5 0.000 0.000 r dip_sw[5] (IN) + net (fo=0) 0.000 0.000 dip_sw[5] + L5 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[5]_inst/O + net (fo=1, routed) 2.069 2.307 u_confreg/dip_sw_IBUF[5] + SLICE_X66Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.352 r u_confreg/s_rdata[5]_i_4/O + net (fo=1, routed) 0.372 2.724 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 + SLICE_X57Y137 LUT6 (Prop_lut6_I4_O) 0.045 2.769 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O + net (fo=1, routed) 0.000 2.769 u_confreg/u_int_ctrl_n_26 + SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -32166,8 +47754,398 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/C + net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk + SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[5]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.788ns (logic 0.393ns (14.104%) route 2.395ns (85.896%)) + Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) + Clock Path Skew: -0.474ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.474ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 f UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 2.328 2.570 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X79Y136 LUT2 (Prop_lut2_I1_O) 0.044 2.614 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O + net (fo=2, routed) 0.068 2.681 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 + SLICE_X79Y136 LUT6 (Prop_lut6_I2_O) 0.107 2.788 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O + net (fo=1, routed) 0.000 2.788 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 + SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.834 -0.474 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C + +Slack: inf + Source: dip_sw[18] + (input port) + Destination: u_confreg/s_rdata_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.792ns (logic 0.347ns (12.424%) route 2.445ns (87.576%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.461ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N3 0.000 0.000 r dip_sw[18] (IN) + net (fo=0) 0.000 0.000 dip_sw[18] + N3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[18]_inst/O + net (fo=1, routed) 2.224 2.481 u_confreg/dip_sw_IBUF[18] + SLICE_X61Y129 LUT5 (Prop_lut5_I4_O) 0.045 2.526 r u_confreg/s_rdata[18]_i_4/O + net (fo=1, routed) 0.221 2.747 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 + SLICE_X48Y129 LUT6 (Prop_lut6_I4_O) 0.045 2.792 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O + net (fo=1, routed) 0.000 2.792 u_confreg/u_int_ctrl_n_13 + SLICE_X48Y129 FDRE r u_confreg/s_rdata_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.847 -0.461 u_confreg/sys_clk + SLICE_X48Y129 FDRE r u_confreg/s_rdata_reg[18]/C + +Slack: inf + Source: dip_sw[24] + (input port) + Destination: u_confreg/s_rdata_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.796ns (logic 0.324ns (11.603%) route 2.472ns (88.397%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.452ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P5 0.000 0.000 r dip_sw[24] (IN) + net (fo=0) 0.000 0.000 dip_sw[24] + P5 IBUF (Prop_ibuf_I_O) 0.234 0.234 r dip_sw_IBUF[24]_inst/O + net (fo=1, routed) 2.272 2.506 u_confreg/dip_sw_IBUF[24] + SLICE_X55Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.551 r u_confreg/s_rdata[24]_i_4/O + net (fo=1, routed) 0.200 2.751 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 + SLICE_X52Y139 LUT6 (Prop_lut6_I4_O) 0.045 2.796 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O + net (fo=1, routed) 0.000 2.796 u_confreg/u_int_ctrl_n_7 + SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk + SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[24]/C + +Slack: inf + Source: dip_sw[3] + (input port) + Destination: u_confreg/s_rdata_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.803ns (logic 0.362ns (12.912%) route 2.441ns (87.088%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.461ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P1 0.000 0.000 r dip_sw[3] (IN) + net (fo=0) 0.000 0.000 dip_sw[3] + P1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[3]_inst/O + net (fo=1, routed) 2.117 2.389 u_confreg/dip_sw_IBUF[3] + SLICE_X63Y131 LUT5 (Prop_lut5_I4_O) 0.045 2.434 r u_confreg/s_rdata[3]_i_4/O + net (fo=1, routed) 0.324 2.758 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 + SLICE_X59Y131 LUT6 (Prop_lut6_I4_O) 0.045 2.803 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O + net (fo=1, routed) 0.000 2.803 u_confreg/u_int_ctrl_n_28 + SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.847 -0.461 u_confreg/sys_clk + SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[3]/C + +Slack: inf + Source: dip_sw[2] + (input port) + Destination: u_confreg/s_rdata_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.824ns (logic 0.353ns (12.494%) route 2.472ns (87.506%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.459ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.459ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M2 0.000 0.000 r dip_sw[2] (IN) + net (fo=0) 0.000 0.000 dip_sw[2] + M2 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[2]_inst/O + net (fo=1, routed) 2.041 2.304 u_confreg/dip_sw_IBUF[2] + SLICE_X66Y131 LUT5 (Prop_lut5_I4_O) 0.045 2.349 r u_confreg/s_rdata[2]_i_4/O + net (fo=1, routed) 0.430 2.779 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 + SLICE_X56Y131 LUT6 (Prop_lut6_I4_O) 0.045 2.824 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O + net (fo=1, routed) 0.000 2.824 u_confreg/u_int_ctrl_n_29 + SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.849 -0.459 u_confreg/sys_clk + SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[2]/C + +Slack: inf + Source: dip_sw[6] + (input port) + Destination: u_confreg/s_rdata_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.873ns (logic 0.346ns (12.035%) route 2.527ns (87.965%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.458ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.458ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L3 0.000 0.000 r dip_sw[6] (IN) + net (fo=0) 0.000 0.000 dip_sw[6] + L3 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[6]_inst/O + net (fo=1, routed) 2.127 2.383 u_confreg/dip_sw_IBUF[6] + SLICE_X65Y134 LUT5 (Prop_lut5_I4_O) 0.045 2.428 r u_confreg/s_rdata[6]_i_4/O + net (fo=1, routed) 0.400 2.828 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 + SLICE_X57Y132 LUT6 (Prop_lut6_I4_O) 0.045 2.873 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O + net (fo=1, routed) 0.000 2.873 u_confreg/u_int_ctrl_n_25 + SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.850 -0.458 u_confreg/sys_clk + SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[6]/C + +Slack: inf + Source: dip_sw[21] + (input port) + Destination: u_confreg/s_rdata_reg[21]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.877ns (logic 0.346ns (12.026%) route 2.531ns (87.974%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.452ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N2 0.000 0.000 r dip_sw[21] (IN) + net (fo=0) 0.000 0.000 dip_sw[21] + N2 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[21]_inst/O + net (fo=1, routed) 2.343 2.599 u_confreg/dip_sw_IBUF[21] + SLICE_X57Y138 LUT5 (Prop_lut5_I4_O) 0.045 2.644 r u_confreg/s_rdata[21]_i_4/O + net (fo=1, routed) 0.187 2.832 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 + SLICE_X51Y138 LUT6 (Prop_lut6_I4_O) 0.045 2.877 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O + net (fo=1, routed) 0.000 2.877 u_confreg/u_int_ctrl_n_10 + SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk + SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[21]/C + +Slack: inf + Source: dip_sw[0] + (input port) + Destination: u_confreg/s_rdata_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.880ns (logic 0.353ns (12.249%) route 2.527ns (87.751%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.459ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.459ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T3 0.000 0.000 r dip_sw[0] (IN) + net (fo=0) 0.000 0.000 dip_sw[0] + T3 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[0]_inst/O + net (fo=1, routed) 2.218 2.481 u_confreg/dip_sw_IBUF[0] + SLICE_X62Y133 LUT5 (Prop_lut5_I4_O) 0.045 2.526 r u_confreg/s_rdata[0]_i_4/O + net (fo=1, routed) 0.309 2.835 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 + SLICE_X60Y133 LUT6 (Prop_lut6_I4_O) 0.045 2.880 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O + net (fo=1, routed) 0.000 2.880 u_confreg/u_int_ctrl_n_31 + SLICE_X60Y133 FDRE r u_confreg/s_rdata_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.849 -0.459 u_confreg/sys_clk + SLICE_X60Y133 FDRE r u_confreg/s_rdata_reg[0]/C + +Slack: inf + Source: dip_sw[13] + (input port) + Destination: u_confreg/s_rdata_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.890ns (logic 0.344ns (11.888%) route 2.547ns (88.112%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.457ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.457ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K3 0.000 0.000 r dip_sw[13] (IN) + net (fo=0) 0.000 0.000 dip_sw[13] + K3 IBUF (Prop_ibuf_I_O) 0.254 0.254 r dip_sw_IBUF[13]_inst/O + net (fo=1, routed) 2.319 2.572 u_confreg/dip_sw_IBUF[13] + SLICE_X58Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.617 r u_confreg/s_rdata[13]_i_4/O + net (fo=1, routed) 0.228 2.845 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 + SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.045 2.890 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O + net (fo=1, routed) 0.000 2.890 u_confreg/u_int_ctrl_n_18 + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.851 -0.457 u_confreg/sys_clk + SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[13]/C + +Slack: inf + Source: dip_sw[12] + (input port) + Destination: u_confreg/s_rdata_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.899ns (logic 0.327ns (11.281%) route 2.572ns (88.719%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.455ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.455ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M5 0.000 0.000 r dip_sw[12] (IN) + net (fo=0) 0.000 0.000 dip_sw[12] + M5 IBUF (Prop_ibuf_I_O) 0.237 0.237 r dip_sw_IBUF[12]_inst/O + net (fo=1, routed) 2.212 2.449 u_confreg/dip_sw_IBUF[12] + SLICE_X59Y137 LUT5 (Prop_lut5_I4_O) 0.045 2.494 r u_confreg/s_rdata[12]_i_4/O + net (fo=1, routed) 0.360 2.854 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 + SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.045 2.899 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O + net (fo=1, routed) 0.000 2.899 u_confreg/u_int_ctrl_n_19 + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[12]/C Slack: inf Source: dip_sw[8] @@ -32176,10 +48154,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 5.044ns (logic 0.334ns (6.614%) route 4.711ns (93.386%)) + Data Path Delay: 2.908ns (logic 0.334ns (11.472%) route 2.575ns (88.528%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.319ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.319ns + Clock Path Skew: -0.461ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -32188,12 +48166,12 @@ Slack: inf M6 0.000 0.000 r dip_sw[8] (IN) net (fo=0) 0.000 0.000 dip_sw[8] M6 IBUF (Prop_ibuf_I_O) 0.244 0.244 r dip_sw_IBUF[8]_inst/O - net (fo=1, routed) 4.491 4.735 u_confreg/dip_sw_IBUF[8] - SLICE_X5Y79 LUT5 (Prop_lut5_I4_O) 0.045 4.780 r u_confreg/s_rdata[8]_i_4/O - net (fo=1, routed) 0.220 4.999 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 - SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.045 5.044 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O - net (fo=1, routed) 0.000 5.044 u_confreg/u_int_ctrl_n_23 - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/D + net (fo=1, routed) 2.293 2.537 u_confreg/dip_sw_IBUF[8] + SLICE_X61Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.582 r u_confreg/s_rdata[8]_i_4/O + net (fo=1, routed) 0.282 2.863 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 + SLICE_X59Y131 LUT6 (Prop_lut6_I4_O) 0.045 2.908 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O + net (fo=1, routed) 0.000 2.908 u_confreg/u_int_ctrl_n_23 + SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -32205,8 +48183,498 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.989 -0.319 u_confreg/sys_clk - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/C + net (fo=9971, routed) 0.847 -0.461 u_confreg/sys_clk + SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[8]/C + +Slack: inf + Source: dip_sw[20] + (input port) + Destination: u_confreg/s_rdata_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.916ns (logic 0.333ns (11.420%) route 2.583ns (88.580%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.452ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M4 0.000 0.000 r dip_sw[20] (IN) + net (fo=0) 0.000 0.000 dip_sw[20] + M4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r dip_sw_IBUF[20]_inst/O + net (fo=1, routed) 2.250 2.493 u_confreg/dip_sw_IBUF[20] + SLICE_X54Y140 LUT5 (Prop_lut5_I4_O) 0.045 2.538 r u_confreg/s_rdata[20]_i_4/O + net (fo=1, routed) 0.332 2.871 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 + SLICE_X50Y138 LUT6 (Prop_lut6_I4_O) 0.045 2.916 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O + net (fo=1, routed) 0.000 2.916 u_confreg/u_int_ctrl_n_11 + SLICE_X50Y138 FDRE r u_confreg/s_rdata_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk + SLICE_X50Y138 FDRE r u_confreg/s_rdata_reg[20]/C + +Slack: inf + Source: dip_sw[4] + (input port) + Destination: u_confreg/s_rdata_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.923ns (logic 0.346ns (11.834%) route 2.577ns (88.166%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.455ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.455ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P4 0.000 0.000 r dip_sw[4] (IN) + net (fo=0) 0.000 0.000 dip_sw[4] + P4 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[4]_inst/O + net (fo=1, routed) 2.226 2.482 u_confreg/dip_sw_IBUF[4] + SLICE_X63Y134 LUT5 (Prop_lut5_I4_O) 0.045 2.527 r u_confreg/s_rdata[4]_i_4/O + net (fo=1, routed) 0.351 2.878 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 + SLICE_X55Y135 LUT6 (Prop_lut6_I4_O) 0.045 2.923 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O + net (fo=1, routed) 0.000 2.923 u_confreg/u_int_ctrl_n_27 + SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk + SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[4]/C + +Slack: inf + Source: dip_sw[16] + (input port) + Destination: u_confreg/s_rdata_reg[16]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.946ns (logic 0.358ns (12.144%) route 2.588ns (87.856%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.455ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.455ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K2 0.000 0.000 r dip_sw[16] (IN) + net (fo=0) 0.000 0.000 dip_sw[16] + K2 IBUF (Prop_ibuf_I_O) 0.268 0.268 r dip_sw_IBUF[16]_inst/O + net (fo=1, routed) 2.202 2.469 u_confreg/dip_sw_IBUF[16] + SLICE_X62Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.514 r u_confreg/s_rdata[16]_i_4/O + net (fo=1, routed) 0.386 2.901 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 + SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.045 2.946 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O + net (fo=1, routed) 0.000 2.946 u_confreg/u_int_ctrl_n_15 + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[16]/C + +Slack: inf + Source: dip_sw[7] + (input port) + Destination: u_confreg/s_rdata_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.963ns (logic 0.329ns (11.112%) route 2.634ns (88.888%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.459ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.459ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N6 0.000 0.000 r dip_sw[7] (IN) + net (fo=0) 0.000 0.000 dip_sw[7] + N6 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[7]_inst/O + net (fo=1, routed) 2.091 2.331 u_confreg/dip_sw_IBUF[7] + SLICE_X66Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.376 r u_confreg/s_rdata[7]_i_4/O + net (fo=1, routed) 0.542 2.918 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 + SLICE_X56Y131 LUT6 (Prop_lut6_I4_O) 0.045 2.963 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O + net (fo=1, routed) 0.000 2.963 u_confreg/u_int_ctrl_n_24 + SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.849 -0.459 u_confreg/sys_clk + SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[7]/C +>>>>>>> Stashed changes + +Slack: inf + Source: dip_sw[25] + (input port) + Destination: u_confreg/s_rdata_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) +<<<<<<< Updated upstream + Data Path Delay: 5.158ns (logic 0.347ns (6.729%) route 4.811ns (93.271%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.309ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.309ns +======= + Data Path Delay: 2.966ns (logic 0.347ns (11.701%) route 2.619ns (88.299%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.452ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.452ns +>>>>>>> Stashed changes + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R3 0.000 0.000 r dip_sw[25] (IN) + net (fo=0) 0.000 0.000 dip_sw[25] + R3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[25]_inst/O +<<<<<<< Updated upstream + net (fo=1, routed) 4.470 4.727 u_confreg/dip_sw_IBUF[25] + SLICE_X1Y60 LUT5 (Prop_lut5_I4_O) 0.045 4.772 r u_confreg/s_rdata[25]_i_4/O + net (fo=1, routed) 0.341 5.113 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 + SLICE_X5Y58 LUT6 (Prop_lut6_I4_O) 0.045 5.158 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O + net (fo=1, routed) 0.000 5.158 u_confreg/u_int_ctrl_n_6 + SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[25]/D +======= + net (fo=1, routed) 2.366 2.623 u_confreg/dip_sw_IBUF[25] + SLICE_X55Y138 LUT5 (Prop_lut5_I4_O) 0.045 2.668 r u_confreg/s_rdata[25]_i_4/O + net (fo=1, routed) 0.253 2.921 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 + SLICE_X51Y138 LUT6 (Prop_lut6_I4_O) 0.045 2.966 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O + net (fo=1, routed) 0.000 2.966 u_confreg/u_int_ctrl_n_6 + SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[25]/D +>>>>>>> Stashed changes + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O +<<<<<<< Updated upstream + net (fo=35652, routed) 0.999 -0.309 u_confreg/sys_clk + SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[25]/C +======= + net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk + SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[25]/C + +Slack: inf + Source: dip_sw[15] + (input port) + Destination: u_confreg/s_rdata_reg[15]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.012ns (logic 0.352ns (11.684%) route 2.660ns (88.316%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.455ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.455ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L2 0.000 0.000 r dip_sw[15] (IN) + net (fo=0) 0.000 0.000 dip_sw[15] + L2 IBUF (Prop_ibuf_I_O) 0.262 0.262 r dip_sw_IBUF[15]_inst/O + net (fo=1, routed) 2.317 2.579 u_confreg/dip_sw_IBUF[15] + SLICE_X58Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.624 r u_confreg/s_rdata[15]_i_4/O + net (fo=1, routed) 0.343 2.967 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 + SLICE_X49Y135 LUT6 (Prop_lut6_I4_O) 0.045 3.012 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O + net (fo=1, routed) 0.000 3.012 u_confreg/u_int_ctrl_n_16 + SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk + SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[15]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.028ns (logic 0.392ns (12.954%) route 2.636ns (87.046%)) + Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) + Clock Path Skew: -0.474ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.474ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 f UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 2.328 2.570 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X79Y136 LUT2 (Prop_lut2_I1_O) 0.044 2.614 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O + net (fo=2, routed) 0.308 2.922 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 + SLICE_X78Y136 LUT5 (Prop_lut5_I1_O) 0.106 3.028 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O + net (fo=1, routed) 0.000 3.028 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 + SLICE_X78Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.834 -0.474 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X78Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C + +Slack: inf + Source: dip_sw[14] + (input port) + Destination: u_confreg/s_rdata_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.067ns (logic 0.373ns (12.147%) route 2.694ns (87.853%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.455ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.455ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + J1 0.000 0.000 r dip_sw[14] (IN) + net (fo=0) 0.000 0.000 dip_sw[14] + J1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r dip_sw_IBUF[14]_inst/O + net (fo=1, routed) 2.150 2.432 u_confreg/dip_sw_IBUF[14] + SLICE_X62Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.477 r u_confreg/s_rdata[14]_i_4/O + net (fo=1, routed) 0.545 3.022 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 + SLICE_X49Y135 LUT6 (Prop_lut6_I4_O) 0.045 3.067 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O + net (fo=1, routed) 0.000 3.067 u_confreg/u_int_ctrl_n_17 + SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk + SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[14]/C + +Slack: inf + Source: dip_sw[27] + (input port) + Destination: u_confreg/s_rdata_reg[27]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.109ns (logic 0.362ns (11.659%) route 2.746ns (88.341%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.454ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.454ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R1 0.000 0.000 r dip_sw[27] (IN) + net (fo=0) 0.000 0.000 dip_sw[27] + R1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[27]_inst/O + net (fo=1, routed) 2.348 2.621 u_confreg/dip_sw_IBUF[27] + SLICE_X61Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.666 r u_confreg/s_rdata[27]_i_4/O + net (fo=1, routed) 0.398 3.064 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 + SLICE_X50Y137 LUT6 (Prop_lut6_I4_O) 0.045 3.109 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O + net (fo=1, routed) 0.000 3.109 u_confreg/u_int_ctrl_n_4 + SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk + SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[27]/C + +Slack: inf + Source: dip_sw[19] + (input port) + Destination: u_confreg/s_rdata_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.148ns (logic 0.336ns (10.676%) route 2.812ns (89.324%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.455ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.455ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L4 0.000 0.000 r dip_sw[19] (IN) + net (fo=0) 0.000 0.000 dip_sw[19] + L4 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[19]_inst/O + net (fo=1, routed) 2.485 2.731 u_confreg/dip_sw_IBUF[19] + SLICE_X54Y136 LUT5 (Prop_lut5_I4_O) 0.045 2.776 r u_confreg/s_rdata[19]_i_4/O + net (fo=1, routed) 0.327 3.103 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 + SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.045 3.148 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O + net (fo=1, routed) 0.000 3.148 u_confreg/u_int_ctrl_n_12 + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk + SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[19]/C + +Slack: inf + Source: dip_sw[29] + (input port) + Destination: u_confreg/s_rdata_reg[29]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.199ns (logic 0.336ns (10.503%) route 2.863ns (89.497%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.451ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T5 0.000 0.000 r dip_sw[29] (IN) + net (fo=0) 0.000 0.000 dip_sw[29] + T5 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[29]_inst/O + net (fo=1, routed) 2.536 2.782 u_confreg/dip_sw_IBUF[29] + SLICE_X60Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.827 r u_confreg/s_rdata[29]_i_4/O + net (fo=1, routed) 0.326 3.154 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 + SLICE_X57Y140 LUT6 (Prop_lut6_I4_O) 0.045 3.199 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O + net (fo=1, routed) 0.000 3.199 u_confreg/u_int_ctrl_n_2 + SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.857 -0.451 u_confreg/sys_clk + SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[29]/C + +Slack: inf + Source: dip_sw[22] + (input port) + Destination: u_confreg/s_rdata_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.279ns (logic 0.320ns (9.768%) route 2.959ns (90.232%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.451ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.451ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P6 0.000 0.000 r dip_sw[22] (IN) + net (fo=0) 0.000 0.000 dip_sw[22] + P6 IBUF (Prop_ibuf_I_O) 0.230 0.230 r dip_sw_IBUF[22]_inst/O + net (fo=1, routed) 2.615 2.845 u_confreg/dip_sw_IBUF[22] + SLICE_X58Y140 LUT5 (Prop_lut5_I4_O) 0.045 2.890 r u_confreg/s_rdata[22]_i_4/O + net (fo=1, routed) 0.345 3.234 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 + SLICE_X52Y140 LUT6 (Prop_lut6_I4_O) 0.045 3.279 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O + net (fo=1, routed) 0.000 3.279 u_confreg/u_int_ctrl_n_9 + SLICE_X52Y140 FDRE r u_confreg/s_rdata_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=9971, routed) 0.857 -0.451 u_confreg/sys_clk + SLICE_X52Y140 FDRE r u_confreg/s_rdata_reg[22]/C +>>>>>>> Stashed changes diff --git a/fpga/vivado_reports_nodsp/utilization.rpt b/fpga/vivado_reports_nodsp/utilization.rpt index ad58480..a213fbe 100644 --- a/fpga/vivado_reports_nodsp/utilization.rpt +++ b/fpga/vivado_reports_nodsp/utilization.rpt @@ -1,13 +1,17 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:05 2026 +<<<<<<< Updated upstream +| Date : Fri Jul 10 04:14:47 2026 +======= +| Date : Sat Jul 11 09:20:51 2026 +>>>>>>> Stashed changes | Host : fedora running 64-bit unknown -| Command : report_utilization -file /home/fallensigh/vivado_reports_nodsp/utilization.rpt +| Command : report_utilization -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization.rpt | Design : soc_top | Device : 7a200tfbg676-1 | Design State : Routed ------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information @@ -31,16 +35,29 @@ Table of Contents +----------------------------+-------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+-------+-------+-----------+-------+ -| Slice LUTs | 60995 | 0 | 133800 | 45.59 | -| LUT as Logic | 59140 | 0 | 133800 | 44.20 | -| LUT as Memory | 1855 | 0 | 46200 | 4.02 | -| LUT as Distributed RAM | 740 | 0 | | | +<<<<<<< Updated upstream +| Slice LUTs | 71196 | 0 | 133800 | 53.21 | +| LUT as Logic | 69453 | 0 | 133800 | 51.91 | +| LUT as Memory | 1743 | 0 | 46200 | 3.77 | +| LUT as Distributed RAM | 628 | 0 | | | | LUT as Shift Register | 1115 | 0 | | | -| Slice Registers | 39931 | 0 | 267600 | 14.92 | -| Register as Flip Flop | 39931 | 0 | 267600 | 14.92 | +| Slice Registers | 39690 | 0 | 267600 | 14.83 | +| Register as Flip Flop | 39690 | 0 | 267600 | 14.83 | | Register as Latch | 0 | 0 | 267600 | 0.00 | -| F7 Muxes | 4480 | 0 | 66900 | 6.70 | -| F8 Muxes | 1556 | 0 | 33450 | 4.65 | +| F7 Muxes | 4565 | 0 | 66900 | 6.82 | +| F8 Muxes | 1520 | 0 | 33450 | 4.54 | +======= +| Slice LUTs | 55066 | 0 | 133800 | 41.16 | +| LUT as Logic | 53158 | 0 | 133800 | 39.73 | +| LUT as Memory | 1908 | 0 | 46200 | 4.13 | +| LUT as Distributed RAM | 740 | 0 | | | +| LUT as Shift Register | 1168 | 0 | | | +| Slice Registers | 31000 | 0 | 267600 | 11.58 | +| Register as Flip Flop | 31000 | 0 | 267600 | 11.58 | +| Register as Latch | 0 | 0 | 267600 | 0.00 | +| F7 Muxes | 2130 | 0 | 66900 | 3.18 | +| F8 Muxes | 319 | 0 | 33450 | 0.95 | +>>>>>>> Stashed changes +----------------------------+-------+-------+-----------+-------+ @@ -57,9 +74,15 @@ Table of Contents | 0 | _ | Reset | - | | 0 | Yes | - | - | | 24 | Yes | - | Set | -| 26637 | Yes | - | Reset | +<<<<<<< Updated upstream +| 26562 | Yes | - | Reset | | 139 | Yes | Set | - | -| 13131 | Yes | Reset | - | +| 12965 | Yes | Reset | - | +======= +| 17683 | Yes | - | Reset | +| 126 | Yes | Set | - | +| 13167 | Yes | Reset | - | +>>>>>>> Stashed changes +-------+--------------+-------------+--------------+ @@ -69,28 +92,53 @@ Table of Contents +--------------------------------------------+-------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +--------------------------------------------+-------+-------+-----------+-------+ -| Slice | 20066 | 0 | 33450 | 59.99 | -| SLICEL | 13210 | 0 | | | -| SLICEM | 6856 | 0 | | | -| LUT as Logic | 59140 | 0 | 133800 | 44.20 | +<<<<<<< Updated upstream +| Slice | 21289 | 0 | 33450 | 63.64 | +| SLICEL | 13965 | 0 | | | +| SLICEM | 7324 | 0 | | | +| LUT as Logic | 69453 | 0 | 133800 | 51.91 | | using O5 output only | 2 | | | | -| using O6 output only | 49931 | | | | -| using O5 and O6 | 9207 | | | | -| LUT as Memory | 1855 | 0 | 46200 | 4.02 | -| LUT as Distributed RAM | 740 | 0 | | | +| using O6 output only | 57661 | | | | +| using O5 and O6 | 11790 | | | | +| LUT as Memory | 1743 | 0 | 46200 | 3.77 | +| LUT as Distributed RAM | 628 | 0 | | | | using O5 output only | 0 | | | | | using O6 output only | 60 | | | | -| using O5 and O6 | 680 | | | | +| using O5 and O6 | 568 | | | | | LUT as Shift Register | 1115 | 0 | | | | using O5 output only | 47 | | | | | using O6 output only | 1008 | | | | | using O5 and O6 | 60 | | | | -| Slice Registers | 39931 | 0 | 267600 | 14.92 | -| Register driven from within the Slice | 20433 | | | | -| Register driven from outside the Slice | 19498 | | | | -| LUT in front of the register is unused | 10788 | | | | -| LUT in front of the register is used | 8710 | | | | -| Unique Control Sets | 1304 | | 33450 | 3.90 | +| Slice Registers | 39690 | 0 | 267600 | 14.83 | +| Register driven from within the Slice | 24917 | | | | +| Register driven from outside the Slice | 14773 | | | | +| LUT in front of the register is unused | 6243 | | | | +| LUT in front of the register is used | 8530 | | | | +| Unique Control Sets | 1278 | | 33450 | 3.82 | +======= +| Slice | 17126 | 0 | 33450 | 51.20 | +| SLICEL | 11119 | 0 | | | +| SLICEM | 6007 | 0 | | | +| LUT as Logic | 53158 | 0 | 133800 | 39.73 | +| using O5 output only | 5 | | | | +| using O6 output only | 42769 | | | | +| using O5 and O6 | 10384 | | | | +| LUT as Memory | 1908 | 0 | 46200 | 4.13 | +| LUT as Distributed RAM | 740 | 0 | | | +| using O5 output only | 0 | | | | +| using O6 output only | 60 | | | | +| using O5 and O6 | 680 | | | | +| LUT as Shift Register | 1168 | 0 | | | +| using O5 output only | 123 | | | | +| using O6 output only | 997 | | | | +| using O5 and O6 | 48 | | | | +| Slice Registers | 31000 | 0 | 267600 | 11.58 | +| Register driven from within the Slice | 16668 | | | | +| Register driven from outside the Slice | 14332 | | | | +| LUT in front of the register is unused | 5924 | | | | +| LUT in front of the register is used | 8408 | | | | +| Unique Control Sets | 930 | | 33450 | 2.78 | +>>>>>>> Stashed changes +--------------------------------------------+-------+-------+-----------+-------+ * Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. @@ -101,11 +149,19 @@ Table of Contents +-------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 23.5 | 0 | 365 | 6.44 | -| RAMB36/FIFO* | 8 | 0 | 365 | 2.19 | -| RAMB36E1 only | 8 | | | | +<<<<<<< Updated upstream +| Block RAM Tile | 25.5 | 0 | 365 | 6.99 | +| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 | +| RAMB36E1 only | 10 | | | | | RAMB18 | 31 | 0 | 730 | 4.25 | | RAMB18E1 only | 31 | | | | +======= +| Block RAM Tile | 29.5 | 0 | 365 | 8.08 | +| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 | +| RAMB36E1 only | 10 | | | | +| RAMB18 | 39 | 0 | 730 | 5.34 | +| RAMB18E1 only | 39 | | | | +>>>>>>> Stashed changes +-------------------+------+-------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 @@ -113,12 +169,11 @@ Table of Contents 4. DSP ------ -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| DSPs | 16 | 0 | 740 | 2.16 | -| DSP48E1 only | 16 | | | | -+----------------+------+-------+-----------+-------+ ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 740 | 0.00 | ++-----------+------+-------+-----------+-------+ 5. IO and GT Specific @@ -154,7 +209,7 @@ Table of Contents +------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +------------+------+-------+-----------+-------+ -| BUFGCTRL | 4 | 0 | 32 | 12.50 | +| BUFGCTRL | 3 | 0 | 32 | 9.38 | | BUFIO | 0 | 0 | 40 | 0.00 | | MMCME2_ADV | 0 | 0 | 10 | 0.00 | | PLLE2_ADV | 1 | 0 | 10 | 10.00 | @@ -188,31 +243,53 @@ Table of Contents +-----------+-------+---------------------+ | Ref Name | Used | Functional Category | +-----------+-------+---------------------+ -| LUT6 | 35413 | LUT | -| FDCE | 26637 | Flop & Latch | -| FDRE | 13131 | Flop & Latch | -| LUT3 | 9384 | LUT | -| LUT5 | 8477 | LUT | -| LUT4 | 7294 | LUT | -| LUT2 | 6978 | LUT | -| MUXF7 | 4480 | MuxFx | -| CARRY4 | 2859 | CarryLogic | -| MUXF8 | 1556 | MuxFx | -| RAMD32 | 1060 | Distributed Memory | +<<<<<<< Updated upstream +| LUT6 | 37981 | LUT | +| FDCE | 26562 | Flop & Latch | +| FDRE | 12965 | Flop & Latch | +| LUT5 | 12781 | LUT | +| LUT4 | 10316 | LUT | +| LUT3 | 10135 | LUT | +| LUT2 | 9228 | LUT | +| MUXF7 | 4565 | MuxFx | +| CARRY4 | 3546 | CarryLogic | +| MUXF8 | 1520 | MuxFx | | SRLC32E | 992 | Distributed Memory | -| LUT1 | 801 | LUT | -| RAMS32 | 328 | Distributed Memory | +| RAMD32 | 892 | Distributed Memory | +| LUT1 | 802 | LUT | +| RAMS32 | 272 | Distributed Memory | | SRL16E | 183 | Distributed Memory | | FDSE | 139 | Flop & Latch | +======= +| LUT6 | 26800 | LUT | +| FDCE | 17683 | Flop & Latch | +| FDRE | 13167 | Flop & Latch | +| LUT3 | 10370 | LUT | +| LUT4 | 8684 | LUT | +| LUT2 | 8543 | LUT | +| LUT5 | 8274 | LUT | +| CARRY4 | 3669 | CarryLogic | +| MUXF7 | 2130 | MuxFx | +| RAMD32 | 1060 | Distributed Memory | +| SRLC32E | 992 | Distributed Memory | +| LUT1 | 871 | LUT | +| RAMS32 | 328 | Distributed Memory | +| MUXF8 | 319 | MuxFx | +| SRL16E | 224 | Distributed Memory | +| FDSE | 126 | Flop & Latch | +>>>>>>> Stashed changes | IBUF | 104 | IO | | OBUF | 98 | IO | | OBUFT | 66 | IO | +| RAMB18E1 | 39 | Block Memory | | RAMD64E | 32 | Distributed Memory | -| RAMB18E1 | 31 | Block Memory | | FDPE | 24 | Flop & Latch | -| DSP48E1 | 16 | Block Arithmetic | -| RAMB36E1 | 8 | Block Memory | +| RAMB36E1 | 10 | Block Memory | +<<<<<<< Updated upstream +| BUFG | 3 | Clock | +======= | BUFG | 4 | Clock | +>>>>>>> Stashed changes | PLLE2_ADV | 1 | Clock | +-----------+-------+---------------------+ diff --git a/fpga/vivado_reports_nodsp/utilization_hier.rpt b/fpga/vivado_reports_nodsp/utilization_hier.rpt index 9abba2a..0630b69 100644 --- a/fpga/vivado_reports_nodsp/utilization_hier.rpt +++ b/fpga/vivado_reports_nodsp/utilization_hier.rpt @@ -1,13 +1,13 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:06 2026 +| Date : Sat Jul 11 09:20:51 2026 | Host : fedora running 64-bit unknown -| Command : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_nodsp/utilization_hier.rpt +| Command : report_utilization -hierarchical -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization_hier.rpt | Design : soc_top | Device : 7a200tfbg676-1 | Design State : Routed -------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information @@ -21,255 +21,269 @@ Table of Contents +------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks | +------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ -| soc_top | (top) | 60995 | 59140 | 740 | 1115 | 39931 | 8 | 31 | 16 | -| (soc_top) | (top) | 878 | 822 | 56 | 0 | 4 | 0 | 0 | 0 | +| soc_top | (top) | 55066 | 53158 | 740 | 1168 | 31000 | 10 | 39 | 0 | +| (soc_top) | (top) | 927 | 919 | 8 | 0 | 4 | 0 | 0 | 0 | | pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| inst | clk_pll__clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst | clk_pll_clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | -| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 459 | 459 | 0 | 0 | 151 | 0 | 0 | 0 | -| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 6 | 6 | 0 | 0 | 24 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_82 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_65 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_81 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_66 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_80 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_67 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_79 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 | +| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 368 | 368 | 0 | 0 | 151 | 0 | 0 | 0 | +| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 | +| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_92 | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 | +| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_75 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_91 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_76 | 17 | 17 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_90 | 17 | 17 | 0 | 0 | 3 | 0 | 0 | 0 | +| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_77 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_89 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 | +| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 32 | 32 | 0 | 0 | 11 | 0 | 0 | 0 | | (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_76 | 27 | 27 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_77 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3_78 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_86 | 26 | 26 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_87 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | +| fifo | StreamFifo_3_88 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_73 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_74 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3_75 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_83 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_84 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | +| fifo | StreamFifo_3_85 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | +| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 | | (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_70 | 20 | 20 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_71 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3_72 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 23 | 23 | 0 | 0 | 11 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_80 | 24 | 24 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_81 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | +| fifo | StreamFifo_3_82 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | +| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 | | (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7 | 21 | 21 | 0 | 0 | 3 | 0 | 0 | 0 | | cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | | fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 96 | 96 | 0 | 0 | 25 | 0 | 0 | 0 | -| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 75 | 75 | 0 | 0 | 12 | 0 | 0 | 0 | -| errorSlave | Axi4ReadOnlyErrorSlave_1_69 | 21 | 21 | 0 | 0 | 13 | 0 | 0 | 0 | -| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 40 | 40 | 0 | 0 | 18 | 0 | 0 | 0 | -| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 | -| errorSlave | Axi4WriteOnlyErrorSlave_1_68 | 21 | 21 | 0 | 0 | 2 | 0 | 0 | 0 | -| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 133 | 133 | 0 | 0 | 17 | 0 | 0 | 0 | -| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 118 | 118 | 0 | 0 | 8 | 0 | 0 | 0 | -| errorSlave | Axi4ReadOnlyErrorSlave_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 | -| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 30 | 30 | 0 | 0 | 14 | 0 | 0 | 0 | -| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 | -| errorSlave | Axi4WriteOnlyErrorSlave_1 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 | -| u_Axi_CDC | Axi_CDC | 410 | 282 | 128 | 0 | 317 | 0 | 0 | 0 | -| arFifo | StreamFifoCC_3_48 | 181 | 145 | 36 | 0 | 77 | 0 | 0 | 0 | -| (arFifo) | StreamFifoCC_3_48 | 176 | 140 | 36 | 0 | 65 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9_63 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11_64 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| awFifo | StreamFifoCC_49 | 103 | 67 | 36 | 0 | 79 | 0 | 0 | 0 | -| (awFifo) | StreamFifoCC_49 | 99 | 63 | 36 | 0 | 65 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_10_60 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9_61 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11_62 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| bFifo | StreamFifoCC_2_50 | 15 | 15 | 0 | 0 | 26 | 0 | 0 | 0 | -| (bFifo) | StreamFifoCC_2_50 | 8 | 8 | 0 | 0 | 12 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_5_57 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_4_58 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_6_59 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| rFifo | StreamFifoCC_4_51 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 | -| (rFifo) | StreamFifoCC_4_51 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_55 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_1_56 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| wFifo | StreamFifoCC_1_52 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 | -| (wFifo) | StreamFifoCC_1_52 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_7_53 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_8_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| u_axi_axil_adapter | axi_axil_adapter | 1073 | 1073 | 0 | 0 | 173 | 0 | 0 | 0 | -| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 498 | 498 | 0 | 0 | 85 | 0 | 0 | 0 | -| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 575 | 575 | 0 | 0 | 88 | 0 | 0 | 0 | -| u_axi_dvi | axi_dvi | 283 | 283 | 0 | 0 | 211 | 0 | 0 | 0 | -| u_axi_ram | axi_wrap_ram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 | -| u_axi_sram_sp | axi2sram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 | -| u_axi_uart_controller | axi_uart_controller | 683 | 667 | 16 | 0 | 457 | 0 | 0 | 0 | -| AA_axi2apb_bridge_cpu | axi2apb_bridge | 251 | 251 | 0 | 0 | 120 | 0 | 0 | 0 | +| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 90 | 90 | 0 | 0 | 25 | 0 | 0 | 0 | +| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 74 | 74 | 0 | 0 | 12 | 0 | 0 | 0 | +| errorSlave | Axi4ReadOnlyErrorSlave_1_79 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 | +| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | +| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | +| errorSlave | Axi4WriteOnlyErrorSlave_1_78 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 | +| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 52 | 52 | 0 | 0 | 17 | 0 | 0 | 0 | +| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 36 | 36 | 0 | 0 | 8 | 0 | 0 | 0 | +| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 | +| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 23 | 23 | 0 | 0 | 14 | 0 | 0 | 0 | +| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 15 | 15 | 0 | 0 | 12 | 0 | 0 | 0 | +| errorSlave | Axi4WriteOnlyErrorSlave_1 | 8 | 8 | 0 | 0 | 2 | 0 | 0 | 0 | +| u_Axi_CDC | Axi_CDC | 427 | 299 | 128 | 0 | 317 | 0 | 0 | 0 | +| arFifo | StreamFifoCC_3_58 | 192 | 156 | 36 | 0 | 77 | 0 | 0 | 0 | +| (arFifo) | StreamFifoCC_3_58 | 186 | 150 | 36 | 0 | 65 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_9_73 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_11_74 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | +| awFifo | StreamFifoCC_59 | 110 | 74 | 36 | 0 | 79 | 0 | 0 | 0 | +| (awFifo) | StreamFifoCC_59 | 103 | 67 | 36 | 0 | 65 | 0 | 0 | 0 | +| bufferCC_12 | BufferCC_10_70 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_9_71 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_11_72 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| bFifo | StreamFifoCC_2_60 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 | +| (bFifo) | StreamFifoCC_2_60 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| bufferCC_12 | BufferCC_5_67 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_4_68 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_6_69 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| rFifo | StreamFifoCC_4_61 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 | +| (rFifo) | StreamFifoCC_4_61 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_65 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_1_66 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| wFifo | StreamFifoCC_1_62 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 | +| (wFifo) | StreamFifoCC_1_62 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_7_63 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_8_64 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| u_axi_axil_adapter | axi_axil_adapter | 1245 | 1245 | 0 | 0 | 161 | 0 | 0 | 0 | +| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 640 | 640 | 0 | 0 | 81 | 0 | 0 | 0 | +| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 605 | 605 | 0 | 0 | 80 | 0 | 0 | 0 | +| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 | +| u_axi_ram | axi_wrap_ram_sp_external | 356 | 356 | 0 | 0 | 78 | 0 | 0 | 0 | +| u_axi_sram_sp | axi2sram_sp_external | 356 | 356 | 0 | 0 | 78 | 0 | 0 | 0 | +| u_axi_uart_controller | axi_uart_controller | 684 | 668 | 16 | 0 | 457 | 0 | 0 | 0 | +| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 | | uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 | | regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 | -| (regs) | uart_regs | 119 | 119 | 0 | 0 | 155 | 0 | 0 | 0 | +| (regs) | uart_regs | 118 | 118 | 0 | 0 | 155 | 0 | 0 | 0 | | i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 | | (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 | | fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 | | (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 | -| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 | +| rfifo | raminfr_57 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 | | transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 | | (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 | | fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 | | (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 | | tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 | -| u_cdma_matmul_bridge | cdma_matmul_bridge | 251 | 251 | 0 | 0 | 578 | 0 | 0 | 0 | +| u_cdma_matmul_bridge | cdma_matmul_bridge | 248 | 248 | 0 | 0 | 578 | 0 | 0 | 0 | | u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 | | (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 | | u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 | | u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 | -| u_cpu | core_top | 8551 | 8299 | 252 | 0 | 5591 | 0 | 20 | 0 | -| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 | -| addr_trans | addr_trans | 2247 | 2107 | 140 | 0 | 1244 | 0 | 0 | 0 | +| u_cpu | core_top | 8584 | 8284 | 300 | 0 | 5591 | 0 | 20 | 0 | +| (u_cpu) | core_top | 561 | 513 | 48 | 0 | 1 | 0 | 0 | 0 | +| addr_trans | addr_trans | 2240 | 2100 | 140 | 0 | 1244 | 0 | 0 | 0 | | (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 | -| tlb_entry | tlb_entry | 2247 | 2107 | 140 | 0 | 1204 | 0 | 0 | 0 | -| axi_bridge | axi_bridge | 40 | 40 | 0 | 0 | 214 | 0 | 0 | 0 | -| btb | btb | 1046 | 966 | 80 | 0 | 1611 | 0 | 0 | 0 | -| (btb) | btb | 1044 | 964 | 80 | 0 | 1611 | 0 | 0 | 0 | +| tlb_entry | tlb_entry | 2240 | 2100 | 140 | 0 | 1204 | 0 | 0 | 0 | +| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 | +| btb | btb | 1041 | 961 | 80 | 0 | 1611 | 0 | 0 | 0 | +| (btb) | btb | 1039 | 959 | 80 | 0 | 1611 | 0 | 0 | 0 | | dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | -| dcache | dcache | 552 | 520 | 32 | 0 | 146 | 0 | 10 | 0 | +| dcache | dcache | 551 | 519 | 32 | 0 | 146 | 0 | 10 | 0 | | (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 | -| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 | -| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 | -| tagv_ram_way[1].u | tagv_sram_46 | 41 | 41 | 0 | 0 | 0 | 0 | 1 | 0 | -| exe_stage | exe_stage | 663 | 663 | 0 | 0 | 233 | 0 | 0 | 0 | -| (exe_stage) | exe_stage | 632 | 632 | 0 | 0 | 233 | 0 | 0 | 0 | +| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_46 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_47 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_48 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_49 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_50 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_51 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_52 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_53 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 | +| lfsr | lfsr_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| tagv_ram_way[0].u | tagv_sram_55 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 | +| tagv_ram_way[1].u | tagv_sram_56 | 42 | 42 | 0 | 0 | 0 | 0 | 1 | 0 | +| exe_stage | exe_stage | 666 | 666 | 0 | 0 | 233 | 0 | 0 | 0 | +| (exe_stage) | exe_stage | 635 | 635 | 0 | 0 | 233 | 0 | 0 | 0 | | u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | -| icache | icache | 235 | 235 | 0 | 0 | 55 | 0 | 10 | 0 | +| icache | icache | 233 | 233 | 0 | 0 | 55 | 0 | 10 | 0 | | (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 | | data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_38 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_39 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_40 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_41 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_42 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_43 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_44 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 | | lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 | -| tagv_ram_way[1].u | tagv_sram_35 | 87 | 87 | 0 | 0 | 0 | 0 | 1 | 0 | +| tagv_ram_way[1].u | tagv_sram_45 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 | | id_stage | id_stage | 1054 | 1054 | 0 | 0 | 108 | 0 | 0 | 0 | -| if_stage | if_stage | 135 | 135 | 0 | 0 | 173 | 0 | 0 | 0 | -| mem_stage | mem_stage | 116 | 116 | 0 | 0 | 211 | 0 | 0 | 0 | -| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 | -| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 | -| u_mul | mul | 936 | 936 | 0 | 0 | 592 | 0 | 0 | 0 | -| wb_stage | wb_stage | 680 | 680 | 0 | 0 | 233 | 0 | 0 | 0 | -| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 36148 | 34927 | 112 | 1109 | 27165 | 8 | 10 | 16 | -| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| u_fft_controller | fft_controller | 2646 | 1606 | 0 | 1040 | 1083 | 6 | 4 | 16 | -| (u_fft_controller) | fft_controller | 123 | 123 | 0 | 0 | 100 | 0 | 0 | 0 | -| u_FFT | FFT | 2496 | 1456 | 0 | 1040 | 983 | 6 | 0 | 16 | -| SU1 | SdfUnit | 1071 | 303 | 0 | 768 | 197 | 2 | 0 | 4 | -| (SU1) | SdfUnit | 205 | 205 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_25 | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | -| DB1 | DelayBuffer | 562 | 50 | 0 | 512 | 32 | 0 | 0 | 0 | -| DB2 | DelayBuffer__parameterized0 | 256 | 0 | 0 | 256 | 32 | 0 | 0 | 0 | -| MU | Multiply_26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | -| TW | Twiddle_27 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | -| SU2 | SdfUnit__parameterized0 | 492 | 300 | 0 | 192 | 197 | 2 | 0 | 4 | -| (SU2) | SdfUnit__parameterized0 | 73 | 73 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 | +| mem_stage | mem_stage | 115 | 115 | 0 | 0 | 211 | 0 | 0 | 0 | +| u_csr | csr | 201 | 201 | 0 | 0 | 663 | 0 | 0 | 0 | +| u_div | div | 141 | 141 | 0 | 0 | 107 | 0 | 0 | 0 | +| u_mul | mul | 938 | 938 | 0 | 0 | 592 | 0 | 0 | 0 | +| wb_stage | wb_stage | 682 | 682 | 0 | 0 | 233 | 0 | 0 | 0 | +| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 30142 | 28868 | 112 | 1162 | 18251 | 10 | 18 | 0 | +| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | +| u_fft_controller | fft_controller | 6934 | 5894 | 0 | 1040 | 1083 | 8 | 4 | 0 | +| (u_fft_controller) | fft_controller | 118 | 118 | 0 | 0 | 100 | 0 | 0 | 0 | +| u_FFT | FFT | 6782 | 5742 | 0 | 1040 | 983 | 8 | 0 | 0 | +| SU1 | SdfUnit | 2144 | 1376 | 0 | 768 | 197 | 2 | 0 | 0 | +| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 | +| BF1 | Butterfly_34 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | +| BF2 | Butterfly__parameterized0_35 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | +| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 | +| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 | +| MU | Multiply_36 | 610 | 610 | 0 | 0 | 0 | 0 | 0 | 0 | +| TW | Twiddle_37 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 | +| SU2 | SdfUnit__parameterized0 | 1567 | 1375 | 0 | 192 | 197 | 2 | 0 | 0 | +| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 | +| BF1 | Butterfly_30 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | +| BF2 | Butterfly__parameterized0_31 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | | DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 | | DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 | -| MU | Multiply_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 | -| TW | Twiddle_23 | 3 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | -| SU3 | SdfUnit__parameterized1 | 346 | 298 | 0 | 48 | 197 | 0 | 0 | 4 | -| (SU3) | SdfUnit__parameterized1 | 74 | 74 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| MU | Multiply_32 | 612 | 612 | 0 | 0 | 0 | 0 | 0 | 0 | +| TW | Twiddle_33 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 | +| SU3 | SdfUnit__parameterized1 | 1416 | 1368 | 0 | 48 | 197 | 2 | 0 | 0 | +| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 | +| BF1 | Butterfly_26 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | +| BF2 | Butterfly__parameterized0_27 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | | DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 | | DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 | -| MU | Multiply_19 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 | -| SU4 | SdfUnit__parameterized2 | 327 | 295 | 0 | 32 | 197 | 2 | 0 | 4 | -| (SU4) | SdfUnit__parameterized2 | 69 | 69 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_15 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| MU | Multiply_28 | 610 | 610 | 0 | 0 | 0 | 0 | 0 | 0 | +| TW | Twiddle_29 | 539 | 539 | 0 | 0 | 0 | 2 | 0 | 0 | +| SU4 | SdfUnit__parameterized2 | 1397 | 1365 | 0 | 32 | 197 | 2 | 0 | 0 | +| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 | +| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | +| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | | DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 | | DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 | -| MU | Multiply | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 | -| TW | Twiddle | 2 | 2 | 0 | 0 | 0 | 2 | 0 | 0 | -| SU5 | SdfUnit__parameterized3 | 260 | 260 | 0 | 0 | 195 | 0 | 0 | 0 | -| (SU5) | SdfUnit__parameterized3 | 68 | 68 | 0 | 0 | 99 | 0 | 0 | 0 | +| MU | Multiply | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 | +| TW | Twiddle | 536 | 536 | 0 | 0 | 0 | 2 | 0 | 0 | +| SU5 | SdfUnit__parameterized3 | 258 | 258 | 0 | 0 | 195 | 0 | 0 | 0 | +| (SU5) | SdfUnit__parameterized3 | 34 | 34 | 0 | 0 | 99 | 0 | 0 | 0 | | BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | | DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 | | DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 | -| u_in0 | my_bram0 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_in1 | my_bram0_12 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_out0 | my_bram0_13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_out1 | my_bram0_14 | 25 | 25 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_mlkem_axi_cdc | Axi_CDC_5 | 421 | 309 | 112 | 0 | 272 | 0 | 0 | 0 | -| arFifo | StreamFifoCC_3 | 53 | 25 | 28 | 0 | 55 | 0 | 0 | 0 | -| (arFifo) | StreamFifoCC_3 | 44 | 16 | 28 | 0 | 43 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9_10 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| awFifo | StreamFifoCC | 40 | 16 | 24 | 0 | 49 | 0 | 0 | 0 | +| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_in1 | my_bram0_21 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_out0 | my_bram0_22 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_out1 | my_bram0_23 | 32 | 32 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_mlkem_axi_cdc | Axi_CDC_5 | 336 | 224 | 112 | 0 | 272 | 0 | 0 | 0 | +| arFifo | StreamFifoCC_3 | 50 | 22 | 28 | 0 | 55 | 0 | 0 | 0 | +| (arFifo) | StreamFifoCC_3 | 42 | 14 | 28 | 0 | 43 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_9_19 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_11_20 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| awFifo | StreamFifoCC | 39 | 15 | 24 | 0 | 49 | 0 | 0 | 0 | | (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 | | bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_9 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | | bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 | | (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 | | bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | -| rFifo | StreamFifoCC_4 | 57 | 29 | 28 | 0 | 72 | 0 | 0 | 0 | -| (rFifo) | StreamFifoCC_4 | 49 | 21 | 28 | 0 | 56 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| rFifo | StreamFifoCC_4 | 65 | 37 | 28 | 0 | 72 | 0 | 0 | 0 | +| (rFifo) | StreamFifoCC_4 | 58 | 30 | 28 | 0 | 56 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | -| wFifo | StreamFifoCC_1 | 253 | 225 | 28 | 0 | 69 | 0 | 0 | 0 | -| (wFifo) | StreamFifoCC_1 | 248 | 220 | 28 | 0 | 53 | 0 | 0 | 0 | +| wFifo | StreamFifoCC_1 | 164 | 136 | 28 | 0 | 69 | 0 | 0 | 0 | +| (wFifo) | StreamFifoCC_1 | 159 | 131 | 28 | 0 | 53 | 0 | 0 | 0 | | popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| u_mlkem_axi_slave | mlkem_axi_slave | 33082 | 33013 | 0 | 69 | 25804 | 2 | 6 | 0 | -| (u_mlkem_axi_slave) | mlkem_axi_slave | 1202 | 1202 | 0 | 0 | 1068 | 0 | 0 | 0 | -| u_mlkem | mlkem_top | 31884 | 31815 | 0 | 69 | 24736 | 2 | 6 | 0 | -| (u_mlkem) | mlkem_top | 2738 | 2738 | 0 | 0 | 4960 | 0 | 0 | 0 | -| u_bank_a | sd_bram__parameterized0 | 50 | 50 | 0 | 0 | 0 | 1 | 1 | 0 | -| u_bank_se | sd_bram__parameterized1 | 70 | 70 | 0 | 0 | 0 | 1 | 0 | 0 | -| u_bank_t | sd_bram__parameterized2 | 654 | 654 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_c_in_bram | sd_bram | 1312 | 1312 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_cbd | sample_cbd_sync_shared | 2741 | 2741 | 0 | 0 | 3186 | 0 | 0 | 0 | -| u_comp | comp_decomp_sync | 467 | 466 | 0 | 1 | 323 | 0 | 0 | 0 | -| u_ct_bram | sd_bram_6 | 13 | 13 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_dkp_bram | sd_bram_7 | 82 | 82 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_ek_bram | sd_bram_8 | 2121 | 2121 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_keccak | keccak_core | 5274 | 5274 | 0 | 0 | 1606 | 0 | 0 | 0 | -| u_ntt | ntt_core | 8625 | 8582 | 0 | 43 | 3861 | 0 | 0 | 0 | -| (u_ntt) | ntt_core | 6101 | 6085 | 0 | 16 | 3358 | 0 | 0 | 0 | -| u_bf | butterfly_unit_pipe | 2260 | 2234 | 0 | 26 | 286 | 0 | 0 | 0 | -| (u_bf) | butterfly_unit_pipe | 69 | 44 | 0 | 25 | 75 | 0 | 0 | 0 | -| u_barrett | barrett_mul_pipe_9 | 2192 | 2191 | 0 | 1 | 211 | 0 | 0 | 0 | -| u_scl | barrett_mul_pipe | 265 | 264 | 0 | 1 | 217 | 0 | 0 | 0 | -| u_pmul | poly_mul_sync | 3881 | 3856 | 0 | 25 | 6743 | 0 | 0 | 0 | -| (u_pmul) | poly_mul_sync | 2434 | 2434 | 0 | 0 | 6280 | 0 | 0 | 0 | -| u_bc | basecase_mul_pipe | 1447 | 1422 | 0 | 25 | 463 | 0 | 0 | 0 | -| u_sha3 | sha3_top_shared | 1766 | 1766 | 0 | 0 | 2388 | 0 | 0 | 0 | +| u_mlkem_axi_slave | mlkem_axi_slave | 22873 | 22751 | 0 | 122 | 16890 | 2 | 14 | 0 | +| (u_mlkem_axi_slave) | mlkem_axi_slave | 1179 | 1179 | 0 | 0 | 1064 | 0 | 0 | 0 | +| u_mlkem | mlkem_top | 21697 | 21575 | 0 | 122 | 15826 | 2 | 14 | 0 | +| (u_mlkem) | mlkem_top | 2633 | 2633 | 0 | 0 | 5010 | 0 | 0 | 0 | +| u_bank_a | sd_bram__parameterized0 | 61 | 61 | 0 | 0 | 0 | 1 | 1 | 0 | +| u_bank_se | sd_bram__parameterized1 | 77 | 77 | 0 | 0 | 0 | 1 | 0 | 0 | +| u_bank_t | sd_bram__parameterized2 | 632 | 632 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_c_in_bram | sd_bram | 1301 | 1301 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_cbd | sample_cbd_sync_shared | 2739 | 2739 | 0 | 0 | 3186 | 0 | 0 | 0 | +| u_comp | comp_decomp_sync | 620 | 618 | 0 | 2 | 319 | 0 | 0 | 0 | +| u_ct_bram | sd_bram_6 | 10 | 10 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_dkp_bram | sd_bram_7 | 74 | 74 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_ek_bram | sd_bram_8 | 304 | 304 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_keccak | keccak_core | 5258 | 5258 | 0 | 0 | 1618 | 0 | 0 | 0 | +| u_ntt | ntt_core | 1900 | 1817 | 0 | 83 | 1062 | 0 | 4 | 0 | +| (u_ntt) | ntt_core | 281 | 249 | 0 | 32 | 215 | 0 | 0 | 0 | +| u_bf0 | butterfly_unit_pipe | 675 | 650 | 0 | 25 | 321 | 0 | 0 | 0 | +| (u_bf0) | butterfly_unit_pipe | 264 | 239 | 0 | 25 | 112 | 0 | 0 | 0 | +| u_barrett | barrett_mul_pipe_18 | 411 | 411 | 0 | 0 | 209 | 0 | 0 | 0 | +| u_bf1 | butterfly_unit_pipe_12 | 487 | 462 | 0 | 25 | 307 | 0 | 0 | 0 | +| (u_bf1) | butterfly_unit_pipe_12 | 89 | 65 | 0 | 24 | 96 | 0 | 0 | 0 | +| u_barrett | barrett_mul_pipe_17 | 398 | 397 | 0 | 1 | 211 | 0 | 0 | 0 | +| u_cr | coeff_bram_4way | 208 | 208 | 0 | 0 | 8 | 0 | 4 | 0 | +| (u_cr) | coeff_bram_4way | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gen_xbar[0].u_bank | sd_bram__parameterized3_13 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | +| gen_xbar[1].u_bank | sd_bram__parameterized3_14 | 89 | 89 | 0 | 0 | 0 | 0 | 1 | 0 | +| gen_xbar[2].u_bank | sd_bram__parameterized3_15 | 16 | 16 | 0 | 0 | 0 | 0 | 1 | 0 | +| gen_xbar[3].u_bank | sd_bram__parameterized3_16 | 82 | 82 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_scl | barrett_mul_pipe | 252 | 251 | 0 | 1 | 211 | 0 | 0 | 0 | +| u_pmul | poly_mul_sync | 2058 | 2021 | 0 | 37 | 584 | 0 | 4 | 0 | +| (u_pmul) | poly_mul_sync | 634 | 634 | 0 | 0 | 121 | 0 | 0 | 0 | +| u_a_even | sd_bram__parameterized3 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_a_odd | sd_bram__parameterized3_9 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_b_even | sd_bram__parameterized3_10 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_b_odd | sd_bram__parameterized3_11 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_bc | basecase_mul_pipe | 1423 | 1386 | 0 | 37 | 463 | 0 | 0 | 0 | +| u_sha3 | sha3_top_shared | 1955 | 1955 | 0 | 0 | 2378 | 0 | 0 | 0 | | u_snt | sample_ntt_sync_shared | 2109 | 2109 | 0 | 0 | 1669 | 0 | 0 | 0 | -| u_matmul_axi_slave | matmul_axi_slave | 9758 | 9576 | 176 | 6 | 3248 | 0 | 0 | 0 | -| (u_matmul_axi_slave) | matmul_axi_slave | 5637 | 5455 | 176 | 6 | 2480 | 0 | 0 | 0 | -| mult_inst[0].u_mult | pipelined_mult_32x32 | 1063 | 1063 | 0 | 0 | 192 | 0 | 0 | 0 | +| u_matmul_axi_slave | matmul_axi_slave | 9879 | 9697 | 176 | 6 | 3243 | 0 | 0 | 0 | +| (u_matmul_axi_slave) | matmul_axi_slave | 5761 | 5579 | 176 | 6 | 2475 | 0 | 0 | 0 | +| mult_inst[0].u_mult | pipelined_mult_32x32 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 | | mult_inst[1].u_mult | pipelined_mult_32x32_2 | 999 | 999 | 0 | 0 | 192 | 0 | 0 | 0 | -| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 | +| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 1060 | 1060 | 0 | 0 | 192 | 0 | 0 | 0 | | mult_inst[3].u_mult | pipelined_mult_32x32_4 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 | -| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1788 | 1788 | 0 | 0 | 1476 | 0 | 1 | 0 | -| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 751 | 751 | 0 | 0 | 1180 | 0 | 0 | 0 | -| u_core_engine | snix_axi_mm2mm | 1038 | 1038 | 0 | 0 | 296 | 0 | 1 | 0 | -| (u_core_engine) | snix_axi_mm2mm | 762 | 762 | 0 | 0 | 243 | 0 | 0 | 0 | -| axis_fifo_u0 | snix_axis_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 | -| u_fifo | snix_sync_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 | +| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1557 | 1557 | 0 | 0 | 1476 | 0 | 1 | 0 | +| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 600 | 600 | 0 | 0 | 1180 | 0 | 0 | 0 | +| u_core_engine | snix_axi_mm2mm | 960 | 960 | 0 | 0 | 296 | 0 | 1 | 0 | +| (u_core_engine) | snix_axi_mm2mm | 750 | 750 | 0 | 0 | 243 | 0 | 0 | 0 | +| axis_fifo_u0 | snix_axis_fifo | 210 | 210 | 0 | 0 | 53 | 0 | 1 | 0 | +| u_fifo | snix_sync_fifo | 210 | 210 | 0 | 0 | 53 | 0 | 1 | 0 | +------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/clock_interaction.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/clock_interaction.rpt deleted file mode 100644 index a8a58a3..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/clock_interaction.rpt +++ /dev/null @@ -1,28 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 -| Host : fedora running 64-bit unknown -| Command : report_clock_interaction -file /home/fallensigh/vivado_reports_nodsp/clock_interaction.rpt -| Design : soc_top -| Device : 7a200t-fbg676 -| Speed File : -1 PRODUCTION 1.23 2018-06-13 ------------------------------------------------------------------------------------------------------------- - -Clock Interaction Report - -Clock Interaction Table ------------------------ - - WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock -From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints ------------------ ----------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- ------------------- -cpu_clk cpu_clk rise - rise 2.72 0.00 0 17264 30.32 Clean Timed -cpu_clk sys_clk 0 162 Ignored Asynchronous Groups -mlkem_clk_clk_pll mlkem_clk_clk_pll rise - rise 10.81 0.00 0 74168 40.00 Clean Timed -mlkem_clk_clk_pll sys_clk rise - rise 11.25 0.00 0 61 20.00 Clean Timed -sys_clk cpu_clk 0 59 Ignored Asynchronous Groups -sys_clk mlkem_clk_clk_pll rise - rise 9.16 0.00 0 112 20.00 Clean Timed -sys_clk sys_clk rise - rise 0.17 0.00 0 23704 20.00 Clean Timed - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/clocks.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/clocks.rpt deleted file mode 100644 index 7ce6dda..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/clocks.rpt +++ /dev/null @@ -1,76 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 -| Host : fedora running 64-bit unknown -| Command : report_clocks -file /home/fallensigh/vivado_reports_nodsp/clocks.rpt -| Design : soc_top -| Device : 7a200t-fbg676 -| Speed File : -1 PRODUCTION 1.23 2018-06-13 --------------------------------------------------------------------------------------- - -Clock Report - - -Attributes - P: Propagated - G: Generated - A: Auto-derived - R: Renamed - V: Virtual - I: Inverted - S: Pin phase-shifted with Latency mode - -Clock Period(ns) Waveform(ns) Attributes Sources -clk 20.000 {0.000 10.000} P {clk} -clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT} -cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} -mlkem_clk_clk_pll 40.000 {0.000 20.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2} -sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1} - - -==================================================== -Generated Clocks -==================================================== - -Generated Clock : clkfbout_clk_pll -Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Master Clock : clk -Multiply By : 1 -Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT} - -Generated Clock : cpu_clk -Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Master Clock : clk -Edges : {1 2 3} -Edge Shifts(ns) : {0.000 5.161 10.323} -Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} - -Generated Clock : mlkem_clk_clk_pll -Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Master Clock : clk -Edges : {1 2 3} -Edge Shifts(ns) : {0.000 10.000 20.000} -Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2} - -Generated Clock : sys_clk -Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Master Clock : clk -Multiply By : 1 -Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1} - - - -==================================================== -User Uncertainty -==================================================== - - - -==================================================== -User Jitter -==================================================== - -Clock Jitter(ns) -clk 0.200 - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_complexity.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_complexity.rpt deleted file mode 100644 index 441963e..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_complexity.rpt +++ /dev/null @@ -1,37 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:35:00 2026 -| Host : fedora running 64-bit unknown -| Command : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_nodsp/design_analysis_complexity.rpt -| Design : soc_top -| Device : xc7a200t -| Design State : Routed -------------------------------------------------------------------------------------------------------------------------------- - -Report Design Analysis - -Table of Contents ------------------ -1. Complexity Characteristics (Cells) - -1. Complexity Characteristics (Cells) -------------------------------------- - -+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+ -| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM | -+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+ -| (top) | soc_top | 0.34 | 3.77 | 118528 | 801(1.2%) | 6978(10.2%) | 9384(13.7%) | 7294(10.7%) | 8477(12.4%) | 35413(51.8%) | 1175 | 16 | 39 | 6020 | 0 | -| u_axi_axil_adapter | axi_axil_adapter | 0.50 | 5.92 | 1309 | 0(0.0%) | 8(0.7%) | 43(3.8%) | 100(8.9%) | 200(17.7%) | 776(68.9%) | 0 | 0 | 0 | 0 | 0 | -| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 | -| u_cdma_matmul_bridge | cdma_matmul_bridge | 0.46 | 2.22 | 1002 | 1(0.3%) | 65(17.1%) | 39(10.3%) | 174(45.8%) | 13(3.4%) | 88(23.2%) | 0 | 0 | 0 | 0 | 0 | -| u_cpu | core_top | 0.56 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 | -| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.56 | 3.75 | 74954 | 362(0.9%) | 3923(9.7%) | 6649(16.4%) | 4109(10.2%) | 4490(11.1%) | 20899(51.7%) | 1169 | 16 | 18 | 5286 | 0 | -| u_matmul_axi_slave | matmul_axi_slave | 0.63 | 3.76 | 15159 | 18(0.2%) | 1646(15.2%) | 357(3.3%) | 830(7.6%) | 974(9.0%) | 7026(64.7%) | 6 | 0 | 0 | 413 | 0 | -| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.36 | 3.45 | 3680 | 136(6.5%) | 181(8.6%) | 405(19.3%) | 255(12.2%) | 342(16.3%) | 776(37.0%) | 0 | 0 | 1 | 4 | 0 | -+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+ -* Complexity Ranges -** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal, 0.65 - 0.85 -> high, 0.85 - 1.0 -> very high -*** -* -> Not computable as cell size is very small - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_timing.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_timing.rpt deleted file mode 100644 index 6e7bf34..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_timing.rpt +++ /dev/null @@ -1,52 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:29 2026 -| Host : fedora running 64-bit unknown -| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_nodsp/design_analysis_timing.rpt -| Design : soc_top -| Device : xc7a200t -| Design State : Routed ------------------------------------------------------------------------------------------------------------------------ - -Report Design Analysis - -Table of Contents ------------------ -1. Setup Path Characteristics 1-1 - -1. Setup Path Characteristics 1-1 ---------------------------------- - -+---------------------------+------------------------------------------------------+ -| Characteristics | Path #1 | -+---------------------------+------------------------------------------------------+ -| Requirement | 20.000 | -| Path Delay | 15.605 | -| Logic Delay | 5.343(35%) | -| Net Delay | 10.263(65%) | -| Clock Skew | -3.858 | -| Slack | 0.167 | -| Clock Relationship | Safely Timed | -| Logic Levels | 9 | -| Routes | 9 | -| Logical Path | FDRE LUT4 LUT6 LUT5 LUT6 RAMD32 LUT6 LUT5 LUT3 OBUFT | -| Start Point Clock | sys_clk | -| End Point Clock | sys_clk | -| DSP Block | None | -| BRAM | None | -| IO Crossings | 3 | -| Config Crossings | 0 | -| SLR Crossings | 0 | -| PBlocks | 0 | -| High Fanout | 130 | -| Dont Touch | 0 | -| Mark Debug | 0 | -| Start Point Pin Primitive | FDRE/C | -| End Point Pin Primitive | ext_ram_data[18] | -| Start Point Pin | FSM_sequential_ext_wr_state_reg[1]/C | -| End Point Pin | ext_ram_data[18] | -+---------------------------+------------------------------------------------------+ -* Bounding box calculated as % of dimensions for the target device (436, 500) - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/drc.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/drc.rpt deleted file mode 100644 index 213e823..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/drc.rpt +++ /dev/null @@ -1,491 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:33:58 2026 -| Host : fedora running 64-bit unknown -| Command : report_drc -file /home/fallensigh/vivado_reports_nodsp/drc.rpt -| Design : soc_top -| Device : xc7a200tfbg676-1 -| Speed File : -1 -| Design State : Fully Routed ------------------------------------------------------------------------------------- - -Report DRC - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: impl_1 - Design limits: - Ruledeck: default - Max violations: - Violations found: 90 -+-----------+----------+----------------------------+------------+ -| Rule | Severity | Description | Violations | -+-----------+----------+----------------------------+------------+ -| CHECK-3 | Warning | Report rule limit reached | 2 | -| DPIP-1 | Warning | Input pipelining | 16 | -| DPOP-1 | Warning | PREG Output pipelining | 16 | -| DPOP-2 | Warning | MREG Output pipelining | 16 | -| REQP-1839 | Warning | RAMB36 async control check | 20 | -| REQP-1840 | Warning | RAMB18 async control check | 20 | -+-----------+----------+----------------------------+------------+ - -2. REPORT DETAILS ------------------ -CHECK-3#1 Warning -Report rule limit reached -REQP-1839 rule limit reached: 20 violations have been found. -Related violations: - -CHECK-3#2 Warning -Report rule limit reached -REQP-1840 rule limit reached: 20 violations have been found. -Related violations: - -DPIP-1#1 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#2 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#3 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#4 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#5 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#6 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#7 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#8 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#9 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#10 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#11 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#12 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#13 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#14 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#15 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#16 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPOP-1#1 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#2 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#3 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#4 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#5 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#6 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#7 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#8 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#9 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#10 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#11 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#12 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#13 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#14 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#15 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#16 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-2#1 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#2 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#3 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#4 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#5 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#6 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#7 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#8 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#9 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#10 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#11 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#12 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#13 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#14 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#15 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#16 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -REQP-1839#1 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#2 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#3 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#4 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#5 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#6 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#7 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#8 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#9 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#10 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#11 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#12 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#13 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#14 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#15 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#16 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#17 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#18 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#19 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#20 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#1 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#2 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#3 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#4 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#5 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#6 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#7 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#8 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#9 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#10 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#11 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#12 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#13 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#14 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#15 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#16 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#17 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#18 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#19 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#20 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/high_fanout.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/high_fanout.rpt deleted file mode 100644 index 5af6bfc..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/high_fanout.rpt +++ /dev/null @@ -1,221 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 -| Host : fedora running 64-bit unknown -| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_nodsp/high_fanout.rpt -| Design : soc_top -| Device : xc7a200t --------------------------------------------------------------------------------------------------------------------------------------------- - -High Fan-out Nets Information - -1. Summary ----------- - -+---------------------------------------------------------------------------------------+--------+-------------+ -| Net Name | Fanout | Driver Type | -+---------------------------------------------------------------------------------------+--------+-------------+ -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1] | 24598 | LUT5 | -| pll_clk.u_clk_pll/inst/sys_clk | 10004 | BUFG | -| pll_clk.u_rst_sys/p_0_in | 4130 | LUT1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT2 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_n_0 | 1619 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0] | 1608 | LUT2 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 | 1608 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state[2]_i_3_n_0 | 1604 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sel_cbd | 1603 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1601 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 | 1601 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_6_n_0 | 1601 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_7_n_0 | 1601 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1] | 1543 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2] | 1542 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1109 | LUT2 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE | -| pll_clk.u_rst_mlkem/delay_reg[1]_0 | 1069 | LUT1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0 | 936 | LUT5 | -| u_cpu/reset | 799 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0] | 769 | CARRY4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1] | 769 | CARRY4 | -| u_matmul_axi_slave/w_addr[2] | 724 | FDRE | -| u_cpu/u_mul/E[0] | 716 | LUT1 | -| u_matmul_axi_slave/w_addr[3] | 628 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1 | 528 | LUT6 | -| u_matmul_axi_slave/current_r_offset[2] | 522 | LUT5 | -| u_matmul_axi_slave/current_r_offset[3] | 520 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0] | 516 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1] | 516 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_rep_2[0] | 512 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[2] | 390 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2] | 385 | CARRY4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_vld_reg_n_0 | 370 | FDCE | -| u_cpu/wb_stage/w_index[0] | 358 | LUT6 | -| u_cpu/wb_stage/w_index[1] | 358 | LUT6 | -| u_cpu/wb_stage/w_index[2] | 358 | LUT6 | -| u_cpu/wb_stage/w_index[3] | 358 | LUT6 | -| u_cpu/wb_stage/w_index[4] | 358 | LUT6 | -| u_matmul_axi_slave/acc_idx_d4[0] | 354 | FDRE | -| u_matmul_axi_slave/acc_idx_d4[1] | 354 | FDRE | -| u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE | -| u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE | -| u_cpu/wb_stage/we_0 | 324 | LUT4 | -| u_matmul_axi_slave/w_addr[4] | 317 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 290 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3] | 284 | FDCE | -| u_matmul_axi_slave/cur_bank_reg_n_0 | 277 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 263 | RAMB18E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 263 | RAMB18E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 262 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 261 | RAMB18E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 261 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[4] | 260 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 259 | RAMB36E1 | -| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 259 | FDRE | -| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0 | 257 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_active_reg_rep__7[0] | 256 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 | -| u_matmul_axi_slave/m_in_b[0][31]_i_1_n_0 | 256 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 | -| u_matmul_axi_slave/w_addr[5] | 246 | FDRE | -| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT3 | -| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 | -| u_cpu/mem_stage/E[0] | 234 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 234 | FDCE | -| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 229 | LUT3 | -| u_matmul_axi_slave/m_in_b[0][31]_i_7_n_0 | 228 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 227 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 224 | LUT4 | -| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 | -| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 | -| u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE | -| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0] | 203 | FDRE | -| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1] | 203 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6] | 200 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 200 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[3] | 197 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2] | 196 | FDCE | -| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 196 | LUT6 | -| u_cpu/wb_stage/Q[33] | 194 | FDRE | -| u_cpu/wb_stage/Q[34] | 194 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5] | 194 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3] | 193 | CARRY4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r_reg[4]_rep_n_0 | 191 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[2] | 187 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3] | 187 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 187 | FDCE | -| u_matmul_axi_slave/current_r_offset[4] | 187 | LUT5 | -| u_matmul_axi_slave/s_axi_wready_reg_1 | 181 | LUT3 | -| u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3] | 180 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 177 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0] | 176 | FDCE | -| u_matmul_axi_slave/p_0_in__0 | 176 | LUT4 | -| u_matmul_axi_slave/p_0_in__0__0 | 176 | LUT4 | -| u_cpu/wb_stage/Q[37] | 173 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7] | 173 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_4_n_7 | 171 | CARRY4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[127]_i_2_n_0 | 169 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[383]_i_2_n_0 | 169 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[639]_i_2_n_0 | 169 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[895]_i_2_n_0 | 169 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 169 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5] | 166 | FDCE | -| u_cpu/wb_stage/Q[32] | 164 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 164 | FDCE | -| u_cpu/wb_stage/Q[35] | 163 | FDRE | -| u_cpu/wb_stage/Q[36] | 162 | FDRE | -| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0 | 161 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1023]_i_2_n_0 | 160 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[255]_i_2_n_0 | 160 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[511]_i_2_n_0 | 160 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[767]_i_2_n_0 | 160 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 155 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6] | 153 | FDCE | -| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 153 | LUT3 | -| u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0 | 151 | FDRE | -| u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1 | 150 | CARRY4 | -| u_cpu/dcache/awaddr[31]_i_3_n_0 | 148 | LUT2 | -| u_cpu/dcache/awaddr[31]_i_4_n_0 | 148 | LUT2 | -| u_matmul_axi_slave/s_axi_wready_reg_0 | 148 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0] | 145 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_63_n_0 | 144 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 143 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 143 | FDCE | -| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0 | 143 | LUT3 | -| u_matmul_axi_slave/pipe_cnt[3]_i_4_n_0 | 143 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep_n_0 | 142 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 141 | FDCE | -| u_cpu/dcache/write_buffer_state | 140 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_reg_rep__6_n_0 | 140 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5] | 140 | FDCE | -| u_cpu/u_csr/tlbw_r_tlbidx[0] | 139 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_37_n_0 | 139 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep__3_n_0 | 139 | FDCE | -+---------------------------------------------------------------------------------------+--------+-------------+ - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/methodology.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/methodology.rpt deleted file mode 100644 index 82b3488..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/methodology.rpt +++ /dev/null @@ -1,542 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:05 2026 -| Host : fedora running 64-bit unknown -| Command : report_methodology -file /home/fallensigh/vivado_reports_nodsp/methodology.rpt -| Design : soc_top -| Device : xc7a200tfbg676-1 -| Speed File : -1 -| Design State : Fully Routed ------------------------------------------------------------------------------------------------- - -Report Methodology - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: impl_1 - Design limits: - Max violations: - Violations found: 99 -+-----------+----------+-------------------------------------------------------------------+------------+ -| Rule | Severity | Description | Violations | -+-----------+----------+-------------------------------------------------------------------+------------+ -| LUTAR-1 | Warning | LUT drives async reset alert | 1 | -| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 | -| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 1 | -| SYNTH-16 | Warning | Address collision | 8 | -| TIMING-10 | Warning | Missing property on synchronizer | 1 | -| TIMING-18 | Warning | Missing input or output delay | 76 | -| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 2 | -| XDCC-1 | Warning | Scoped Clock constraint overwritten with the same name | 1 | -| XDCC-7 | Warning | Scoped Clock constraint overwritten on the same source | 1 | -+-----------+----------+-------------------------------------------------------------------+------------+ - -2. REPORT DETAILS ------------------ -LUTAR-1#1 Warning -LUT drives async reset alert -LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24584 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. -Related violations: - -SYNTH-5#1 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#2 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#3 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#4 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#5 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#6 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#7 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#8 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-6#1 Warning -Timing of a block RAM might be sub-optimal -The timing for the instance u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block -Related violations: - -SYNTH-16#1 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#2 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#3 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#4 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#5 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#6 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#7 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#8 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -TIMING-10#1 Warning -Missing property on synchronizer -One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage -Related violations: - -TIMING-18#1 Warning -Missing input or output delay -An input delay is missing on UART_RX relative to clock(s) clk -Related violations: - -TIMING-18#2 Warning -Missing input or output delay -An input delay is missing on UART_TX relative to clock(s) clk -Related violations: - -TIMING-18#3 Warning -Missing input or output delay -An input delay is missing on dip_sw[0] relative to clock(s) clk -Related violations: - -TIMING-18#4 Warning -Missing input or output delay -An input delay is missing on dip_sw[10] relative to clock(s) clk -Related violations: - -TIMING-18#5 Warning -Missing input or output delay -An input delay is missing on dip_sw[11] relative to clock(s) clk -Related violations: - -TIMING-18#6 Warning -Missing input or output delay -An input delay is missing on dip_sw[12] relative to clock(s) clk -Related violations: - -TIMING-18#7 Warning -Missing input or output delay -An input delay is missing on dip_sw[13] relative to clock(s) clk -Related violations: - -TIMING-18#8 Warning -Missing input or output delay -An input delay is missing on dip_sw[14] relative to clock(s) clk -Related violations: - -TIMING-18#9 Warning -Missing input or output delay -An input delay is missing on dip_sw[15] relative to clock(s) clk -Related violations: - -TIMING-18#10 Warning -Missing input or output delay -An input delay is missing on dip_sw[16] relative to clock(s) clk -Related violations: - -TIMING-18#11 Warning -Missing input or output delay -An input delay is missing on dip_sw[17] relative to clock(s) clk -Related violations: - -TIMING-18#12 Warning -Missing input or output delay -An input delay is missing on dip_sw[18] relative to clock(s) clk -Related violations: - -TIMING-18#13 Warning -Missing input or output delay -An input delay is missing on dip_sw[19] relative to clock(s) clk -Related violations: - -TIMING-18#14 Warning -Missing input or output delay -An input delay is missing on dip_sw[1] relative to clock(s) clk -Related violations: - -TIMING-18#15 Warning -Missing input or output delay -An input delay is missing on dip_sw[20] relative to clock(s) clk -Related violations: - -TIMING-18#16 Warning -Missing input or output delay -An input delay is missing on dip_sw[21] relative to clock(s) clk -Related violations: - -TIMING-18#17 Warning -Missing input or output delay -An input delay is missing on dip_sw[22] relative to clock(s) clk -Related violations: - -TIMING-18#18 Warning -Missing input or output delay -An input delay is missing on dip_sw[23] relative to clock(s) clk -Related violations: - -TIMING-18#19 Warning -Missing input or output delay -An input delay is missing on dip_sw[24] relative to clock(s) clk -Related violations: - -TIMING-18#20 Warning -Missing input or output delay -An input delay is missing on dip_sw[25] relative to clock(s) clk -Related violations: - -TIMING-18#21 Warning -Missing input or output delay -An input delay is missing on dip_sw[26] relative to clock(s) clk -Related violations: - -TIMING-18#22 Warning -Missing input or output delay -An input delay is missing on dip_sw[27] relative to clock(s) clk -Related violations: - -TIMING-18#23 Warning -Missing input or output delay -An input delay is missing on dip_sw[28] relative to clock(s) clk -Related violations: - -TIMING-18#24 Warning -Missing input or output delay -An input delay is missing on dip_sw[29] relative to clock(s) clk -Related violations: - -TIMING-18#25 Warning -Missing input or output delay -An input delay is missing on dip_sw[2] relative to clock(s) clk -Related violations: - -TIMING-18#26 Warning -Missing input or output delay -An input delay is missing on dip_sw[30] relative to clock(s) clk -Related violations: - -TIMING-18#27 Warning -Missing input or output delay -An input delay is missing on dip_sw[31] relative to clock(s) clk -Related violations: - -TIMING-18#28 Warning -Missing input or output delay -An input delay is missing on dip_sw[3] relative to clock(s) clk -Related violations: - -TIMING-18#29 Warning -Missing input or output delay -An input delay is missing on dip_sw[4] relative to clock(s) clk -Related violations: - -TIMING-18#30 Warning -Missing input or output delay -An input delay is missing on dip_sw[5] relative to clock(s) clk -Related violations: - -TIMING-18#31 Warning -Missing input or output delay -An input delay is missing on dip_sw[6] relative to clock(s) clk -Related violations: - -TIMING-18#32 Warning -Missing input or output delay -An input delay is missing on dip_sw[7] relative to clock(s) clk -Related violations: - -TIMING-18#33 Warning -Missing input or output delay -An input delay is missing on dip_sw[8] relative to clock(s) clk -Related violations: - -TIMING-18#34 Warning -Missing input or output delay -An input delay is missing on dip_sw[9] relative to clock(s) clk -Related violations: - -TIMING-18#35 Warning -Missing input or output delay -An input delay is missing on touch_btn[0] relative to clock(s) clk -Related violations: - -TIMING-18#36 Warning -Missing input or output delay -An input delay is missing on touch_btn[1] relative to clock(s) clk -Related violations: - -TIMING-18#37 Warning -Missing input or output delay -An input delay is missing on touch_btn[2] relative to clock(s) clk -Related violations: - -TIMING-18#38 Warning -Missing input or output delay -An input delay is missing on touch_btn[3] relative to clock(s) clk -Related violations: - -TIMING-18#39 Warning -Missing input or output delay -An output delay is missing on dpy0[0] relative to clock(s) clk -Related violations: - -TIMING-18#40 Warning -Missing input or output delay -An output delay is missing on dpy0[1] relative to clock(s) clk -Related violations: - -TIMING-18#41 Warning -Missing input or output delay -An output delay is missing on dpy0[2] relative to clock(s) clk -Related violations: - -TIMING-18#42 Warning -Missing input or output delay -An output delay is missing on dpy0[3] relative to clock(s) clk -Related violations: - -TIMING-18#43 Warning -Missing input or output delay -An output delay is missing on dpy0[4] relative to clock(s) clk -Related violations: - -TIMING-18#44 Warning -Missing input or output delay -An output delay is missing on dpy0[5] relative to clock(s) clk -Related violations: - -TIMING-18#45 Warning -Missing input or output delay -An output delay is missing on dpy0[6] relative to clock(s) clk -Related violations: - -TIMING-18#46 Warning -Missing input or output delay -An output delay is missing on dpy0[7] relative to clock(s) clk -Related violations: - -TIMING-18#47 Warning -Missing input or output delay -An output delay is missing on dpy1[0] relative to clock(s) clk -Related violations: - -TIMING-18#48 Warning -Missing input or output delay -An output delay is missing on dpy1[1] relative to clock(s) clk -Related violations: - -TIMING-18#49 Warning -Missing input or output delay -An output delay is missing on dpy1[2] relative to clock(s) clk -Related violations: - -TIMING-18#50 Warning -Missing input or output delay -An output delay is missing on dpy1[3] relative to clock(s) clk -Related violations: - -TIMING-18#51 Warning -Missing input or output delay -An output delay is missing on dpy1[4] relative to clock(s) clk -Related violations: - -TIMING-18#52 Warning -Missing input or output delay -An output delay is missing on dpy1[5] relative to clock(s) clk -Related violations: - -TIMING-18#53 Warning -Missing input or output delay -An output delay is missing on dpy1[6] relative to clock(s) clk -Related violations: - -TIMING-18#54 Warning -Missing input or output delay -An output delay is missing on dpy1[7] relative to clock(s) clk -Related violations: - -TIMING-18#55 Warning -Missing input or output delay -An output delay is missing on leds[0] relative to clock(s) clk -Related violations: - -TIMING-18#56 Warning -Missing input or output delay -An output delay is missing on leds[10] relative to clock(s) clk -Related violations: - -TIMING-18#57 Warning -Missing input or output delay -An output delay is missing on leds[11] relative to clock(s) clk -Related violations: - -TIMING-18#58 Warning -Missing input or output delay -An output delay is missing on leds[12] relative to clock(s) clk -Related violations: - -TIMING-18#59 Warning -Missing input or output delay -An output delay is missing on leds[13] relative to clock(s) clk -Related violations: - -TIMING-18#60 Warning -Missing input or output delay -An output delay is missing on leds[14] relative to clock(s) clk -Related violations: - -TIMING-18#61 Warning -Missing input or output delay -An output delay is missing on leds[15] relative to clock(s) clk -Related violations: - -TIMING-18#62 Warning -Missing input or output delay -An output delay is missing on leds[1] relative to clock(s) clk -Related violations: - -TIMING-18#63 Warning -Missing input or output delay -An output delay is missing on leds[2] relative to clock(s) clk -Related violations: - -TIMING-18#64 Warning -Missing input or output delay -An output delay is missing on leds[3] relative to clock(s) clk -Related violations: - -TIMING-18#65 Warning -Missing input or output delay -An output delay is missing on leds[4] relative to clock(s) clk -Related violations: - -TIMING-18#66 Warning -Missing input or output delay -An output delay is missing on leds[5] relative to clock(s) clk -Related violations: - -TIMING-18#67 Warning -Missing input or output delay -An output delay is missing on leds[6] relative to clock(s) clk -Related violations: - -TIMING-18#68 Warning -Missing input or output delay -An output delay is missing on leds[7] relative to clock(s) clk -Related violations: - -TIMING-18#69 Warning -Missing input or output delay -An output delay is missing on leds[8] relative to clock(s) clk -Related violations: - -TIMING-18#70 Warning -Missing input or output delay -An output delay is missing on leds[9] relative to clock(s) clk -Related violations: - -TIMING-18#71 Warning -Missing input or output delay -An output delay is missing on video_de relative to clock(s) clk -Related violations: - -TIMING-18#72 Warning -Missing input or output delay -An output delay is missing on video_hsync relative to clock(s) clk -Related violations: - -TIMING-18#73 Warning -Missing input or output delay -An output delay is missing on video_red[0] relative to clock(s) clk -Related violations: - -TIMING-18#74 Warning -Missing input or output delay -An output delay is missing on video_red[1] relative to clock(s) clk -Related violations: - -TIMING-18#75 Warning -Missing input or output delay -An output delay is missing on video_red[2] relative to clock(s) clk -Related violations: - -TIMING-18#76 Warning -Missing input or output delay -An output delay is missing on video_vsync relative to clock(s) clk -Related violations: - -TIMING-47#1 Warning -False path or asynchronous clock group between synchronous clocks -A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. -Related violations: - -TIMING-47#2 Warning -False path or asynchronous clock group between synchronous clocks -A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. -Related violations: - -XDCC-1#1 Warning -Scoped Clock constraint overwritten with the same name -A new clock constraint create_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors. -New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4)) -Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56)) -Related violations: - -XDCC-7#1 Warning -Scoped Clock constraint overwritten on the same source -A new clock constraint create_clock overrides a previous scoped clock constraint defined on the same source. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors. -New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4)) -Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56)) -Related violations: - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/mlkem_clk_timing.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/mlkem_clk_timing.rpt deleted file mode 100644 index 2fdd8cd..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/mlkem_clk_timing.rpt +++ /dev/null @@ -1,5216 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 -| Host : fedora running 64-bit unknown -| Command : report_timing -from [get_clocks mlkem_clk_clk_pll] -to [get_clocks mlkem_clk_clk_pll] -delay_type max -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/mlkem_clk_timing.rpt -| Design : soc_top -| Device : 7a200t-fbg676 -| Speed File : -1 PRODUCTION 1.23 2018-06-13 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Timing Report - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] - ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 - ------------------------------------------------------------------- - slack 11.519 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] - ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 - ------------------------------------------------------------------- - slack 11.519 - - - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/power.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/power.rpt deleted file mode 100644 index 851e855..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/power.rpt +++ /dev/null @@ -1,180 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:25 2026 -| Host : fedora running 64-bit unknown -| Command : report_power -file /home/fallensigh/vivado_reports_nodsp/power.rpt -| Design : soc_top -| Device : xc7a200tfbg676-1 -| Design State : routed -| Grade : commercial -| Process : typical -| Characterization : Production ------------------------------------------------------------------------------------------------- - -Power Report - -Table of Contents ------------------ -1. Summary -1.1 On-Chip Components -1.2 Power Supply Summary -1.3 Confidence Level -2. Settings -2.1 Environment -2.2 Clock Constraints -3. Detailed Reports -3.1 By Hierarchy - -1. Summary ----------- - -+--------------------------+--------------+ -| Total On-Chip Power (W) | 0.549 | -| Design Power Budget (W) | Unspecified* | -| Power Budget Margin (W) | NA | -| Dynamic (W) | 0.409 | -| Device Static (W) | 0.141 | -| Effective TJA (C/W) | 1.9 | -| Max Ambient (C) | 84.0 | -| Junction Temperature (C) | 26.0 | -| Confidence Level | Low | -| Setting File | --- | -| Simulation Activity File | --- | -| Design Nets Matched | NA | -+--------------------------+--------------+ -* Specify Design Power Budget using, set_operating_conditions -design_power_budget - - -1.1 On-Chip Components ----------------------- - -+--------------------------+-----------+----------+-----------+-----------------+ -| On-Chip | Power (W) | Used | Available | Utilization (%) | -+--------------------------+-----------+----------+-----------+-----------------+ -| Clocks | 0.042 | 7 | --- | --- | -| Slice Logic | 0.069 | 120086 | --- | --- | -| LUT as Logic | 0.064 | 63754 | 133800 | 47.65 | -| CARRY4 | 0.002 | 2859 | 33450 | 8.55 | -| LUT as Distributed RAM | <0.001 | 740 | 46200 | 1.60 | -| Register | <0.001 | 39931 | 267600 | 14.92 | -| LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 | -| F7/F8 Muxes | <0.001 | 6036 | 133800 | 4.51 | -| Others | 0.000 | 318 | --- | --- | -| Signals | 0.115 | 85084 | --- | --- | -| Block RAM | 0.019 | 23.5 | 365 | 6.44 | -| PLL | 0.132 | 1 | 10 | 10.00 | -| DSPs | 0.009 | 16 | 740 | 2.16 | -| I/O | 0.023 | 202 | 400 | 50.50 | -| Static Power | 0.141 | | | | -| Total | 0.549 | | | | -+--------------------------+-----------+----------+-----------+-----------------+ - - -1.2 Power Supply Summary ------------------------- - -+-----------+-------------+-----------+-------------+------------+ -| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | -+-----------+-------------+-----------+-------------+------------+ -| Vccint | 1.000 | 0.294 | 0.262 | 0.032 | -| Vccaux | 1.800 | 0.099 | 0.069 | 0.031 | -| Vcco33 | 3.300 | 0.011 | 0.006 | 0.005 | -| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | -| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | -| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | -| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | -| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | -| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccbram | 1.000 | 0.003 | 0.001 | 0.001 | -| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | -| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | -| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | -+-----------+-------------+-----------+-------------+------------+ - - -1.3 Confidence Level --------------------- - -+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ -| User Input Data | Confidence | Details | Action | -+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ -| Design implementation state | High | Design is routed | | -| Clock nodes activity | High | User specified more than 95% of clocks | | -| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | -| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | -| Device models | High | Device models are Production | | -| | | | | -| Overall confidence level | Low | | | -+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ - - -2. Settings ------------ - -2.1 Environment ---------------- - -+-----------------------+--------------------------+ -| Ambient Temp (C) | 25.0 | -| ThetaJA (C/W) | 1.9 | -| Airflow (LFM) | 250 | -| Heat Sink | medium (Medium Profile) | -| ThetaSA (C/W) | 3.4 | -| Board Selection | medium (10"x10") | -| # of Board Layers | 12to15 (12 to 15 Layers) | -| Board Temperature (C) | 25.0 | -+-----------------------+--------------------------+ - - -2.2 Clock Constraints ---------------------- - -+-------------------+------------------------------------------+-----------------+ -| Clock | Domain | Constraint (ns) | -+-------------------+------------------------------------------+-----------------+ -| clk | clk | 20.0 | -| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 | -| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 | -| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 40.0 | -| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 | -+-------------------+------------------------------------------+-----------------+ - - -3. Detailed Reports -------------------- - -3.1 By Hierarchy ----------------- - -+----------------------------+-----------+ -| Name | Power (W) | -+----------------------------+-----------+ -| soc_top | 0.409 | -| pll_clk.u_clk_pll | 0.133 | -| inst | 0.133 | -| u_Axi_CDC | 0.002 | -| u_axi_uart_controller | 0.001 | -| uart0 | 0.001 | -| regs | 0.001 | -| u_cdma_matmul_bridge | 0.001 | -| u_cpu | 0.018 | -| addr_trans | 0.002 | -| tlb_entry | 0.002 | -| btb | 0.002 | -| dcache | 0.004 | -| icache | 0.005 | -| u_csr | 0.002 | -| u_fft_mlkem_axi_slave | 0.148 | -| u_fft_controller | 0.032 | -| u_FFT | 0.029 | -| u_mlkem_axi_cdc | 0.002 | -| u_mlkem_axi_slave | 0.115 | -| u_mlkem | 0.113 | -| u_matmul_axi_slave | 0.065 | -| u_snix_axil_cdma_mux_8ch | 0.009 | -| u_core_engine | 0.004 | -| axis_fifo_u0 | 0.003 | -+----------------------------+-----------+ - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/route_status.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/route_status.rpt deleted file mode 100644 index a98697c..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/route_status.rpt +++ /dev/null @@ -1,12 +0,0 @@ -Design Route Status - : # nets : - ------------------------------------------- : ----------- : - # of logical nets.......................... : 128919 : - # of nets not needing routing.......... : 43824 : - # of internally routed nets........ : 43359 : - # of nets with no loads............ : 465 : - # of routable nets..................... : 85095 : - # of fully routed nets............. : 85095 : - # of nets with routing errors.......... : 0 : - ------------------------------------------- : ----------- : - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_hold_paths.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_hold_paths.rpt deleted file mode 100644 index fefd31f..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_hold_paths.rpt +++ /dev/null @@ -1,17094 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 -| Host : fedora running 64-bit unknown -| Command : report_timing -delay_type min -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/timing_hold_paths.rpt -| Design : soc_top -| Device : 7a200t-fbg676 -| Speed File : -1 PRODUCTION 1.23 2018-06-13 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Timing Report - -Slack (MET) : 0.032ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.595 -0.352 - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.053 - arrival time -0.021 - ------------------------------------------------------------------- - slack 0.032 - -Slack (MET) : 0.032ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.191 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.595 -0.352 - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.053 - arrival time -0.021 - ------------------------------------------------------------------- - slack 0.032 - -Slack (MET) : 0.042ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 0.061 - arrival time -0.019 - ------------------------------------------------------------------- - slack 0.042 - -Slack (MET) : 0.042ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 0.061 - arrival time -0.019 - ------------------------------------------------------------------- - slack 0.042 - -Slack (MET) : 0.049ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y34 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C - SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q - net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.218 -0.528 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.332 - ------------------------------------------------------------------- - slack 0.049 - -Slack (MET) : 0.049ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y34 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C - SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo0_reg[14]/Q - net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 - SLICE_X46Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.218 -0.528 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.332 - ------------------------------------------------------------------- - slack 0.049 - -Slack (MET) : 0.052ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.052 - -Slack (MET) : 0.052ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.052 - -Slack (MET) : 0.054ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.269 -0.579 - SLICE_X20Y72 RAMD32 0.000 -0.579 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 0.067 - arrival time -0.013 - ------------------------------------------------------------------- - slack 0.054 - -Slack (MET) : 0.054ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.269 -0.579 - SLICE_X20Y72 RAMD32 0.000 -0.579 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.185 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] - SLICE_X23Y73 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 0.067 - arrival time -0.013 - ------------------------------------------------------------------- - slack 0.054 - -Slack (MET) : 0.057ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.496ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.353 -0.496 - SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C - SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q - net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.037 -0.301 - SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC - ------------------------------------------------------------------- - required time 0.157 - arrival time -0.100 - ------------------------------------------------------------------- - slack 0.057 - -Slack (MET) : 0.057ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.496ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.353 -0.496 - SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C - SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 f u_cpu/axi_bridge/awaddr_reg[10]/Q - net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 - SLICE_X16Y57 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.037 -0.301 - SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC - ------------------------------------------------------------------- - required time 0.157 - arrival time -0.100 - ------------------------------------------------------------------- - slack 0.057 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.695ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.153 -0.695 - SLICE_X84Y144 FDRE 0.000 -0.695 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q - net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0 - SLICE_X84Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/I0 - SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O - net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0 - SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.472 -0.475 - clock pessimism 0.045 -0.430 - SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6] - ------------------------------------------------------------------- - required time 0.309 - arrival time -0.251 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.695ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.153 -0.695 - SLICE_X84Y144 FDRE 0.000 -0.695 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q - net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0 - SLICE_X84Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/I0 - SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O - net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0 - SLICE_X84Y151 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.472 -0.475 - clock pessimism 0.045 -0.430 - SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6] - ------------------------------------------------------------------- - required time 0.309 - arrival time -0.251 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[0]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[0]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.155 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[0]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[0]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.155 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.061ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.273ns - Source Clock Delay (SCD): -0.507ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.342 -0.507 - SLICE_X37Y38 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C - SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q - net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 - SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.674 -0.273 - clock pessimism -0.221 -0.494 - SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.347 - arrival time -0.285 - ------------------------------------------------------------------- - slack 0.061 - -Slack (MET) : 0.061ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.273ns - Source Clock Delay (SCD): -0.507ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.342 -0.507 - SLICE_X37Y38 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C - SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 f u_cpu/u_csr/csr_tlbelo1_reg[20]/Q - net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 - SLICE_X36Y38 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.674 -0.273 - clock pessimism -0.221 -0.494 - SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.347 - arrival time -0.285 - ------------------------------------------------------------------- - slack 0.061 - -Slack (MET) : 0.066ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.554 -0.393 - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.020 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.066ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.554 -0.393 - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.020 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.077ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.277ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X86Y154 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q - net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] - SLICE_X86Y148 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/I0 - SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O - net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0 - SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.478 -0.469 - clock pessimism 0.045 -0.424 - SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.255 - ------------------------------------------------------------------- - slack 0.077 - -Slack (MET) : 0.077ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.277ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X86Y154 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q - net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] - SLICE_X86Y148 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/I0 - SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O - net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0 - SLICE_X86Y148 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.478 -0.469 - clock pessimism 0.045 -0.424 - SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.255 - ------------------------------------------------------------------- - slack 0.077 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.260ns - Source Clock Delay (SCD): -0.566ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.282 -0.566 - SLICE_X18Y50 SRLC32E 0.000 -0.566 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.188 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31 - net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56 - SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.687 -0.260 - clock pessimism 0.037 -0.223 - SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32 - ------------------------------------------------------------------- - required time 0.101 - arrival time -0.023 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.260ns - Source Clock Delay (SCD): -0.566ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.282 -0.566 - SLICE_X18Y50 SRLC32E 0.000 -0.566 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.188 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31 - net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56 - SLICE_X14Y49 SRLC32E f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.687 -0.260 - clock pessimism 0.037 -0.223 - SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32 - ------------------------------------------------------------------- - required time 0.101 - arrival time -0.023 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q - net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.378 - arrival time -0.299 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q - net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0 - SLICE_X6Y56 RAMD32 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.378 - arrival time -0.299 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.410 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.410 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.080ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q - net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.377 - arrival time -0.298 - ------------------------------------------------------------------- - slack 0.080 - -Slack (MET) : 0.080ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q - net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0 - SLICE_X6Y56 RAMD32 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.377 - arrival time -0.298 - ------------------------------------------------------------------- - slack 0.080 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q - net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49] - ------------------------------------------------------------------- - required time 0.228 - arrival time -0.145 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q - net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49] - SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49] - ------------------------------------------------------------------- - required time 0.228 - arrival time -0.145 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%)) - Logic Levels: 0 - Clock Path Skew: 0.056ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X62Y75 FDCE 0.000 -0.626 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q - net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5] - RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.357 - clock pessimism -0.213 -0.570 - RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10]) - 0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.302 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%)) - Logic Levels: 0 - Clock Path Skew: 0.056ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X62Y75 FDCE 0.000 -0.626 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q - net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5] - RAMB18_X3Y30 RAMB18E1 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.357 - clock pessimism -0.213 -0.570 - RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10]) - 0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.302 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] - SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.002 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.195 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] - SLICE_X14Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.002 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[1]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[1]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.182 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[1]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[1]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 - SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.182 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.087ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.089 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] - SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.029 - ------------------------------------------------------------------- - slack 0.087 - -Slack (MET) : 0.087ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.089 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] - SLICE_X23Y77 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.029 - ------------------------------------------------------------------- - slack 0.087 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.095ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.464ns - Source Clock Delay (SCD): -0.683ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.165 -0.683 - SLICE_X73Y148 FDCE 0.000 -0.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q - net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16] - SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.483 -0.464 - clock pessimism 0.045 -0.419 - SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16] - ------------------------------------------------------------------- - required time 0.362 - arrival time -0.267 - ------------------------------------------------------------------- - slack 0.095 - -Slack (MET) : 0.095ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.464ns - Source Clock Delay (SCD): -0.683ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.165 -0.683 - SLICE_X73Y148 FDCE 0.000 -0.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q - net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16] - SLICE_X73Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.483 -0.464 - clock pessimism 0.045 -0.419 - SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16] - ------------------------------------------------------------------- - required time 0.362 - arrival time -0.267 - ------------------------------------------------------------------- - slack 0.095 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X20Y50 SRLC32E 0.000 -0.568 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.190 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31 - net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55 - SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.685 -0.262 - clock pessimism 0.037 -0.225 - SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32 - ------------------------------------------------------------------- - required time 0.103 - arrival time -0.008 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X20Y50 SRLC32E 0.000 -0.568 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.190 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31 - net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55 - SLICE_X20Y49 SRLC32E f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.685 -0.262 - clock pessimism 0.037 -0.225 - SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32 - ------------------------------------------------------------------- - required time 0.103 - arrival time -0.008 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[14]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[14]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB - ------------------------------------------------------------------- - required time 0.306 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[14]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[14]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0 - SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB - ------------------------------------------------------------------- - required time 0.306 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q - net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.280 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo1_reg[26]/Q - net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0 - SLICE_X46Y36 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.280 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q - net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51] - ------------------------------------------------------------------- - required time 0.229 - arrival time -0.128 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q - net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51] - SLICE_X15Y89 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51] - ------------------------------------------------------------------- - required time 0.229 - arrival time -0.128 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%)) - Logic Levels: 0 - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q - net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59] - ------------------------------------------------------------------- - required time 0.226 - arrival time -0.125 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%)) - Logic Levels: 0 - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q - net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59] - SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59] - ------------------------------------------------------------------- - required time 0.226 - arrival time -0.125 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X21Y48 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[3]/C - SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[3]/Q - net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.178 - arrival time -0.075 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X21Y48 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[3]/C - SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[3]/Q - net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1 - SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.178 - arrival time -0.075 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.119 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.119 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.105ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X83Y155 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q - net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5] - SLICE_X84Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/I0 - SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0 - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.471 -0.476 - clock pessimism 0.040 -0.436 - SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5] - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.200 - ------------------------------------------------------------------- - slack 0.105 - -Slack (MET) : 0.105ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X83Y155 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q - net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5] - SLICE_X84Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/I0 - SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0 - SLICE_X84Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.471 -0.476 - clock pessimism 0.040 -0.436 - SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5] - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.200 - ------------------------------------------------------------------- - slack 0.105 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[1]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[1]/Q - net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[1]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[1]/Q - net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1 - SLICE_X6Y45 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q - net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57] - ------------------------------------------------------------------- - required time 0.233 - arrival time -0.127 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q - net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57] - SLICE_X15Y89 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57] - ------------------------------------------------------------------- - required time 0.233 - arrival time -0.127 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.280ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.458ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.156 -0.693 - SLICE_X89Y154 FDCE 0.000 -0.693 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q - net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] - SLICE_X90Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/I3 - SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O - net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0 - SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.489 -0.458 - clock pessimism 0.045 -0.413 - SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8] - ------------------------------------------------------------------- - required time 0.292 - arrival time -0.185 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.280ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.458ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.156 -0.693 - SLICE_X89Y154 FDCE 0.000 -0.693 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q - net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] - SLICE_X90Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/I3 - SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O - net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0 - SLICE_X90Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.489 -0.458 - clock pessimism 0.045 -0.413 - SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8] - ------------------------------------------------------------------- - required time 0.292 - arrival time -0.185 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X64Y76 RAMD32 0.000 -0.626 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.081 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X64Y76 RAMD32 0.000 -0.626 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.081 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.268 -0.580 - SLICE_X22Y71 RAMD32 0.000 -0.580 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.056 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.268 -0.580 - SLICE_X22Y71 RAMD32 0.000 -0.580 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] - SLICE_X25Y70 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.056 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q - net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48] - ------------------------------------------------------------------- - required time 0.232 - arrival time -0.124 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q - net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48] - SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48] - ------------------------------------------------------------------- - required time 0.232 - arrival time -0.124 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.118ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[15]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[15]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1 - ------------------------------------------------------------------- - required time 0.328 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.118 - -Slack (MET) : 0.118ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[15]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[15]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1 - SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1 - ------------------------------------------------------------------- - required time 0.328 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.118 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.369 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.369 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 0.025 - arrival time 0.096 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 0.025 - arrival time 0.096 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.496 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.496 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.272 -0.576 - SLICE_X15Y70 FDCE 0.000 -0.576 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.272 -0.576 - SLICE_X15Y70 FDCE 0.000 -0.576 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y70 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X17Y59 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.499 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.499 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.476 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.476 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[10]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[10]/Q - net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[10]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[10]/Q - net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0 - SLICE_X44Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0 - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.232 -0.541 - SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.466 - arrival time -0.344 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0 - SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.232 -0.541 - SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.466 - arrival time -0.344 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X17Y59 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.539ns - Clock Pessimism Removal (CPR): 0.231ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.539 - SLICE_X1Y61 FDSE 0.000 -0.539 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0 - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.231 -0.539 - SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0] - ------------------------------------------------------------------- - required time 0.464 - arrival time -0.342 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.539ns - Clock Pessimism Removal (CPR): 0.231ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.539 - SLICE_X1Y61 FDSE 0.000 -0.539 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 f u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0 - SLICE_X1Y61 FDSE f u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.231 -0.539 - SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0] - ------------------------------------------------------------------- - required time 0.464 - arrival time -0.342 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.603ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.245 -0.603 - SLICE_X117Y61 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q - net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0] - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.573 -0.374 - clock pessimism -0.229 -0.603 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] - ------------------------------------------------------------------- - required time 0.528 - arrival time -0.406 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.603ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.245 -0.603 - SLICE_X117Y61 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q - net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0] - SLICE_X117Y61 FDCE f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.573 -0.374 - clock pessimism -0.229 -0.603 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] - ------------------------------------------------------------------- - required time 0.528 - arrival time -0.406 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.261 -0.587 - SLICE_X29Y74 FDCE 0.000 -0.587 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.227 -0.587 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.512 - arrival time -0.390 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.261 -0.587 - SLICE_X29Y74 FDCE 0.000 -0.587 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X29Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.227 -0.587 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.512 - arrival time -0.390 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0 - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.229 -0.570 - SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.229 -0.570 - SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.477 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.477 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.553ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.295 -0.553 - SLICE_X5Y75 FDCE 0.000 -0.553 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.623 -0.324 - clock pessimism -0.229 -0.553 - SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.478 - arrival time -0.356 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.553ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.295 -0.553 - SLICE_X5Y75 FDCE 0.000 -0.553 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.623 -0.324 - clock pessimism -0.229 -0.553 - SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.478 - arrival time -0.356 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.123ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y34 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[12]/C - SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[12]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.218 -0.527 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.123 - -Slack (MET) : 0.123ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y34 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[12]/C - SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[12]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0 - SLICE_X44Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.218 -0.527 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.123 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y36 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[16]/C - SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[16]/Q - net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y36 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[16]/C - SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo0_reg[16]/Q - net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0 - SLICE_X46Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[22]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%)) - Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X5Y47 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[22]/C - SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[22]/Q - net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0 - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.196 -0.425 - SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC - ------------------------------------------------------------------- - required time 0.281 - arrival time -0.157 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[22]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%)) - Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X5Y47 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[22]/C - SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[22]/Q - net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0 - SLICE_X2Y48 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.196 -0.425 - SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC - ------------------------------------------------------------------- - required time 0.281 - arrival time -0.157 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.504 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.504 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.481 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.481 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.394 - arrival time -0.266 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.394 - arrival time -0.266 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.510ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.339 -0.510 - SLICE_X41Y37 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[15]/C - SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[15]/Q - net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1 - SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1 - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.510ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.339 -0.510 - SLICE_X41Y37 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[15]/C - SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 f u_cpu/u_csr/csr_tlbelo1_reg[15]/Q - net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1 - SLICE_X40Y38 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1 - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q - net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 - ------------------------------------------------------------------- - required time 0.406 - arrival time -0.278 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo1_reg[27]/Q - net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 - SLICE_X46Y36 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 - ------------------------------------------------------------------- - required time 0.406 - arrival time -0.278 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0 - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.602 -0.345 - clock pessimism -0.230 -0.575 - SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.369 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0 - SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.602 -0.345 - clock pessimism -0.230 -0.575 - SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.369 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.390 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.390 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.542ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.542 - SLICE_X43Y32 FDRE 0.000 -0.542 r u_cpu/u_csr/csr_tlbelo0_reg[20]/C - SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 r u_cpu/u_csr/csr_tlbelo0_reg[20]/Q - net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0 - SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.542ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.542 - SLICE_X43Y32 FDRE 0.000 -0.542 r u_cpu/u_csr/csr_tlbelo0_reg[20]/C - SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 f u_cpu/u_csr/csr_tlbelo0_reg[20]/Q - net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0 - SLICE_X42Y33 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[0]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[0]/Q - net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.172 - ------------------------------------------------------------------- - slack 0.133 - -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[0]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[0]/Q - net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0 - SLICE_X6Y45 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.172 - ------------------------------------------------------------------- - slack 0.133 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q - net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[2]/Q - net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D - SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.349 -0.500 - SLICE_X28Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[2]/C - SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[2]/Q - net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB - ------------------------------------------------------------------- - required time 0.165 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.349 -0.500 - SLICE_X28Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[2]/C - SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 f u_cpu/axi_bridge/araddr_reg[2]/Q - net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0 - SLICE_X36Y59 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB - ------------------------------------------------------------------- - required time 0.165 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[12]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[12]/Q - net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.170 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[12]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[12]/Q - net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0 - SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.170 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[12]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[12]/Q - net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.385 - arrival time -0.249 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[12]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_cpu/u_csr/csr_tlbelo1_reg[12]/Q - net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 - SLICE_X46Y32 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.385 - arrival time -0.249 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.349 -0.500 - SLICE_X29Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[0]/C - SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[0]/Q - net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.164 - arrival time -0.028 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.349 -0.500 - SLICE_X29Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[0]/C - SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 f u_cpu/axi_bridge/araddr_reg[0]/Q - net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X36Y59 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.164 - arrival time -0.028 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[11]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[11]/Q - net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.405 - arrival time -0.268 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[11]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_cpu/u_csr/csr_tlbelo1_reg[11]/Q - net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1 - SLICE_X46Y32 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.405 - arrival time -0.268 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[28]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y48 FDRE 0.000 -0.465 r u_cpu/axi_bridge/wdata_reg[28]/C - SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 r u_cpu/axi_bridge/wdata_reg[28]/Q - net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I) - 0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC - ------------------------------------------------------------------- - required time 0.359 - arrival time -0.221 - ------------------------------------------------------------------- - slack 0.138 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[28]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y48 FDRE 0.000 -0.465 r u_cpu/axi_bridge/wdata_reg[28]/C - SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 f u_cpu/axi_bridge/wdata_reg[28]/Q - net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I) - 0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC - ------------------------------------------------------------------- - required time 0.359 - arrival time -0.221 - ------------------------------------------------------------------- - slack 0.138 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y43 FDRE 0.000 -0.468 r u_cpu/icache/lfsr/r_lfsr_reg[6]/C - SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/icache/lfsr/r_lfsr_reg[6]/Q - net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0] - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.236 -0.468 - SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7] - ------------------------------------------------------------------- - required time 0.397 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y43 FDRE 0.000 -0.468 r u_cpu/icache/lfsr/r_lfsr_reg[6]/C - SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/icache/lfsr/r_lfsr_reg[6]/Q - net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0] - SLICE_X5Y43 FDRE f u_cpu/icache/lfsr/r_lfsr_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.236 -0.468 - SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7] - ------------------------------------------------------------------- - required time 0.397 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[11]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[11]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1 - SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism -0.217 -0.524 - SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.400 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[11]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[11]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1 - SLICE_X44Y37 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism -0.217 -0.524 - SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.400 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.268ns - Source Clock Delay (SCD): -0.502ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.347 -0.502 - SLICE_X31Y41 FDRE 0.000 -0.502 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q - net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16] - SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.679 -0.268 - clock pessimism -0.221 -0.489 - SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16] - ------------------------------------------------------------------- - required time 0.442 - arrival time -0.301 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.268ns - Source Clock Delay (SCD): -0.502ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.347 -0.502 - SLICE_X31Y41 FDRE 0.000 -0.502 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q - net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16] - SLICE_X30Y41 FDRE f u_cpu/u_csr/lladdr_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.679 -0.268 - clock pessimism -0.221 -0.489 - SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16] - ------------------------------------------------------------------- - required time 0.442 - arrival time -0.301 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%)) - Logic Levels: 0 - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.269ns - Source Clock Delay (SCD): -0.504ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.345 -0.504 - SLICE_X32Y40 FDRE 0.000 -0.504 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q - net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9] - SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.678 -0.269 - clock pessimism -0.196 -0.465 - SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9] - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.244 - ------------------------------------------------------------------- - slack 0.143 - -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%)) - Logic Levels: 0 - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.269ns - Source Clock Delay (SCD): -0.504ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.345 -0.504 - SLICE_X32Y40 FDRE 0.000 -0.504 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q - net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9] - SLICE_X31Y39 FDRE f u_cpu/u_csr/lladdr_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.678 -0.269 - clock pessimism -0.196 -0.465 - SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9] - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.244 - ------------------------------------------------------------------- - slack 0.143 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%)) - Logic Levels: 0 - Clock Path Skew: 0.035ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.282ns - Source Clock Delay (SCD): -0.513ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.336 -0.513 - SLICE_X27Y26 FDRE 0.000 -0.513 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q - net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46] - SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.665 -0.282 - clock pessimism -0.196 -0.478 - SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82] - ------------------------------------------------------------------- - required time 0.407 - arrival time -0.259 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%)) - Logic Levels: 0 - Clock Path Skew: 0.035ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.282ns - Source Clock Delay (SCD): -0.513ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.336 -0.513 - SLICE_X27Y26 FDRE 0.000 -0.513 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 f u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q - net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46] - SLICE_X28Y26 FDRE f u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.665 -0.282 - clock pessimism -0.196 -0.478 - SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82] - ------------------------------------------------------------------- - required time 0.407 - arrival time -0.259 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1 - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1 - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.524ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.468ns (logic 0.227ns (48.556%) route 0.241ns (51.444%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.187 -0.103 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X17Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.605 -0.342 - clock pessimism -0.192 -0.534 - SLICE_X17Y86 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3] - ------------------------------------------------------------------- - required time 0.626 - arrival time -0.103 - ------------------------------------------------------------------- - slack 0.524 - -Slack (MET) : 0.548ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.227ns (48.316%) route 0.243ns (51.684%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.189 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X15Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.605 -0.342 - clock pessimism -0.214 -0.556 - SLICE_X15Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.648 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.648 - arrival time -0.101 - ------------------------------------------------------------------- - slack 0.548 - -Slack (MET) : 0.558ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X14Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.620 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.620 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.558 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.650ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.622ns (logic 0.227ns (36.501%) route 0.395ns (63.499%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.341 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X16Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.192 -0.531 - SLICE_X16Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 0.598 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.650 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 - ------------------------------------------------------------------- - slack 0.800 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 - ------------------------------------------------------------------- - slack 0.800 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 - ------------------------------------------------------------------- - slack 0.800 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 - ------------------------------------------------------------------- - slack 0.800 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.824ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X121Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.824 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0] - ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg - ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.881ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X120Y70 FDCE (Remov_fdce_C_CLR) -0.067 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1] - ------------------------------------------------------------------- - required time 0.642 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.881 - -Slack (MET) : 0.881ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X120Y70 FDCE (Remov_fdce_C_CLR) -0.067 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2] - ------------------------------------------------------------------- - required time 0.642 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.881 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13] - ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.906 - -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21] - ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.906 - -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29] - ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.906 - -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5] - ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.906 - - - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization.rpt deleted file mode 100644 index ad58480..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization.rpt +++ /dev/null @@ -1,237 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:05 2026 -| Host : fedora running 64-bit unknown -| Command : report_utilization -file /home/fallensigh/vivado_reports_nodsp/utilization.rpt -| Design : soc_top -| Device : 7a200tfbg676-1 -| Design State : Routed ------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Slice Logic Distribution -3. Memory -4. DSP -5. IO and GT Specific -6. Clocking -7. Specific Feature -8. Primitives -9. Black Boxes -10. Instantiated Netlists - -1. Slice Logic --------------- - -+----------------------------+-------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------------------+-------+-------+-----------+-------+ -| Slice LUTs | 60995 | 0 | 133800 | 45.59 | -| LUT as Logic | 59140 | 0 | 133800 | 44.20 | -| LUT as Memory | 1855 | 0 | 46200 | 4.02 | -| LUT as Distributed RAM | 740 | 0 | | | -| LUT as Shift Register | 1115 | 0 | | | -| Slice Registers | 39931 | 0 | 267600 | 14.92 | -| Register as Flip Flop | 39931 | 0 | 267600 | 14.92 | -| Register as Latch | 0 | 0 | 267600 | 0.00 | -| F7 Muxes | 4480 | 0 | 66900 | 6.70 | -| F8 Muxes | 1556 | 0 | 33450 | 4.65 | -+----------------------------+-------+-------+-----------+-------+ - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 24 | Yes | - | Set | -| 26637 | Yes | - | Reset | -| 139 | Yes | Set | - | -| 13131 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Slice Logic Distribution ---------------------------- - -+--------------------------------------------+-------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+--------------------------------------------+-------+-------+-----------+-------+ -| Slice | 20066 | 0 | 33450 | 59.99 | -| SLICEL | 13210 | 0 | | | -| SLICEM | 6856 | 0 | | | -| LUT as Logic | 59140 | 0 | 133800 | 44.20 | -| using O5 output only | 2 | | | | -| using O6 output only | 49931 | | | | -| using O5 and O6 | 9207 | | | | -| LUT as Memory | 1855 | 0 | 46200 | 4.02 | -| LUT as Distributed RAM | 740 | 0 | | | -| using O5 output only | 0 | | | | -| using O6 output only | 60 | | | | -| using O5 and O6 | 680 | | | | -| LUT as Shift Register | 1115 | 0 | | | -| using O5 output only | 47 | | | | -| using O6 output only | 1008 | | | | -| using O5 and O6 | 60 | | | | -| Slice Registers | 39931 | 0 | 267600 | 14.92 | -| Register driven from within the Slice | 20433 | | | | -| Register driven from outside the Slice | 19498 | | | | -| LUT in front of the register is unused | 10788 | | | | -| LUT in front of the register is used | 8710 | | | | -| Unique Control Sets | 1304 | | 33450 | 3.90 | -+--------------------------------------------+-------+-------+-----------+-------+ -* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. - - -3. Memory ---------- - -+-------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 23.5 | 0 | 365 | 6.44 | -| RAMB36/FIFO* | 8 | 0 | 365 | 2.19 | -| RAMB36E1 only | 8 | | | | -| RAMB18 | 31 | 0 | 730 | 4.25 | -| RAMB18E1 only | 31 | | | | -+-------------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -4. DSP ------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| DSPs | 16 | 0 | 740 | 2.16 | -| DSP48E1 only | 16 | | | | -+----------------+------+-------+-----------+-------+ - - -5. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 202 | 202 | 400 | 50.50 | -| IOB Master Pads | 97 | | | | -| IOB Slave Pads | 102 | | | | -| Bonded IPADs | 0 | 0 | 26 | 0.00 | -| Bonded OPADs | 0 | 0 | 16 | 0.00 | -| PHY_CONTROL | 0 | 0 | 10 | 0.00 | -| PHASER_REF | 0 | 0 | 10 | 0.00 | -| OUT_FIFO | 0 | 0 | 40 | 0.00 | -| IN_FIFO | 0 | 0 | 40 | 0.00 | -| IDELAYCTRL | 0 | 0 | 10 | 0.00 | -| IBUFDS | 0 | 0 | 384 | 0.00 | -| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 | -| ILOGIC | 0 | 0 | 400 | 0.00 | -| OLOGIC | 0 | 0 | 400 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -6. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 4 | 0 | 32 | 12.50 | -| BUFIO | 0 | 0 | 40 | 0.00 | -| MMCME2_ADV | 0 | 0 | 10 | 0.00 | -| PLLE2_ADV | 1 | 0 | 10 | 10.00 | -| BUFMRCE | 0 | 0 | 20 | 0.00 | -| BUFHCE | 0 | 0 | 120 | 0.00 | -| BUFR | 0 | 0 | 40 | 0.00 | -+------------+------+-------+-----------+-------+ - - -7. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -8. Primitives -------------- - -+-----------+-------+---------------------+ -| Ref Name | Used | Functional Category | -+-----------+-------+---------------------+ -| LUT6 | 35413 | LUT | -| FDCE | 26637 | Flop & Latch | -| FDRE | 13131 | Flop & Latch | -| LUT3 | 9384 | LUT | -| LUT5 | 8477 | LUT | -| LUT4 | 7294 | LUT | -| LUT2 | 6978 | LUT | -| MUXF7 | 4480 | MuxFx | -| CARRY4 | 2859 | CarryLogic | -| MUXF8 | 1556 | MuxFx | -| RAMD32 | 1060 | Distributed Memory | -| SRLC32E | 992 | Distributed Memory | -| LUT1 | 801 | LUT | -| RAMS32 | 328 | Distributed Memory | -| SRL16E | 183 | Distributed Memory | -| FDSE | 139 | Flop & Latch | -| IBUF | 104 | IO | -| OBUF | 98 | IO | -| OBUFT | 66 | IO | -| RAMD64E | 32 | Distributed Memory | -| RAMB18E1 | 31 | Block Memory | -| FDPE | 24 | Flop & Latch | -| DSP48E1 | 16 | Block Arithmetic | -| RAMB36E1 | 8 | Block Memory | -| BUFG | 4 | Clock | -| PLLE2_ADV | 1 | Clock | -+-----------+-------+---------------------+ - - -9. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -10. Instantiated Netlists -------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ -| clk_pll | 1 | -+----------+------+ - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization_hier.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization_hier.rpt deleted file mode 100644 index 9abba2a..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization_hier.rpt +++ /dev/null @@ -1,276 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:06 2026 -| Host : fedora running 64-bit unknown -| Command : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_nodsp/utilization_hier.rpt -| Design : soc_top -| Device : 7a200tfbg676-1 -| Design State : Routed -------------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Utilization by Hierarchy - -1. Utilization by Hierarchy ---------------------------- - -+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ -| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks | -+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ -| soc_top | (top) | 60995 | 59140 | 740 | 1115 | 39931 | 8 | 31 | 16 | -| (soc_top) | (top) | 878 | 822 | 56 | 0 | 4 | 0 | 0 | 0 | -| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| inst | clk_pll__clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | -| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 459 | 459 | 0 | 0 | 151 | 0 | 0 | 0 | -| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 6 | 6 | 0 | 0 | 24 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_82 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_65 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_81 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_66 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_80 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_67 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_79 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 | -| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_76 | 27 | 27 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_77 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3_78 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_73 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_74 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3_75 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 | -| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_70 | 20 | 20 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_71 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3_72 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 23 | 23 | 0 | 0 | 11 | 0 | 0 | 0 | -| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 96 | 96 | 0 | 0 | 25 | 0 | 0 | 0 | -| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 75 | 75 | 0 | 0 | 12 | 0 | 0 | 0 | -| errorSlave | Axi4ReadOnlyErrorSlave_1_69 | 21 | 21 | 0 | 0 | 13 | 0 | 0 | 0 | -| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 40 | 40 | 0 | 0 | 18 | 0 | 0 | 0 | -| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 | -| errorSlave | Axi4WriteOnlyErrorSlave_1_68 | 21 | 21 | 0 | 0 | 2 | 0 | 0 | 0 | -| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 133 | 133 | 0 | 0 | 17 | 0 | 0 | 0 | -| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 118 | 118 | 0 | 0 | 8 | 0 | 0 | 0 | -| errorSlave | Axi4ReadOnlyErrorSlave_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 | -| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 30 | 30 | 0 | 0 | 14 | 0 | 0 | 0 | -| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 | -| errorSlave | Axi4WriteOnlyErrorSlave_1 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 | -| u_Axi_CDC | Axi_CDC | 410 | 282 | 128 | 0 | 317 | 0 | 0 | 0 | -| arFifo | StreamFifoCC_3_48 | 181 | 145 | 36 | 0 | 77 | 0 | 0 | 0 | -| (arFifo) | StreamFifoCC_3_48 | 176 | 140 | 36 | 0 | 65 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9_63 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11_64 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| awFifo | StreamFifoCC_49 | 103 | 67 | 36 | 0 | 79 | 0 | 0 | 0 | -| (awFifo) | StreamFifoCC_49 | 99 | 63 | 36 | 0 | 65 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_10_60 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9_61 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11_62 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| bFifo | StreamFifoCC_2_50 | 15 | 15 | 0 | 0 | 26 | 0 | 0 | 0 | -| (bFifo) | StreamFifoCC_2_50 | 8 | 8 | 0 | 0 | 12 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_5_57 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_4_58 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_6_59 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| rFifo | StreamFifoCC_4_51 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 | -| (rFifo) | StreamFifoCC_4_51 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_55 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_1_56 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| wFifo | StreamFifoCC_1_52 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 | -| (wFifo) | StreamFifoCC_1_52 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_7_53 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_8_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| u_axi_axil_adapter | axi_axil_adapter | 1073 | 1073 | 0 | 0 | 173 | 0 | 0 | 0 | -| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 498 | 498 | 0 | 0 | 85 | 0 | 0 | 0 | -| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 575 | 575 | 0 | 0 | 88 | 0 | 0 | 0 | -| u_axi_dvi | axi_dvi | 283 | 283 | 0 | 0 | 211 | 0 | 0 | 0 | -| u_axi_ram | axi_wrap_ram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 | -| u_axi_sram_sp | axi2sram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 | -| u_axi_uart_controller | axi_uart_controller | 683 | 667 | 16 | 0 | 457 | 0 | 0 | 0 | -| AA_axi2apb_bridge_cpu | axi2apb_bridge | 251 | 251 | 0 | 0 | 120 | 0 | 0 | 0 | -| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 | -| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 | -| (regs) | uart_regs | 119 | 119 | 0 | 0 | 155 | 0 | 0 | 0 | -| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | -| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 | -| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 | -| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 | -| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 | -| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 | -| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 | -| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 | -| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 | -| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 | -| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 | -| u_cdma_matmul_bridge | cdma_matmul_bridge | 251 | 251 | 0 | 0 | 578 | 0 | 0 | 0 | -| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 | -| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 | -| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 | -| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 | -| u_cpu | core_top | 8551 | 8299 | 252 | 0 | 5591 | 0 | 20 | 0 | -| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 | -| addr_trans | addr_trans | 2247 | 2107 | 140 | 0 | 1244 | 0 | 0 | 0 | -| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 | -| tlb_entry | tlb_entry | 2247 | 2107 | 140 | 0 | 1204 | 0 | 0 | 0 | -| axi_bridge | axi_bridge | 40 | 40 | 0 | 0 | 214 | 0 | 0 | 0 | -| btb | btb | 1046 | 966 | 80 | 0 | 1611 | 0 | 0 | 0 | -| (btb) | btb | 1044 | 964 | 80 | 0 | 1611 | 0 | 0 | 0 | -| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | -| dcache | dcache | 552 | 520 | 32 | 0 | 146 | 0 | 10 | 0 | -| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 | -| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 | -| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 | -| tagv_ram_way[1].u | tagv_sram_46 | 41 | 41 | 0 | 0 | 0 | 0 | 1 | 0 | -| exe_stage | exe_stage | 663 | 663 | 0 | 0 | 233 | 0 | 0 | 0 | -| (exe_stage) | exe_stage | 632 | 632 | 0 | 0 | 233 | 0 | 0 | 0 | -| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | -| icache | icache | 235 | 235 | 0 | 0 | 55 | 0 | 10 | 0 | -| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 | -| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 | -| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 | -| tagv_ram_way[1].u | tagv_sram_35 | 87 | 87 | 0 | 0 | 0 | 0 | 1 | 0 | -| id_stage | id_stage | 1054 | 1054 | 0 | 0 | 108 | 0 | 0 | 0 | -| if_stage | if_stage | 135 | 135 | 0 | 0 | 173 | 0 | 0 | 0 | -| mem_stage | mem_stage | 116 | 116 | 0 | 0 | 211 | 0 | 0 | 0 | -| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 | -| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 | -| u_mul | mul | 936 | 936 | 0 | 0 | 592 | 0 | 0 | 0 | -| wb_stage | wb_stage | 680 | 680 | 0 | 0 | 233 | 0 | 0 | 0 | -| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 36148 | 34927 | 112 | 1109 | 27165 | 8 | 10 | 16 | -| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| u_fft_controller | fft_controller | 2646 | 1606 | 0 | 1040 | 1083 | 6 | 4 | 16 | -| (u_fft_controller) | fft_controller | 123 | 123 | 0 | 0 | 100 | 0 | 0 | 0 | -| u_FFT | FFT | 2496 | 1456 | 0 | 1040 | 983 | 6 | 0 | 16 | -| SU1 | SdfUnit | 1071 | 303 | 0 | 768 | 197 | 2 | 0 | 4 | -| (SU1) | SdfUnit | 205 | 205 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_25 | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | -| DB1 | DelayBuffer | 562 | 50 | 0 | 512 | 32 | 0 | 0 | 0 | -| DB2 | DelayBuffer__parameterized0 | 256 | 0 | 0 | 256 | 32 | 0 | 0 | 0 | -| MU | Multiply_26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | -| TW | Twiddle_27 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | -| SU2 | SdfUnit__parameterized0 | 492 | 300 | 0 | 192 | 197 | 2 | 0 | 4 | -| (SU2) | SdfUnit__parameterized0 | 73 | 73 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 | -| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 | -| MU | Multiply_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 | -| TW | Twiddle_23 | 3 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | -| SU3 | SdfUnit__parameterized1 | 346 | 298 | 0 | 48 | 197 | 0 | 0 | 4 | -| (SU3) | SdfUnit__parameterized1 | 74 | 74 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 | -| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 | -| MU | Multiply_19 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 | -| SU4 | SdfUnit__parameterized2 | 327 | 295 | 0 | 32 | 197 | 2 | 0 | 4 | -| (SU4) | SdfUnit__parameterized2 | 69 | 69 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_15 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 | -| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 | -| MU | Multiply | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 | -| TW | Twiddle | 2 | 2 | 0 | 0 | 0 | 2 | 0 | 0 | -| SU5 | SdfUnit__parameterized3 | 260 | 260 | 0 | 0 | 195 | 0 | 0 | 0 | -| (SU5) | SdfUnit__parameterized3 | 68 | 68 | 0 | 0 | 99 | 0 | 0 | 0 | -| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 | -| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 | -| u_in0 | my_bram0 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_in1 | my_bram0_12 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_out0 | my_bram0_13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_out1 | my_bram0_14 | 25 | 25 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_mlkem_axi_cdc | Axi_CDC_5 | 421 | 309 | 112 | 0 | 272 | 0 | 0 | 0 | -| arFifo | StreamFifoCC_3 | 53 | 25 | 28 | 0 | 55 | 0 | 0 | 0 | -| (arFifo) | StreamFifoCC_3 | 44 | 16 | 28 | 0 | 43 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9_10 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| awFifo | StreamFifoCC | 40 | 16 | 24 | 0 | 49 | 0 | 0 | 0 | -| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 | -| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | -| rFifo | StreamFifoCC_4 | 57 | 29 | 28 | 0 | 72 | 0 | 0 | 0 | -| (rFifo) | StreamFifoCC_4 | 49 | 21 | 28 | 0 | 56 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | -| wFifo | StreamFifoCC_1 | 253 | 225 | 28 | 0 | 69 | 0 | 0 | 0 | -| (wFifo) | StreamFifoCC_1 | 248 | 220 | 28 | 0 | 53 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| u_mlkem_axi_slave | mlkem_axi_slave | 33082 | 33013 | 0 | 69 | 25804 | 2 | 6 | 0 | -| (u_mlkem_axi_slave) | mlkem_axi_slave | 1202 | 1202 | 0 | 0 | 1068 | 0 | 0 | 0 | -| u_mlkem | mlkem_top | 31884 | 31815 | 0 | 69 | 24736 | 2 | 6 | 0 | -| (u_mlkem) | mlkem_top | 2738 | 2738 | 0 | 0 | 4960 | 0 | 0 | 0 | -| u_bank_a | sd_bram__parameterized0 | 50 | 50 | 0 | 0 | 0 | 1 | 1 | 0 | -| u_bank_se | sd_bram__parameterized1 | 70 | 70 | 0 | 0 | 0 | 1 | 0 | 0 | -| u_bank_t | sd_bram__parameterized2 | 654 | 654 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_c_in_bram | sd_bram | 1312 | 1312 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_cbd | sample_cbd_sync_shared | 2741 | 2741 | 0 | 0 | 3186 | 0 | 0 | 0 | -| u_comp | comp_decomp_sync | 467 | 466 | 0 | 1 | 323 | 0 | 0 | 0 | -| u_ct_bram | sd_bram_6 | 13 | 13 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_dkp_bram | sd_bram_7 | 82 | 82 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_ek_bram | sd_bram_8 | 2121 | 2121 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_keccak | keccak_core | 5274 | 5274 | 0 | 0 | 1606 | 0 | 0 | 0 | -| u_ntt | ntt_core | 8625 | 8582 | 0 | 43 | 3861 | 0 | 0 | 0 | -| (u_ntt) | ntt_core | 6101 | 6085 | 0 | 16 | 3358 | 0 | 0 | 0 | -| u_bf | butterfly_unit_pipe | 2260 | 2234 | 0 | 26 | 286 | 0 | 0 | 0 | -| (u_bf) | butterfly_unit_pipe | 69 | 44 | 0 | 25 | 75 | 0 | 0 | 0 | -| u_barrett | barrett_mul_pipe_9 | 2192 | 2191 | 0 | 1 | 211 | 0 | 0 | 0 | -| u_scl | barrett_mul_pipe | 265 | 264 | 0 | 1 | 217 | 0 | 0 | 0 | -| u_pmul | poly_mul_sync | 3881 | 3856 | 0 | 25 | 6743 | 0 | 0 | 0 | -| (u_pmul) | poly_mul_sync | 2434 | 2434 | 0 | 0 | 6280 | 0 | 0 | 0 | -| u_bc | basecase_mul_pipe | 1447 | 1422 | 0 | 25 | 463 | 0 | 0 | 0 | -| u_sha3 | sha3_top_shared | 1766 | 1766 | 0 | 0 | 2388 | 0 | 0 | 0 | -| u_snt | sample_ntt_sync_shared | 2109 | 2109 | 0 | 0 | 1669 | 0 | 0 | 0 | -| u_matmul_axi_slave | matmul_axi_slave | 9758 | 9576 | 176 | 6 | 3248 | 0 | 0 | 0 | -| (u_matmul_axi_slave) | matmul_axi_slave | 5637 | 5455 | 176 | 6 | 2480 | 0 | 0 | 0 | -| mult_inst[0].u_mult | pipelined_mult_32x32 | 1063 | 1063 | 0 | 0 | 192 | 0 | 0 | 0 | -| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 999 | 999 | 0 | 0 | 192 | 0 | 0 | 0 | -| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 | -| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 | -| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1788 | 1788 | 0 | 0 | 1476 | 0 | 1 | 0 | -| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 751 | 751 | 0 | 0 | 1180 | 0 | 0 | 0 | -| u_core_engine | snix_axi_mm2mm | 1038 | 1038 | 0 | 0 | 296 | 0 | 1 | 0 | -| (u_core_engine) | snix_axi_mm2mm | 762 | 762 | 0 | 0 | 243 | 0 | 0 | 0 | -| axis_fifo_u0 | snix_axis_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 | -| u_fifo | snix_sync_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 | -+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ -* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining - - diff --git a/rtl/ip/PLL_2019_2/.gitignore b/rtl/ip/PLL_2019_2/.gitignore deleted file mode 100644 index 3fbcd97..0000000 --- a/rtl/ip/PLL_2019_2/.gitignore +++ /dev/null @@ -1 +0,0 @@ -PLL_* diff --git a/rtl/ip/PLL_2019_2/clk_pll.xci b/rtl/ip/PLL_2019_2/clk_pll.xci index 113f373..92ef6f9 100644 --- a/rtl/ip/PLL_2019_2/clk_pll.xci +++ b/rtl/ip/PLL_2019_2/clk_pll.xci @@ -35,12 +35,6 @@ 100000000 0 0.000 - - - - 100000000 - 0 - 0.000 1 LEVEL_HIGH @@ -104,14 +98,14 @@ 100.0 0000 0000 - 32.97872 + 33.33333 0000 0000 50.00000 BUFG 50.0 false - 32.97872 + 33.33333 0.000 50.000 33.000 @@ -119,7 +113,7 @@ 1 0000 0000 - 50.00000 + 76.92308 BUFG 50.0 false @@ -136,13 +130,13 @@ BUFG 50.0 false - 50.00000 + 76.92308 0.000 50.000 - 50 + 100.000 0.000 1 - 1 + 0 0000 0000 100.000 @@ -210,7 +204,7 @@ 0000 1 0.66 - 0.66 + 0.33 0.33 0.33 0.33 @@ -252,20 +246,24 @@ false false OPTIMIZED - 31.000 + 20.000 0.000 FALSE 20.000 10.0 - 47.000 + 30.000 0.500 0.000 FALSE - 31 + 20 0.500 0.000 FALSE - 31 +<<<<<<< Updated upstream + 1 +======= + 13 +>>>>>>> Stashed changes 0.500 0.000 FALSE @@ -295,17 +293,23 @@ FALSE 64.000 2.000 - 3 + 2 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +<<<<<<< Updated upstream _cpu_clk__32.97872______0.000______50.0______130.093____123.600 _sys_clk__50.00000______0.000______50.0______122.035____123.600 - mlkem_clk__50.00000______0.000______50.0______122.035____123.600 + no_CLK_OUT3_output +======= + _cpu_clk__33.33333______0.000______50.0______215.691____164.985 + _sys_clk__50.00000______0.000______50.0______192.113____164.985 + mlkem_clk__76.92308______0.000______50.0______172.249____164.985 +>>>>>>> Stashed changes no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output - 0 + 1 0 128.000 1.000 @@ -438,14 +442,14 @@ 1 true BUFG - 122.035 + 110.420 false 123.600 50.000 - 50 + 100.000 0.000 1 - true + false BUFG 0.0 false @@ -531,20 +535,24 @@ No_Jitter locked OPTIMIZED - 31 + 20 0.000 false 20.000 10.0 - 47 + 30 0.500 0.000 false - 31 + 20 0.500 0.000 false - 31 +<<<<<<< Updated upstream + 1 +======= + 13 +>>>>>>> Stashed changes 0.500 0.000 false @@ -572,8 +580,13 @@ 0.010 0.010 false - 3 +<<<<<<< Updated upstream + 2 false +======= + 3 + true +>>>>>>> Stashed changes false WAVEFORM false @@ -722,6 +735,9 @@ + + + @@ -731,6 +747,7 @@ + diff --git a/sdk/software/examples/mlkem_test/result.txt b/sdk/software/examples/mlkem_test/result.txt new file mode 100644 index 0000000..af9dd98 --- /dev/null +++ b/sdk/software/examples/mlkem_test/result.txt @@ -0,0 +1,97 @@ +MLKEM_START +MLKEM_INPUTS=STATIC_KAT_COUNT_0 +MLKEM_LEVELS=k2,k3,k4 +MLKEM_DIAG_MODE=isolated_sw_cpu_dma +MLKEM_DIAG_ITERS=100 + +============================================================ +ML-KEM-512 isolated diagnostic (k=2) +EK=800 bytes, DK=1632 bytes, CT=768 bytes +EXPECT_EK32=80b70100831d7ee168f47392483119f93863ecb0bc605312d35728876b00f5f5 +EXPECT_CT32=917e59d1e182a29648a61955a154b304a842f458eba593f3065fb7d744fba24f +EXPECT_SS=2b5c52ee72946331983ba050be0f435055c0547901e03559b356517889ea27c5 +MLKEM512_SW_ONLY_BEGIN iters=100 +MLKEM512_SW_ONLY_ITERS=100 +MLKEM512_SW_ONLY_FAILS=0 +MLKEM512_SW_ONLY_AVG_CYCLES=2594034 +MLKEM512_SW_ONLY_AVG_US=78607 +MLKEM512_SW_ONLY_RESULT=PASS +MLKEM512_SW_ONLY_END +MLKEM512_CPU_ONLY_BEGIN iters=100 +MLKEM512_CPU_ONLY_ITERS=100 +MLKEM512_CPU_ONLY_FAILS=0 +MLKEM512_CPU_ONLY_AVG_CYCLES=200471 +MLKEM512_CPU_ONLY_AVG_US=6074 +MLKEM512_CPU_ONLY_RESULT=PASS +MLKEM512_CPU_ONLY_END +MLKEM512_DMA_ONLY_BEGIN iters=100 +MLKEM512_DMA_ONLY_ITERS=100 +MLKEM512_DMA_ONLY_FAILS=0 +MLKEM512_DMA_ONLY_AVG_CYCLES=52995 +MLKEM512_DMA_ONLY_AVG_US=1605 +MLKEM512_DMA_ONLY_RESULT=PASS +MLKEM512_DMA_ONLY_END +MLKEM512_ISOLATED_FAILS=0 +MLKEM512_RESULT=PASS + +============================================================ +ML-KEM-768 isolated diagnostic (k=3) +EK=1184 bytes, DK=2400 bytes, CT=1088 bytes +EXPECT_EK32=01f60af1dc8e6360ae78b59d4a5042eb9145a269046d6236b8304f305c2d9dcb +EXPECT_CT32=16a61ff84787fd4a5f19ca59b3657db3a106a7329e2d62747a2ef85149163109 +EXPECT_SS=b408d5d115713f0a93047dbbea832e4340787686d59a9a2d106bd662ba0aa035 +MLKEM768_SW_ONLY_BEGIN iters=100 +MLKEM768_SW_ONLY_ITERS=100 +MLKEM768_SW_ONLY_FAILS=0 +MLKEM768_SW_ONLY_AVG_CYCLES=4065123 +MLKEM768_SW_ONLY_AVG_US=123185 +MLKEM768_SW_ONLY_RESULT=PASS +MLKEM768_SW_ONLY_END +MLKEM768_CPU_ONLY_BEGIN iters=100 +MLKEM768_CPU_ONLY_ITERS=100 +MLKEM768_CPU_ONLY_FAILS=0 +MLKEM768_CPU_ONLY_AVG_CYCLES=296193 +MLKEM768_CPU_ONLY_AVG_US=8975 +MLKEM768_CPU_ONLY_RESULT=PASS +MLKEM768_CPU_ONLY_END +MLKEM768_DMA_ONLY_BEGIN iters=100 +MLKEM768_DMA_ONLY_ITERS=100 +MLKEM768_DMA_ONLY_FAILS=0 +MLKEM768_DMA_ONLY_AVG_CYCLES=80648 +MLKEM768_DMA_ONLY_AVG_US=2443 +MLKEM768_DMA_ONLY_RESULT=PASS +MLKEM768_DMA_ONLY_END +MLKEM768_ISOLATED_FAILS=0 +MLKEM768_RESULT=PASS + +============================================================ +ML-KEM-1024 isolated diagnostic (k=4) +EK=1568 bytes, DK=3168 bytes, CT=1568 bytes +EXPECT_EK32=a8122f376b3f5d355263eba522c43995044beca78b9ba9924b87035490ae78a9 +EXPECT_CT32=707d18cabcf89670c80003b47d2b8678ad0da4aaad781a3351e82ac3e447e701 +EXPECT_SS=23f211b84a6ee20c8c29f6e5314c91b414e940513d380add17bd724ab3a13a52 +MLKEM1024_SW_ONLY_BEGIN iters=100 +MLKEM1024_SW_ONLY_ITERS=100 +MLKEM1024_SW_ONLY_FAILS=0 +MLKEM1024_SW_ONLY_AVG_CYCLES=6041204 +MLKEM1024_SW_ONLY_AVG_US=183066 +MLKEM1024_SW_ONLY_RESULT=PASS +MLKEM1024_SW_ONLY_END +MLKEM1024_CPU_ONLY_BEGIN iters=100 +MLKEM1024_CPU_ONLY_ITERS=100 +MLKEM1024_CPU_ONLY_FAILS=0 +MLKEM1024_CPU_ONLY_AVG_CYCLES=404476 +MLKEM1024_CPU_ONLY_AVG_US=12256 +MLKEM1024_CPU_ONLY_RESULT=PASS +MLKEM1024_CPU_ONLY_END +MLKEM1024_DMA_ONLY_BEGIN iters=100 +MLKEM1024_DMA_ONLY_ITERS=100 +MLKEM1024_DMA_ONLY_FAILS=0 +MLKEM1024_DMA_ONLY_AVG_CYCLES=113273 +MLKEM1024_DMA_ONLY_AVG_US=3432 +MLKEM1024_DMA_ONLY_RESULT=PASS +MLKEM1024_DMA_ONLY_END +MLKEM1024_ISOLATED_FAILS=0 +MLKEM1024_RESULT=PASS +MLKEM_RESULT=PASS +MLKEM_DONE